controller/dwc/pci-layerscape.c

26 #include "pcie-designware.h"
72 #define ls_pcie_pf_lut_readl_addr(addr)	ls_pcie_pf_lut_readl(pcie, addr)
75 static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
77 	struct dw_pcie *pci = pcie->pci;
87 static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
89 	struct dw_pcie *pci = pcie->pci;
95 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
98 	struct dw_pcie *pci = pcie->pci;
106 static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
108 	struct dw_pcie *pci = pcie->pci;
113 static u32 ls_pcie_pf_lut_readl(struct ls_pcie *pcie, u32 off)
115 	if (pcie->big_endian)
116 		return ioread32be(pcie->pf_lut_base + off);
118 	return ioread32(pcie->pf_lut_base + off);
121 static void ls_pcie_pf_lut_writel(struct ls_pcie *pcie, u32 off, u32 val)
123 	if (pcie->big_endian)
124 		iowrite32be(val, pcie->pf_lut_base + off);
126 		iowrite32(val, pcie->pf_lut_base + off);
132 	struct ls_pcie *pcie = to_ls_pcie(pci);
136 	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR);
138 	ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val);
145 		dev_err(pcie->pci->dev, "PME_Turn_off timeout\n");
151 	struct ls_pcie *pcie = to_ls_pcie(pci);
159 	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR);
161 	ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val);
172 		dev_err(pcie->pci->dev, "L2 exit timeout\n");
180 	struct ls_pcie *pcie = to_ls_pcie(pci);
182 	ls_pcie_fix_error_response(pcie);
185 	ls_pcie_clear_multifunction(pcie);
188 	ls_pcie_drop_msg_tlp(pcie);
214 	struct ls_pcie *pcie = to_ls_pcie(pci);
216 	scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), PMXMTTURNOFF);
231 	struct ls_pcie *pcie = to_ls_pcie(pci);
233 	return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index));
239 	struct ls_pcie *pcie = to_ls_pcie(pci);
241 	scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMECR, PEXPME(pcie->index));
247 	struct ls_pcie *pcie = to_ls_pcie(pci);
256 	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
258 	ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
260 	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
262 	ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
264 	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
266 	ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
268 	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
270 	ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
313 	{ .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata },
314 	{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata },
315 	{ .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata },
316 	{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043a_drvdata },
317 	{ .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata },
318 	{ .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata },
319 	{ .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata },
320 	{ .compatible = "fsl,ls2088a-pcie", .data = &layerscape_drvdata },
321 	{ .compatible = "fsl,ls1088a-pcie", .data = &layerscape_drvdata },
329 	struct ls_pcie *pcie;
334 	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
335 	if (!pcie)
342 	pcie->drvdata = of_device_get_match_data(dev);
345 	pcie->pci = pci;
346 	pci->pp.ops = pcie->drvdata->ops;
353 	pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian");
355 	pcie->pf_lut_base = pci->dbi_base + pcie->drvdata->pf_lut_off;
357 	if (pcie->drvdata->scfg_support) {
358 		pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg");
359 		if (IS_ERR(pcie->scfg)) {
361 			return PTR_ERR(pcie->scfg);
364 		ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", index, 2);
368 		pcie->index = index[1];
371 	if (!ls_pcie_is_bridge(pcie))
374 	platform_set_drvdata(pdev, pcie);
381 	struct ls_pcie *pcie = dev_get_drvdata(dev);
383 	if (!pcie->drvdata->pm_support)
386 	return dw_pcie_suspend_noirq(pcie->pci);
391 	struct ls_pcie *pcie = dev_get_drvdata(dev);
394 	if (!pcie->drvdata->pm_support)
397 	ret = pcie->drvdata->exit_from_l2(&pcie->pci->pp);
401 	return dw_pcie_resume_noirq(pcie->pci);
411 		.name = "layerscape-pcie",