controller/cadence/pcie-cadence-host.c

219 					enum cdns_pcie_rp_bar bar,
226 	if (!rc->avail_ib_bar[bar])
229 	rc->avail_ib_bar[bar] = false;
235 	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar), addr0);
236 	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar), addr1);
238 	if (bar == RP_NO_BAR)
242 	value &= ~(LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) |
243 		   LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) |
244 		   LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) |
245 		   LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) |
246 		   LM_RC_BAR_CFG_APERTURE(bar, bar_aperture_mask[bar] + 2));
249 			value |= LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar);
250 		value |= LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar);
253 			value |= LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar);
254 		value |= LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar);
257 	value |= LM_RC_BAR_CFG_APERTURE(bar, aperture);
266 	enum cdns_pcie_rp_bar bar, sel_bar;
269 	for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) {
270 		if (!rc->avail_ib_bar[bar])
273 		if (size <= bar_max_size[bar]) {
275 				sel_bar = bar;
279 			if (bar_max_size[bar] < bar_max_size[sel_bar])
280 				sel_bar = bar;
290 	enum cdns_pcie_rp_bar bar, sel_bar;
293 	for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) {
294 		if (!rc->avail_ib_bar[bar])
297 		if (size >= bar_max_size[bar]) {
299 				sel_bar = bar;
303 			if (bar_max_size[bar] > bar_max_size[sel_bar])
304 				sel_bar = bar;
317 	enum cdns_pcie_rp_bar bar;
341 		bar = cdns_pcie_host_find_min_bar(rc, size);
342 		if (bar != RP_BAR_UNDEFINED) {
343 			ret = cdns_pcie_host_bar_ib_config(rc, bar, cpu_addr,
346 				dev_err(dev, "IB BAR: %d config failed\n", bar);
361 		bar = cdns_pcie_host_find_max_bar(rc, size);
362 		if (bar == RP_BAR_UNDEFINED) {
368 		winsize = bar_max_size[bar];
369 		ret = cdns_pcie_host_bar_ib_config(rc, bar, cpu_addr, winsize,
372 			dev_err(dev, "IB BAR: %d config failed\n", bar);
409 		of_property_read_u32(np, "cdns,no-bar-match-nbits",
506 	enum cdns_pcie_rp_bar bar;
551 	for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++)
552 		rc->avail_ib_bar[bar] = true;