Lines Matching refs:t7xx_dev
54 20000000, false, IREG_BASE(md->t7xx_dev) + \
125 struct device *dev = &ctl->md->t7xx_dev->pdev->dev;
179 struct device *dev = &ctl->md->t7xx_dev->pdev->dev;
198 t7xx_pci_pm_exp_detected(ctl->md->t7xx_dev);
220 value = ioread32(IREG_BASE(md->t7xx_dev) + T7XX_PCIE_MISC_DEV_STATUS);
223 iowrite32(value, IREG_BASE(md->t7xx_dev) + T7XX_PCIE_MISC_DEV_STATUS);
234 dev = &md->t7xx_dev->pdev->dev;
254 t7xx_mode_update(md->t7xx_dev, T7XX_FASTBOOT_DOWNLOAD);
256 t7xx_mode_update(md->t7xx_dev, T7XX_FASTBOOT_DUMP);
270 return t7xx_md_reset(ctl->md->t7xx_dev);
286 struct t7xx_pci_dev *t7xx_dev = ctl->md->t7xx_dev;
287 enum t7xx_mode mode = READ_ONCE(t7xx_dev->mode);
302 t7xx_mhccif_h2d_swint_trigger(t7xx_dev, H2D_CH_DRM_DISABLE_AP);
307 t7xx_mhccif_h2d_swint_trigger(t7xx_dev, H2D_CH_DEVICE_RESET);
309 err = t7xx_acpi_fldr_func(t7xx_dev);
311 t7xx_mhccif_h2d_swint_trigger(t7xx_dev, H2D_CH_DEVICE_RESET);
334 t7xx_mode_update(md->t7xx_dev, T7XX_READY);
351 dev = &md->t7xx_dev->pdev->dev;
372 t7xx_pci_pm_init_late(md->t7xx_dev);
393 dev = &md->t7xx_dev->pdev->dev;
422 t7xx_mhccif_mask_clr(md->t7xx_dev, D2H_INT_PORT_ENUM |
530 struct device *dev = &ctl->md->t7xx_dev->pdev->dev;
616 struct device *dev = &md->t7xx_dev->pdev->dev;