wwan/t7xx/t7xx_cldma.c

34 	iowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_IP_BUSY);
57 	iowrite32(ul_cfg, hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
59 	iowrite32(UL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_UL_MEM);
60 	iowrite32(DL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_DL_MEM);
72 	iowrite32(val, reg);
78 	iowrite32(TXRX_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0);
79 	iowrite32(TXRX_STATUS_BITMASK, hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0);
81 	iowrite32(EMPTY_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0);
82 	iowrite32(EMPTY_STATUS_BITMASK, hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0);
91 	iowrite32(val, ao_base + REG_INFRA_RST2_SET);
94 	iowrite32(val, ao_base + REG_INFRA_RST4_SET);
99 	iowrite32(val, ao_base + REG_INFRA_RST4_CLR);
102 	iowrite32(val, ao_base + REG_INFRA_RST2_CLR);
129 		iowrite32(BIT(qno), base + REG_CLDMA_DL_RESUME_CMD);
131 		iowrite32(BIT(qno), base + REG_CLDMA_UL_RESUME_CMD);
155 	iowrite32(ch_id, hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);
166 	iowrite32(ch_id, hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);
191 	iowrite32(val, reg);
202 	iowrite32(val << EQ_STA_BIT_OFFSET, reg);
214 	iowrite32(val, reg);
225 	iowrite32(val << EQ_STA_BIT_OFFSET, reg);
255 	iowrite32(ul_cfg, hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
257 	iowrite32(dl_cfg, hw_info->ap_ao_base + REG_CLDMA_DL_CFG);
258 	iowrite32(0, hw_info->ap_ao_base + REG_CLDMA_INT_MASK);
259 	iowrite32(BUSY_MASK_MD, hw_info->ap_ao_base + REG_CLDMA_BUSY_MASK);
260 	iowrite32(UL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_UL_MEM);
261 	iowrite32(DL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_DL_MEM);
270 	iowrite32(CLDMA_ALL_Q, reg);
279 	iowrite32(TXRX_STATUS_BITMASK, reg);
280 	iowrite32(EMPTY_STATUS_BITMASK, reg);