Lines Matching refs:wl
661 static int wl18xx_identify_chip(struct wl1271 *wl)
665 switch (wl->chip.id) {
668 wl->chip.id);
669 wl->sr_fw_name = WL18XX_FW_NAME;
671 wl->plt_fw_name = WL18XX_FW_NAME;
672 wl->quirks |= WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN |
679 wlcore_set_min_fw_ver(wl, WL18XX_CHIP_VER,
687 wl->chip.id);
692 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
697 wl->fw_mem_block_size = 272;
698 wl->fwlog_end = 0x40000000;
700 wl->scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4;
701 wl->scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5;
702 wl->sched_scan_templ_id_2_4 = CMD_TEMPL_PROBE_REQ_2_4_PERIODIC;
703 wl->sched_scan_templ_id_5 = CMD_TEMPL_PROBE_REQ_5_PERIODIC;
704 wl->max_channels_5 = WL18XX_MAX_CHANNELS_5GHZ;
705 wl->ba_rx_session_count_max = WL18XX_RX_BA_MAX_SESSIONS;
710 static int wl18xx_set_clk(struct wl1271 *wl)
715 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
721 ret = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT, &clk_freq);
731 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_N,
736 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_M,
742 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_SWALLOW_EN,
747 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N,
752 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M,
759 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1,
766 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2,
773 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1,
780 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2,
786 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN,
793 ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_SEL,
799 ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_EN, PLLSH_WL_PLL_EN_VAL1);
806 ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_EN, PLLSH_WL_PLL_EN_VAL2);
811 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_SWALLOW_EN,
818 static int wl18xx_boot_soft_reset(struct wl1271 *wl)
823 ret = wlcore_write32(wl, WL18XX_ENABLE, 0x0);
828 ret = wlcore_write32(wl, WL18XX_SPARE_A2, 0xffff);
834 static int wl18xx_pre_boot(struct wl1271 *wl)
838 ret = wl18xx_set_clk(wl);
843 ret = wlcore_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
849 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
854 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
858 ret = wl18xx_boot_soft_reset(wl);
864 static int wl18xx_pre_upload(struct wl1271 *wl)
873 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
878 ret = wlcore_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
882 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
888 ret = wlcore_read32(wl, WL18XX_SCR_PAD2, &tmp);
899 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
904 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
910 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
916 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
921 ret = irq_get_trigger_type(wl->irq);
924 ret = wlcore_set_partition(wl,
925 &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
929 ret = wl18xx_top_reg_read(wl, TOP_FN0_CCCR_REG_32, &irq_invert);
934 ret = wl18xx_top_reg_write(wl, TOP_FN0_CCCR_REG_32, irq_invert);
938 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
945 static int wl18xx_set_mac_and_phy(struct wl1271 *wl)
947 struct wl18xx_priv *priv = wl->priv;
957 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
961 ret = wlcore_write(wl, WL18XX_PHY_INIT_MEM_ADDR, params,
969 static int wl18xx_enable_interrupts(struct wl1271 *wl)
977 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, event_mask);
981 wlcore_enable_interrupts(wl);
983 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
991 wlcore_disable_interrupts(wl);
997 static int wl18xx_boot(struct wl1271 *wl)
1001 ret = wl18xx_pre_boot(wl);
1005 ret = wl18xx_pre_upload(wl);
1009 ret = wlcore_boot_upload_firmware(wl);
1013 ret = wl18xx_set_mac_and_phy(wl);
1017 wl->event_mask = BSS_LOSS_EVENT_ID |
1036 wl->ap_event_mask = MAX_TX_FAILURE_EVENT_ID;
1038 ret = wlcore_boot_run_firmware(wl);
1042 ret = wl18xx_enable_interrupts(wl);
1048 static int wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
1051 struct wl18xx_priv *priv = wl->priv;
1056 return wlcore_write(wl, cmd_box_addr, priv->cmd_buf,
1060 static int wl18xx_ack_event(struct wl1271 *wl)
1062 return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
1066 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
1073 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1080 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1086 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME)
1099 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
1107 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1119 static void wl18xx_tx_immediate_completion(struct wl1271 *wl)
1121 wl18xx_tx_immediate_complete(wl);
1124 static int wl18xx_set_host_cfg_bitmap(struct wl1271 *wl, u32 extra_mem_blk)
1132 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) {
1138 if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) {
1143 ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap,
1152 static int wl18xx_hw_init(struct wl1271 *wl)
1155 struct wl18xx_priv *priv = wl->priv;
1162 ret = wl18xx_set_host_cfg_bitmap(wl, WL18XX_TX_HW_BLOCK_SPARE);
1167 ret = wl18xx_acx_dynamic_fw_traces(wl);
1172 ret = wl18xx_acx_set_checksum_state(wl);
1180 static void wl18xx_convert_fw_status(struct wl1271 *wl, void *raw_fw_status,
1217 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl,
1247 static void wl18xx_set_rx_csum(struct wl1271 *wl,
1255 static bool wl18xx_is_mimo_supported(struct wl1271 *wl)
1257 struct wl18xx_priv *priv = wl->priv;
1271 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1283 } else if (wl18xx_is_mimo_supported(wl)) {
1291 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
1303 } else if (wl18xx_is_mimo_supported(wl) &&
1342 static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1348 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1352 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse);
1358 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_1_3, &fuse);
1372 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse);
1384 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
1438 static int wl18xx_conf_init(struct wl1271 *wl, struct device *dev)
1440 struct platform_device *pdev = wl->pdev;
1442 struct wl18xx_priv *priv = wl->priv;
1444 if (wl18xx_load_conf_file(dev, &wl->conf, &priv->conf,
1449 memcpy(&wl->conf, &wl18xx_conf, sizeof(wl->conf));
1458 static int wl18xx_plt_init(struct wl1271 *wl)
1463 if (wl->plt_mode == PLT_FEM_DETECT) {
1468 ret = wlcore_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT);
1472 return wl->ops->boot(wl);
1475 static int wl18xx_get_mac(struct wl1271 *wl)
1480 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1484 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1, &mac1);
1488 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2, &mac2);
1493 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1495 wl->fuse_nic_addr = (mac1 & 0xffffff);
1497 if (!wl->fuse_oui_addr && !wl->fuse_nic_addr) {
1502 wl->fuse_oui_addr = (mac[0] << 16) + (mac[1] << 8) + mac[2];
1503 wl->fuse_nic_addr = (mac[3] << 16) + (mac[4] << 8) + mac[5];
1507 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1513 static int wl18xx_handle_static_data(struct wl1271 *wl,
1519 strscpy(wl->chip.phy_fw_ver_str, static_data_priv->phy_version,
1520 sizeof(wl->chip.phy_fw_ver_str));
1527 static int wl18xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1529 struct wl18xx_priv *priv = wl->priv;
1538 static int wl18xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1543 struct wl18xx_priv *priv = wl->priv;
1553 ret = wlcore_set_key(wl, cmd, vif, sta, key_conf);
1581 ret = wl18xx_set_host_cfg_bitmap(wl,
1584 ret = wl18xx_set_host_cfg_bitmap(wl,
1591 static u32 wl18xx_pre_pkt_send(struct wl1271 *wl,
1594 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) {
1598 last_desc = (struct wl1271_tx_hw_descr *)(wl->aggr_buf +
1610 static void wl18xx_sta_rc_update(struct wl1271 *wl,
1631 wl18xx_acx_peer_ht_operation_mode(wl, wlvif->sta.hlid, wide);
1636 static int wl18xx_set_peer_cap(struct wl1271 *wl,
1641 return wl18xx_acx_set_peer_cap(wl, ht_cap, allow_ht_operation,
1645 static bool wl18xx_lnk_high_prio(struct wl1271 *wl, u8 hlid,
1650 (struct wl18xx_fw_status_priv *)wl->fw_status->priv;
1663 if (test_bit(hlid, &wl->fw_fast_lnk_map) &&
1664 !test_bit(hlid, &wl->ap_fw_ps_map))
1672 static bool wl18xx_lnk_low_prio(struct wl1271 *wl, u8 hlid,
1677 (struct wl18xx_fw_status_priv *)wl->fw_status->priv;
1687 else if (test_bit(hlid, &wl->fw_fast_lnk_map) &&
1688 !test_bit(hlid, &wl->ap_fw_ps_map))
1696 static u32 wl18xx_convert_hwaddr(struct wl1271 *wl, u32 hwaddr)
1701 static int wl18xx_setup(struct wl1271 *wl);
1867 static int wl18xx_setup(struct wl1271 *wl)
1869 struct wl18xx_priv *priv = wl->priv;
1876 wl->rtable = wl18xx_rtable;
1877 wl->num_tx_desc = WL18XX_NUM_TX_DESCRIPTORS;
1878 wl->num_rx_desc = WL18XX_NUM_RX_DESCRIPTORS;
1879 wl->num_links = WL18XX_MAX_LINKS;
1880 wl->max_ap_stations = WL18XX_MAX_AP_STATIONS;
1881 wl->iface_combinations = wl18xx_iface_combinations;
1882 wl->n_iface_combinations = ARRAY_SIZE(wl18xx_iface_combinations);
1883 wl->num_mac_addr = WL18XX_NUM_MAC_ADDRESSES;
1884 wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
1885 wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
1886 wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
1887 wl->fw_status_len = sizeof(struct wl18xx_fw_status);
1888 wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
1889 wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics);
1890 wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv);
1893 wl->num_rx_desc = num_rx_desc_param;
1895 ret = wl18xx_conf_init(wl, wl->dev);
1962 if (wl18xx_is_mimo_supported(wl))
1963 wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ,
1966 wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ,
1970 wlcore_set_ht_cap(wl, NL80211_BAND_5GHZ,
1973 wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ,
1975 wlcore_set_ht_cap(wl, NL80211_BAND_5GHZ,
1978 wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ,
1980 wlcore_set_ht_cap(wl, NL80211_BAND_5GHZ,
1990 wl->enable_11a = (priv->conf.phy.number_of_assembled_ant5 != 0);
1997 struct wl1271 *wl;
2010 wl = hw->priv;
2011 wl->ops = &wl18xx_ops;
2012 wl->ptable = wl18xx_ptable;
2013 ret = wlcore_probe(wl, pdev);
2020 wlcore_free_hw(wl);