Lines Matching refs:path
152 u8 path;
156 for (path = 0; path < RF_PATH_MAX; path++) {
157 if (!(kpath & BIT(path)))
161 2, 5000, false, rtwdev, path, 0x00,
165 path, ret);
303 enum rtw89_rf_path path, u8 index)
311 path_offset = (path == RF_PATH_A ? 0 : 0x28);
319 val32 |= dack->msbk_d[path][index][i + 12] << (i * 8);
328 val32 |= dack->msbk_d[path][index][i + 8] << (i * 8);
337 val32 |= dack->msbk_d[path][index][i + 4] << (i * 8);
346 val32 |= dack->msbk_d[path][index][i] << (i * 8);
353 val32 = (dack->biask_d[path][index] << 22) |
354 (dack->dadck_d[path][index] << 14);
360 static void _dack_reload(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
365 _dack_reload_by_path(rtwdev, path, i);
406 static void _dack_reset(struct rtw89_dev *rtwdev, u8 path)
408 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
442 static void rtw8852c_txck_force(struct rtw89_dev *rtwdev, u8 path, bool force,
445 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x0);
450 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_VAL, ck);
451 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x1);
454 static void rtw8852c_rxck_force(struct rtw89_dev *rtwdev, u8 path, bool force,
459 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x0);
464 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_VAL, ck);
465 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x1);
480 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_CTL, def->ctl);
481 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_EN, def->en);
482 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_BW0, def->bw0);
483 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1 | (path << 8), B_P0_CFCH_BW1, def->bw1);
484 rtw89_phy_write32_mask(rtwdev, R_DRCK | (path << 8), B_DRCK_MUL, def->mul);
485 rtw89_phy_write32_mask(rtwdev, R_ADCMOD | (path << 8), B_ADCMOD_LP, def->lp);
646 static void rtw8852c_disable_rxagc(struct rtw89_dev *rtwdev, u8 path, u8 en_rxgac)
648 if (path == RF_PATH_A)
654 static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path)
658 if (path == RF_PATH_A)
663 switch (iqk_info->iqk_bw[path]) {
666 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_DPD_GDIS, 0x1);
667 rtw8852c_rxck_force(rtwdev, path, true, ADC_480M);
668 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_ACK_VAL, 0x0);
669 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_CKT, 0x1);
670 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG, 0x1);
673 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_DPD_GDIS, 0x1);
674 rtw8852c_rxck_force(rtwdev, path, true, ADC_960M);
675 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_ACK_VAL, 0x1);
676 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_CKT, 0x1);
677 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG, 0x1);
680 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_DPD_GDIS, 0x1);
681 rtw8852c_rxck_force(rtwdev, path, true, ADC_1920M);
682 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_ACK_VAL, 0x2);
683 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_CKT, 0x1);
684 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG, 0x1);
692 if (path == RF_PATH_A)
698 static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path, u8 ktype)
710 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ret=%d\n", path, ret);
713 "[IQK]S%x, type= %x, 0x8008 = 0x%x\n", path, ktype, tmp);
719 enum rtw89_phy_idx phy_idx, u8 path, u8 ktype)
722 u32 addr_rfc_ctl = R_UPD_CLK + (path << 13);
728 iqk_cmd = 0x008 | (1 << (4 + path)) | (path << 1);
732 iqk_cmd = 0x008 | (1 << (4 + path));
736 iqk_cmd = 0x108 | (1 << (4 + path));
740 iqk_cmd = 0x508 | (1 << (4 + path));
744 iqk_cmd = 0x208 | (1 << (4 + path));
748 iqk_cmd = 0x308 | (1 << (4 + path));
752 iqk_cmd = 0x008 | (1 << (4 + path)) | ((0x8 + iqk_info->iqk_bw[path]) << 8);
755 iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1);
759 iqk_cmd = 0x008 | (1 << (4 + path)) | ((0xc + iqk_info->iqk_bw[path]) << 8);
763 iqk_cmd = 0x408 | (1 << (4 + path));
767 iqk_cmd = 0x608 | (1 << (4 + path));
775 fail = _iqk_check_cal(rtwdev, path, ktype);
782 enum rtw89_phy_idx phy_idx, u8 path)
790 bkrf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_NBW);
791 if (path == RF_PATH_B) {
799 switch (iqk_info->iqk_band[path]) {
802 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
803 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, 0x0);
804 rtw89_write_rf(rtwdev, path, RR_RXG, RR_RXG_IQKMOD, 0x9);
807 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
808 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, 0x0);
809 rtw89_write_rf(rtwdev, path, RR_RXAE, RR_RXAE_IQKMOD, 0x8);
812 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
813 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, 0x0);
814 rtw89_write_rf(rtwdev, path, RR_RXAE, RR_RXAE_IQKMOD, 0x9);
821 switch (iqk_info->iqk_band[path]) {
824 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG,
826 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_VOBUF,
830 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG,
832 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_IATT,
836 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG,
838 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_IATT,
842 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
844 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
846 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
848 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK);
851 if (path == RF_PATH_B)
852 rtw89_write_rf(rtwdev, path, RR_IQKPLL, RR_IQKPLL_MOD, 0x0);
853 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, bkrf0);
856 iqk_info->nb_rxcfir[path] = 0x40000002;
857 iqk_info->is_wb_rxiqk[path] = false;
859 iqk_info->nb_rxcfir[path] = 0x40000000;
860 iqk_info->is_wb_rxiqk[path] = true;
867 enum rtw89_phy_idx phy_idx, u8 path)
875 bkrf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_NBW);
876 if (path == RF_PATH_B) {
884 switch (iqk_info->iqk_band[path]) {
887 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
888 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, 0x0);
889 rtw89_write_rf(rtwdev, path, RR_RXG, RR_RXG_IQKMOD, 0x9);
892 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
893 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, 0x0);
894 rtw89_write_rf(rtwdev, path, RR_RXAE, RR_RXAE_IQKMOD, 0x8);
897 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
898 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, 0x0);
899 rtw89_write_rf(rtwdev, path, RR_RXAE, RR_RXAE_IQKMOD, 0x9);
905 switch (iqk_info->iqk_band[path]) {
908 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, _rxk_g_idxrxgain[gp]);
909 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_VOBUF, _rxk_g_idxattc2[gp]);
912 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, _rxk_a_idxrxgain[gp]);
913 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_IATT, _rxk_a_idxattc2[gp]);
916 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, _rxk_a6_idxrxgain[gp]);
917 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_IATT, _rxk_a6_idxattc2[gp]);
921 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1);
922 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x0);
923 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP_V1, gp);
924 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK);
926 if (path == RF_PATH_B)
927 rtw89_write_rf(rtwdev, path, RR_IQKPLL, RR_IQKPLL_MOD, 0x0);
929 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, bkrf0);
932 iqk_info->nb_rxcfir[path] =
933 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8),
936 iqk_info->nb_rxcfir[path] = 0x40000002;
938 iqk_info->is_wb_rxiqk[path] = false;
943 enum rtw89_phy_idx phy_idx, u8 path)
950 switch (iqk_info->iqk_band[path]) {
952 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
954 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
956 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
959 R_KIP_IQP + (path << 8),
963 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
965 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
967 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
970 R_KIP_IQP + (path << 8),
974 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
976 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
978 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
981 R_KIP_IQP + (path << 8),
987 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
989 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
991 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
993 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
997 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK);
1001 iqk_info->nb_txcfir[path] = 0x40000002;
1002 iqk_info->is_wb_txiqk[path] = false;
1004 iqk_info->nb_txcfir[path] = 0x40000000;
1005 iqk_info->is_wb_txiqk[path] = true;
1012 enum rtw89_phy_idx phy_idx, u8 path)
1018 switch (iqk_info->iqk_band[path]) {
1020 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, _txk_g_power_range[gp]);
1021 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, _txk_g_track_range[gp]);
1022 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, _txk_g_gain_bb[gp]);
1023 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1027 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, _txk_a_power_range[gp]);
1028 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, _txk_a_track_range[gp]);
1029 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, _txk_a_gain_bb[gp]);
1030 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1034 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, _txk_a6_power_range[gp]);
1035 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, _txk_a6_track_range[gp]);
1036 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, _txk_a6_gain_bb[gp]);
1037 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1044 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1);
1045 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x1);
1046 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G2, 0x0);
1047 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, gp + 1);
1050 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
1053 iqk_info->nb_txcfir[path] =
1054 rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8),
1057 iqk_info->nb_txcfir[path] = 0x40000002;
1059 iqk_info->is_wb_txiqk[path] = false;
1064 static bool _lok_finetune_check(struct rtw89_dev *rtwdev, u8 path)
1077 val = rtw89_read_rf(rtwdev, path, RR_TXMO, RFREG_MASK);
1086 iqk_info->lok_idac[idx][path] = val;
1088 val = rtw89_read_rf(rtwdev, path, RR_LOKVB, RFREG_MASK);
1097 iqk_info->lok_vbuf[idx][path] = val;
1103 enum rtw89_phy_idx phy_idx, u8 path)
1114 switch (iqk_info->iqk_band[path]) {
1116 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x6);
1117 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1122 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x6);
1123 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1128 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x6);
1129 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1136 tmp = _iqk_one_shot(rtwdev, phy_idx, path, tmp_id);
1137 iqk_info->lok_cor_fail[0][path] = tmp;
1140 switch (iqk_info->iqk_band[path]) {
1142 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1143 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1147 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1148 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1152 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1153 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1159 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_VBUFFER);
1162 switch (iqk_info->iqk_band[path]) {
1164 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x6);
1165 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1170 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x6);
1171 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1176 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x6);
1177 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1184 tmp = _iqk_one_shot(rtwdev, phy_idx, path, tmp_id);
1185 iqk_info->lok_fin_fail[0][path] = tmp;
1188 switch (iqk_info->iqk_band[path]) {
1191 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1192 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1196 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1197 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1201 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1202 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1206 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_VBUFFER);
1207 fail = _lok_finetune_check(rtwdev, path);
1212 static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path)
1216 switch (iqk_info->iqk_band[path]) {
1219 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0);
1220 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x0);
1221 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1);
1222 rtw89_write_rf(rtwdev, path, RR_TXA2, RR_TXA2_LDO, 0xf);
1223 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0);
1224 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
1225 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK,
1228 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
1229 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x6);
1232 rtw89_write_rf(rtwdev, path, RR_TXATANK, RR_TXATANK_LBSW2, 0x0);
1233 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXAS, 0x1);
1234 rtw89_write_rf(rtwdev, path, RR_TXA2, RR_TXA2_LDO, 0xf);
1235 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0);
1236 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
1237 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK,
1240 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
1241 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x6);
1244 rtw89_write_rf(rtwdev, path, RR_TXATANK, RR_TXATANK_LBSW2, 0x0);
1245 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXAS, 0x1);
1246 rtw89_write_rf(rtwdev, path, RR_TXA2, RR_TXA2_LDO, 0xf);
1247 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0);
1248 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
1249 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK,
1252 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
1253 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x6);
1259 u8 path)
1265 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_thermal = %lu\n", path,
1266 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]));
1267 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_COR_fail= %d\n", path,
1268 iqk_info->lok_cor_fail[0][path]);
1269 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_FIN_fail= %d\n", path,
1270 iqk_info->lok_fin_fail[0][path]);
1271 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_TXIQK_fail = %d\n", path,
1272 iqk_info->iqk_tx_fail[0][path]);
1273 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_RXIQK_fail= %d,\n", path,
1274 iqk_info->iqk_rx_fail[0][path]);
1276 flag = iqk_info->lok_cor_fail[0][path];
1277 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FCOR << (path * 4), flag);
1278 flag = iqk_info->lok_fin_fail[0][path];
1279 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FFIN << (path * 4), flag);
1280 flag = iqk_info->iqk_tx_fail[0][path];
1281 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FTX << (path * 4), flag);
1282 flag = iqk_info->iqk_rx_fail[0][path];
1283 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_F_RX << (path * 4), flag);
1285 tmp = rtw89_phy_read32_mask(rtwdev, R_IQK_RES + (path << 8), MASKDWORD);
1286 iqk_info->bp_iqkenable[path] = tmp;
1287 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
1288 iqk_info->bp_txkresult[path] = tmp;
1289 tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD);
1290 iqk_info->bp_rxkresult[path] = tmp;
1295 tmp = rtw89_phy_read32_mask(rtwdev, R_IQKINF, B_IQKINF_FAIL << (path * 4));
1298 rtw89_phy_write32_mask(rtwdev, R_IQKINF2, B_IQKINF2_FCNT << (path * 4),
1302 static void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1306 _iqk_txk_setting(rtwdev, path);
1307 iqk_info->lok_fail[path] = _iqk_lok(rtwdev, phy_idx, path);
1310 iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path);
1312 iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path);
1314 _iqk_rxk_setting(rtwdev, path);
1316 iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path);
1318 iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path);
1320 _iqk_info_iqk(rtwdev, phy_idx, path);
1324 enum rtw89_phy_idx phy, u8 path)
1331 iqk_info->iqk_band[path] = chan->band_type;
1332 iqk_info->iqk_bw[path] = chan->band_width;
1333 iqk_info->iqk_ch[path] = chan->channel;
1336 "[IQK]iqk_info->iqk_band[%x] = 0x%x\n", path,
1337 iqk_info->iqk_band[path]);
1339 path, iqk_info->iqk_bw[path]);
1341 path, iqk_info->iqk_ch[path]);
1343 "[IQK]S%d (PHY%d): / DBCC %s/ %s/ CH%d/ %s\n", path, phy,
1345 iqk_info->iqk_band[path] == 0 ? "2G" :
1346 iqk_info->iqk_band[path] == 1 ? "5G" : "6G",
1347 iqk_info->iqk_ch[path],
1348 iqk_info->iqk_bw[path] == 0 ? "20M" :
1349 iqk_info->iqk_bw[path] == 1 ? "40M" : "80M");
1356 rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_BAND << (path * 16),
1357 iqk_info->iqk_band[path]);
1358 rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_BW << (path * 16),
1359 iqk_info->iqk_bw[path]);
1360 rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_CH << (path * 16),
1361 iqk_info->iqk_ch[path]);
1367 u8 path)
1369 _iqk_by_path(rtwdev, phy_idx, path);
1372 static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path)
1377 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD,
1378 iqk_info->nb_txcfir[path]);
1379 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD,
1380 iqk_info->nb_rxcfir[path]);
1382 0x00001219 + (path << 4));
1384 fail = _iqk_check_cal(rtwdev, path, 0x12);
1391 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0);
1392 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
1393 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
1397 enum rtw89_phy_idx phy_idx, u8 path)
1399 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
1403 rtw8852c_disable_rxagc(rtwdev, path, 0x1);
1406 static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path)
1412 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_IQC, idx);
1413 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3, idx);
1414 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1420 enum rtw89_phy_idx phy_idx, u8 path)
1425 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0);
1426 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A0 << path, 0x1);
1427 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A1 << path, 0x0);
1428 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A2 << path, 0x1);
1429 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A3 << path, 0x0);
1432 rtw8852c_disable_rxagc(rtwdev, path, 0x0);
1433 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK | (path << 13), MASKDWORD, 0xf801fffd);
1434 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK | (path << 13), B_DPD_DIS, 0x1);
1435 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK | (path << 13), B_DAC_VAL, 0x1);
1437 rtw8852c_txck_force(rtwdev, path, true, DAC_960M);
1438 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK | (path << 13), B_DPD_GDIS, 0x1);
1440 rtw8852c_rxck_force(rtwdev, path, true, ADC_1920M);
1441 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK | (path << 13), B_ACK_VAL, 0x2);
1443 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW | (path << 13), B_P0_NRBW_DBG, 0x1);
1448 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A1 << path, 0x1);
1449 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A3 << path, 0x1);
1452 static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
1458 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path);
1460 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
1462 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1463 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
1466 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
1469 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240);
1472 false, rtwdev, path, 0x1c, BIT(3));
1476 rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA);
1477 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val);
1479 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
1483 rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK),
1484 rtw89_read_rf(rtwdev, path, RR_RCKS, RFREG_MASK));
1490 u8 ch, path;
1507 for (path = 0; path < RTW8852C_IQK_SS; path++) {
1508 iqk_info->lok_cor_fail[ch][path] = false;
1509 iqk_info->lok_fin_fail[ch][path] = false;
1510 iqk_info->iqk_tx_fail[ch][path] = false;
1511 iqk_info->iqk_rx_fail[ch][path] = false;
1512 iqk_info->iqk_mcc_ch[ch][path] = 0x0;
1513 iqk_info->iqk_table_idx[path] = 0x0;
1519 enum rtw89_phy_idx phy_idx, u8 path)
1534 _iqk_get_ch_info(rtwdev, phy_idx, path);
1536 _rfk_backup_rf_reg(rtwdev, backup_rf_val[path], path);
1537 _iqk_macbb_setting(rtwdev, phy_idx, path);
1538 _iqk_preset(rtwdev, path);
1539 _iqk_start_iqk(rtwdev, phy_idx, path);
1540 _iqk_restore(rtwdev, path);
1541 _iqk_afebb_restore(rtwdev, phy_idx, path);
1543 _rfk_restore_rf_reg(rtwdev, backup_rf_val[path], path);
1565 static void _rx_dck_value_rewrite(struct rtw89_dev *rtwdev, u8 path, u8 addr,
1577 rtw89_write_rf(rtwdev, path, RR_LUTPLL, RR_CAL_RW, 0x1);
1578 rtw89_write_rf(rtwdev, path, RR_RFC, RR_WCAL, 0x1);
1579 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x1);
1580 rtw89_write_rf(rtwdev, path, RR_LUTWA, MASKBYTE0, addr);
1581 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, ofst_val);
1582 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, ofst_val);
1583 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0);
1584 rtw89_write_rf(rtwdev, path, RR_RFC, RR_WCAL, 0x0);
1585 rtw89_write_rf(rtwdev, path, RR_LUTPLL, RR_CAL_RW, 0x0);
1592 static bool _rx_dck_rek_check(struct rtw89_dev *rtwdev, u8 path)
1602 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr_bs[i]);
1603 i_even_bs = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA);
1604 q_even_bs = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA);
1609 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr[i]);
1610 i_even = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA);
1611 q_even = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA);
1619 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr_bs[i] + 1);
1620 i_odd_bs = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA);
1621 q_odd_bs = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA);
1626 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr[i] + 1);
1627 i_odd = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA);
1628 q_odd = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA);
1640 static void _rx_dck_fix_if_need(struct rtw89_dev *rtwdev, u8 path, u8 addr,
1662 _rx_dck_value_rewrite(rtwdev, path, addr, val_i, val_q);
1665 static void _rx_dck_recover(struct rtw89_dev *rtwdev, u8 path)
1676 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr_bs[i]);
1677 i_even_bs = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA);
1678 q_even_bs = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA);
1680 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr_bs[i] + 1);
1681 i_odd_bs = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA);
1682 q_odd_bs = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA);
1688 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr[i]);
1689 i_even = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA);
1690 q_even = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA);
1695 _rx_dck_fix_if_need(rtwdev, path, _dck_addr[i],
1702 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr[i] + 1);
1703 i_odd = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA);
1704 q_odd = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA);
1709 _rx_dck_fix_if_need(rtwdev, path, _dck_addr[i] + 1,
1714 static void _rx_dck_toggle(struct rtw89_dev *rtwdev, u8 path)
1719 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
1720 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1);
1723 2, 2000, false, rtwdev, path,
1726 rtw89_warn(rtwdev, "[RX_DCK] S%d RXDCK timeout\n", path);
1728 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RX_DCK] S%d RXDCK finish\n", path);
1730 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
1733 static void _set_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, u8 path,
1738 rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_CLR, 0x0);
1740 _rx_dck_toggle(rtwdev, path);
1741 if (rtw89_read_rf(rtwdev, path, RR_DCKC, RR_DCKC_CHK) == 0)
1743 res = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_DONE);
1745 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_IDAC, res);
1746 _rx_dck_toggle(rtwdev, path);
1747 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_IDAC, 0x1);
1830 enum rtw89_rf_path path, bool is_bybb)
1833 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
1835 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1839 enum rtw89_rf_path path, bool off);
1842 u32 reg_bkup[][RTW8852C_DPK_KIP_REG_NUM], u8 path)
1847 reg_bkup[path][i] =
1848 rtw89_phy_read32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD);
1851 reg[i] + (path << 8), reg_bkup[path][i]);
1856 u32 reg_bkup[][RTW8852C_DPK_KIP_REG_NUM], u8 path)
1861 rtw89_phy_write32_mask(rtwdev, reg[i] + (path << 8),
1862 MASKDWORD, reg_bkup[path][i]);
1864 reg[i] + (path << 8), reg_bkup[path][i]);
1869 enum rtw89_rf_path path, enum rtw8852c_dpk_id id)
1875 dpk_cmd = (u16)((id << 8) | (0x19 + path * 0x12));
1904 enum rtw89_rf_path path)
1909 u8 kidx = dpk->cur_idx[path];
1911 dpk->bp[path][kidx].band = chan->band_type;
1912 dpk->bp[path][kidx].ch = chan->channel;
1913 dpk->bp[path][kidx].bw = chan->band_width;
1917 path, dpk->cur_idx[path], phy,
1918 rtwdev->is_tssi_mode[path] ? "on" : "off",
1920 dpk->bp[path][kidx].band == 0 ? "2G" :
1921 dpk->bp[path][kidx].band == 1 ? "5G" : "6G",
1922 dpk->bp[path][kidx].ch,
1923 dpk->bp[path][kidx].bw == 0 ? "20M" :
1924 dpk->bp[path][kidx].bw == 1 ? "40M" : "80M");
1929 enum rtw89_rf_path path, u8 kpath)
1932 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A0 << path, 0x1);
1933 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A1 << path, 0x0);
1934 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A2 << path, 0x1);
1935 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A3 << path, 0x0);
1938 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), MASKDWORD, 0xd801dffd);
1941 rtw8852c_txck_force(rtwdev, path, true, DAC_960M);
1944 rtw8852c_rxck_force(rtwdev, path, true, ADC_1920M);
1945 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW + (path << 13),
1953 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A1 << path, 0x1);
1954 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A3 << path, 0x1);
1956 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d BB/AFE setting\n", path);
1959 static void _dpk_bb_afe_restore(struct rtw89_dev *rtwdev, u8 path)
1961 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW + (path << 13),
1963 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A0 << path, 0x1);
1964 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A1 << path, 0x0);
1965 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A2 << path, 0x1);
1966 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A3 << path, 0x0);
1967 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), MASKDWORD, 0x00000000);
1968 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), B_P0_TXCK_ALL, 0x00);
1969 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A0 << path, 0x0);
1970 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A2 << path, 0x0);
1972 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d BB/AFE restore\n", path);
1976 enum rtw89_rf_path path, bool is_pause)
1978 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13),
1981 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path,
1985 static void _dpk_kip_control_rfc(struct rtw89_dev *rtwdev, u8 path, bool ctrl_by_kip)
1987 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_IQK_RFC_ON, ctrl_by_kip);
1992 static void _dpk_txpwr_bb_force(struct rtw89_dev *rtwdev, u8 path, bool force)
1994 rtw89_phy_write32_mask(rtwdev, R_TXPWRB + (path << 13), B_TXPWRB_ON, force);
1995 rtw89_phy_write32_mask(rtwdev, R_TXPWRB_H + (path << 13), B_TXPWRB_RDY, force);
1998 path, force ? "on" : "off");
2002 enum rtw89_rf_path path)
2004 _dpk_one_shot(rtwdev, phy, path, D_KIP_RESTORE);
2005 _dpk_kip_control_rfc(rtwdev, path, false);
2006 _dpk_txpwr_bb_force(rtwdev, path, false);
2007 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path);
2012 enum rtw89_rf_path path)
2018 rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), B_DPD_LBK, 0x1);
2021 _dpk_kip_control_rfc(rtwdev, path, false);
2023 cur_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB);
2024 rf_11 = rtw89_read_rf(rtwdev, path, RR_TXIG, RFREG_MASK);
2025 reg_81cc = rtw89_phy_read32_mask(rtwdev, R_KIP_IQP + (path << 8),
2028 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
2029 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x3);
2030 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0xd);
2031 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB, 0x1f);
2033 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x12);
2034 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_SW, 0x3);
2036 _dpk_kip_control_rfc(rtwdev, path, true);
2040 _dpk_one_shot(rtwdev, phy, path, LBK_RXIQK);
2042 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path,
2043 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD));
2045 _dpk_kip_control_rfc(rtwdev, path, false);
2047 rtw89_write_rf(rtwdev, path, RR_TXIG, RFREG_MASK, rf_11);
2048 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB, cur_rxbb);
2049 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_SW, reg_81cc);
2053 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_DI, 0x1);
2055 _dpk_kip_control_rfc(rtwdev, path, true);
2059 enum rtw89_rf_path path, u8 kidx)
2063 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) {
2064 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK,
2066 rtw89_write_rf(rtwdev, path, RR_MOD_V1, RR_MOD_MASK, RF_DPK);
2067 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTC, 0x2);
2068 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTR, 0x4);
2069 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1);
2070 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1);
2074 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK),
2075 rtw89_read_rf(rtwdev, path, RR_RXBB, RFREG_MASK),
2076 rtw89_read_rf(rtwdev, path, RR_TIA, RFREG_MASK),
2077 rtw89_read_rf(rtwdev, path, RR_BTC, RFREG_MASK),
2078 rtw89_read_rf(rtwdev, path, RR_LUTDBG, RFREG_MASK),
2079 rtw89_read_rf(rtwdev, path, 0x1001a, RFREG_MASK));
2081 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK,
2083 rtw89_write_rf(rtwdev, path, RR_MOD_V1, RR_MOD_MASK, RF_DPK);
2085 if (dpk->bp[path][kidx].band == RTW89_BAND_6G && dpk->bp[path][kidx].ch >= 161)
2086 rtw89_write_rf(rtwdev, path, RR_IQGEN, RR_IQGEN_BIAS, 0x8);
2088 rtw89_write_rf(rtwdev, path, RR_LOGEN, RR_LOGEN_RPT, 0xd);
2089 rtw89_write_rf(rtwdev, path, RR_TXAC, RR_TXAC_IQG, 0x8);
2091 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_ATT, 0x0);
2092 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT2, 0x3);
2093 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1);
2094 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1);
2096 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_160)
2097 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_EBW, 0x0);
2101 static void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
2105 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_160) {
2108 } else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80) {
2111 } else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40) {
2119 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_160 ? "160M" :
2120 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" :
2121 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M");
2124 static bool _dpk_sync_check(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
2139 dpk->corr_idx[path][kidx] = corr_idx;
2140 dpk->corr_val[path][kidx] = corr_val;
2152 path, corr_idx, corr_val, dc_i, dc_q);
2154 dpk->dc_i[path][kidx] = dc_i;
2155 dpk->dc_q[path][kidx] = dc_q;
2165 path, rxbb,
2203 static void _dpk_kset_query(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
2207 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0x10);
2209 rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), 0xE0000000) - 1;
2213 enum rtw89_rf_path path, u8 dbm, bool set_from_bb)
2217 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] set S%d txagc to %ddBm\n", path, dbm);
2218 rtw89_phy_write32_mask(rtwdev, R_TXPWRB + (path << 13), B_TXPWRB_VAL, dbm << 2);
2220 _dpk_one_shot(rtwdev, phy, path, D_TXAGC);
2221 _dpk_kset_query(rtwdev, path);
2225 enum rtw89_rf_path path, u8 kidx)
2227 _dpk_one_shot(rtwdev, phy, path, D_GAIN_LOSS);
2228 _dpk_kip_set_txagc(rtwdev, phy, path, 0xff, false);
2230 rtw89_phy_write32_mask(rtwdev, R_DPK_GL + (path << 8), B_DPK_GL_A1, 0x0);
2231 rtw89_phy_write32_mask(rtwdev, R_DPK_GL + (path << 8), B_DPK_GL_A0, 0x0);
2282 enum rtw89_rf_path path, u8 kidx)
2284 _dpk_kip_control_rfc(rtwdev, path, false);
2286 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
2287 _dpk_kip_control_rfc(rtwdev, path, true);
2289 _dpk_one_shot(rtwdev, phy, path, D_RXAGC);
2291 return _dpk_sync_check(rtwdev, path, kidx);
2310 static void _dpk_bypass_rxiqc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
2312 rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), B_DPD_LBK, 0x1);
2313 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD, 0x40000002);
2319 enum rtw89_rf_path path, u8 kidx, u8 init_xdbm, u8 loss_only)
2334 is_fail = _dpk_kip_set_rxagc(rtwdev, phy, path, kidx);
2347 _dpk_one_shot(rtwdev, phy, path, D_SYNC);
2352 if (dpk->bp[path][kidx].band == RTW89_BAND_2G)
2353 _dpk_bypass_rxiqc(rtwdev, path);
2355 _dpk_lbk_rxiqk(rtwdev, phy, path);
2361 tmp_gl_idx = _dpk_gainloss(rtwdev, phy, path, kidx);
2382 _dpk_kip_set_txagc(rtwdev, phy, path, tmp_dbm, true);
2394 _dpk_kip_set_txagc(rtwdev, phy, path, tmp_dbm, true);
2401 _dpk_kip_control_rfc(rtwdev, path, false);
2402 tmp_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB);
2408 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB, tmp_rxbb);
2411 _dpk_kip_control_rfc(rtwdev, path, true);
2449 enum rtw89_rf_path path, u8 kidx)
2464 else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_5 ||
2465 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_10 ||
2466 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_20)
2468 else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ||
2469 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80)
2477 _dpk_one_shot(rtwdev, phy, path, D_MDPK_IDL);
2486 _dpk_one_shot(rtwdev, phy, path, D_MDPK_IDL);
2493 _dpk_one_shot(rtwdev, phy, path, D_MDPK_IDL);
2498 enum rtw89_rf_path path)
2509 if (cur_band != dpk->bp[path][idx].band ||
2510 cur_ch != dpk->bp[path][idx].ch)
2513 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8),
2515 dpk->cur_idx[path] = idx;
2518 "[DPK] reload S%d[%d] success\n", path, idx);
2531 enum rtw89_rf_path path, u8 kidx)
2534 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
2538 R_DPD_CH0A + (path << 8) + (kidx << 2),
2542 R_DPD_CH0A + (path << 8) + (kidx << 2),
2545 _dpk_kip_control_rfc(rtwdev, path, true);
2546 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_MDPD, kidx);
2548 _dpk_one_shot(rtwdev, phy, path, D_KIP_PRESET);
2551 static void _dpk_para_query(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
2558 para = rtw89_phy_read32_mask(rtwdev, dpk_par_regs[kidx][dpk->cur_k_set] + (path << 8),
2561 dpk->bp[path][kidx].txagc_dpk = FIELD_GET(_DPK_PARA_TXAGC, para);
2562 dpk->bp[path][kidx].ther_dpk = FIELD_GET(_DPK_PARA_THER, para);
2565 dpk->cur_k_set, dpk->bp[path][kidx].ther_dpk, dpk->bp[path][kidx].txagc_dpk);
2569 enum rtw89_rf_path path, u8 kidx, bool is_execute)
2574 rtw89_phy_write32_mask(rtwdev, R_DPK_GN + (path << 8), B_DPK_GN_AG, 0x200);
2575 rtw89_phy_write32_mask(rtwdev, R_DPK_GN + (path << 8), B_DPK_GN_EN, 0x3);
2577 _dpk_one_shot(rtwdev, phy, path, D_GAIN_NORM);
2579 rtw89_phy_write32_mask(rtwdev, dpk_par_regs[kidx][dpk->cur_k_set] + (path << 8),
2582 dpk->bp[path][kidx].gs =
2583 rtw89_phy_read32_mask(rtwdev, dpk_par_regs[kidx][dpk->cur_k_set] + (path << 8),
2616 enum rtw89_rf_path path, u8 kidx)
2620 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1);
2621 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x0);
2622 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2625 dpk->bp[path][kidx].mdpd_en = BIT(dpk->cur_k_set);
2626 dpk->bp[path][kidx].path_ok = true;
2629 path, kidx, dpk->bp[path][kidx].mdpd_en);
2631 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2632 B_DPD_MEN, dpk->bp[path][kidx].mdpd_en);
2634 _dpk_gain_normalize_8852c(rtwdev, phy, path, kidx, false);
2638 enum rtw89_rf_path path, u8 gain)
2641 u8 kidx = dpk->cur_idx[path];
2646 "[DPK] ========= S%d[%d] DPK Start =========\n", path, kidx);
2647 _dpk_kip_control_rfc(rtwdev, path, false);
2648 _rf_direct_cntrl(rtwdev, path, false);
2649 rtw89_write_rf(rtwdev, path, RR_BBDC, RFREG_MASK, 0x03ffd);
2650 _dpk_rf_setting(rtwdev, gain, path, kidx);
2651 _set_rx_dck(rtwdev, phy, path, false);
2653 _dpk_kip_preset_8852c(rtwdev, phy, path, kidx);
2654 _dpk_txpwr_bb_force(rtwdev, path, true);
2655 _dpk_kip_set_txagc(rtwdev, phy, path, init_xdbm, true);
2656 _dpk_tpg_sel(rtwdev, path, kidx);
2658 is_fail = _dpk_agc(rtwdev, phy, path, kidx, init_xdbm, false);
2662 _dpk_idl_mpa(rtwdev, phy, path, kidx);
2663 _dpk_para_query(rtwdev, path, kidx);
2664 _dpk_on(rtwdev, phy, path, kidx);
2667 _dpk_kip_control_rfc(rtwdev, path, false);
2668 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RF_RX);
2669 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d]_K%d %s\n", path, kidx,
2675 static void _dpk_init(struct rtw89_dev *rtwdev, u8 path)
2678 u8 kidx = dpk->cur_idx[path];
2680 dpk->bp[path][kidx].path_ok = false;
2683 static void _dpk_drf_direct_cntrl(struct rtw89_dev *rtwdev, u8 path, bool is_bybb)
2686 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1);
2688 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0);
2698 u8 path;
2704 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++) {
2705 if (!(kpath & BIT(path)))
2708 reloaded[path] = _dpk_reload_check(rtwdev, phy, path);
2709 if (!reloaded[path] && dpk->bp[path][0].ch != 0)
2710 dpk->cur_idx[path] = !dpk->cur_idx[path];
2712 _dpk_onoff(rtwdev, path, false);
2715 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++)
2716 dpk->cur_idx[path] = 0;
2719 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++) {
2722 path, dpk->cur_idx[path]);
2723 _dpk_bkup_kip(rtwdev, kip_reg, kip_bkup, path);
2724 _rfk_backup_rf_reg(rtwdev, backup_rf_val[path], path);
2725 _dpk_information(rtwdev, phy, path);
2726 _dpk_init(rtwdev, path);
2727 if (rtwdev->is_tssi_mode[path])
2728 _dpk_tssi_pause(rtwdev, path, true);
2731 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++) {
2734 path, dpk->cur_idx[path]);
2735 rtw8852c_disable_rxagc(rtwdev, path, 0x0);
2736 _dpk_drf_direct_cntrl(rtwdev, path, false);
2737 _dpk_bb_afe_setting(rtwdev, phy, path, kpath);
2738 is_fail = _dpk_main(rtwdev, phy, path, 1);
2739 _dpk_onoff(rtwdev, path, is_fail);
2742 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++) {
2745 path, dpk->cur_idx[path]);
2746 _dpk_kip_restore(rtwdev, phy, path);
2747 _dpk_reload_kip(rtwdev, kip_reg, kip_bkup, path);
2748 _rfk_restore_rf_reg(rtwdev, backup_rf_val[path], path);
2749 _dpk_bb_afe_restore(rtwdev, path);
2750 rtw8852c_disable_rxagc(rtwdev, path, 0x1);
2751 if (rtwdev->is_tssi_mode[path])
2752 _dpk_tssi_pause(rtwdev, path, false);
2783 u8 path, kpath;
2787 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++) {
2788 if (kpath & BIT(path))
2789 _dpk_onoff(rtwdev, path, true);
2810 enum rtw89_rf_path path, bool off)
2813 u8 val, kidx = dpk->cur_idx[path];
2815 val = dpk->is_dpk_enable && !off && dpk->bp[path][kidx].path_ok ?
2816 dpk->bp[path][kidx].mdpd_en : 0;
2818 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2821 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path,
2828 u8 path, kidx;
2835 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++) {
2836 kidx = dpk->cur_idx[path];
2839 path, kidx, dpk->bp[path][kidx].ch);
2842 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), 0x0000003f);
2844 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), MASKBYTE2);
2846 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BTP + (path << 13), B_TXAGC_BTP);
2849 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xf);
2851 rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), B_RPT_PER_TH);
2853 rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), B_RPT_PER_OF);
2855 rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), B_RPT_PER_TSSI);
2858 cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
2863 if (dpk->bp[path][kidx].ch != 0 && cur_ther != 0)
2864 delta_ther = dpk->bp[path][kidx].ther_dpk - cur_ther;
2870 delta_ther, cur_ther, dpk->bp[path][kidx].ther_dpk);
2873 txagc_rf - dpk->bp[path][kidx].txagc_dpk, txagc_rf,
2874 dpk->bp[path][kidx].txagc_dpk);
2887 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2),
2894 enum rtw89_rf_path path)
2915 if (path == RF_PATH_A) {
2931 enum rtw89_rf_path path)
2933 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2940 enum rtw89_rf_path path)
2942 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2948 enum rtw89_rf_path path)
2953 if (path == RF_PATH_A) {
2967 enum rtw89_rf_path path)
2969 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2975 enum rtw89_rf_path path)
3057 if (path == RF_PATH_A) {
3161 enum rtw89_rf_path path)
3166 if (path == RF_PATH_A) {
3178 enum rtw89_rf_path path)
3184 if (path == RF_PATH_A) {
3204 enum rtw89_rf_path path)
3206 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3212 enum rtw89_rf_path path)
3214 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3220 enum rtw89_rf_path path)
3222 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3229 enum rtw89_rf_path path)
3231 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3239 u32 i, path = RF_PATH_A, path_max = RF_PATH_NUM_8852C;
3243 path = RF_PATH_A;
3246 path = RF_PATH_B;
3251 for (i = path; i < path_max; i++) {
3267 u32 i, path = RF_PATH_A, path_max = RF_PATH_NUM_8852C;
3271 path = RF_PATH_A;
3274 path = RF_PATH_B;
3279 for (i = path; i < path_max; i++) {
3589 enum rtw89_rf_path path)
3604 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n",
3605 path, gidx);
3610 de_1st = tssi_info->tssi_mcs[path][gidx_1st];
3611 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
3615 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
3616 path, val, de_1st, de_2nd);
3618 val = tssi_info->tssi_mcs[path][gidx];
3621 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
3627 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n",
3628 path, gidx);
3633 de_1st = tssi_info->tssi_6g_mcs[path][gidx_1st];
3634 de_2nd = tssi_info->tssi_6g_mcs[path][gidx_2nd];
3638 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
3639 path, val, de_1st, de_2nd);
3641 val = tssi_info->tssi_6g_mcs[path][gidx];
3644 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
3653 enum rtw89_rf_path path)
3668 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
3669 path, tgidx);
3674 tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
3675 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
3679 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
3680 path, val, tde_1st, tde_2nd);
3682 val = tssi_info->tssi_trim[path][tgidx];
3685 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
3686 path, val);
3692 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
3693 path, tgidx);
3698 tde_1st = tssi_info->tssi_trim_6g[path][tgidx_1st];
3699 tde_2nd = tssi_info->tssi_trim_6g[path][tgidx_2nd];
3703 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
3704 path, val, tde_1st, tde_2nd);
3706 val = tssi_info->tssi_trim_6g[path][tgidx];
3709 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
3710 path, val);
3727 u32 i, path = RF_PATH_A, path_max = RF_PATH_NUM_8852C;
3734 path = RF_PATH_A;
3737 path = RF_PATH_B;
3742 for (i = path; i < path_max; i++) {
3748 "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n",
3765 "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n",
3784 enum rtw89_rf_path path)
3790 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0);
3791 rtw89_phy_write32_mask(rtwdev, tssi_en[path], BIT(31), 0x0);
3792 if (rtwdev->dbcc_en && path == RF_PATH_B)
3797 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1);
3798 rtw89_phy_write32_mask(rtwdev, tssi_en[path], BIT(31), 0x1);
3815 static void _bw_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
3827 rf_reg18 = rtw89_read_rf(rtwdev, path, reg_reg18_addr, RFREG_MASK);
3835 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_BW0, 0x3);
3836 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1 | (path << 8), B_P0_CFCH_BW1, 0xf);
3840 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_BW0, 0x3);
3841 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1 | (path << 8), B_P0_CFCH_BW1, 0xf);
3845 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_BW0, 0x2);
3846 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1 | (path << 8), B_P0_CFCH_BW1, 0xd);
3850 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_BW0, 0x1);
3851 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1 | (path << 8), B_P0_CFCH_BW1, 0xb);
3857 rtw89_write_rf(rtwdev, path, reg_reg18_addr, RFREG_MASK, rf_reg18);
3864 u8 kpath, path;
3870 for (path = 0; path < 2; path++) {
3871 if (!(kpath & BIT(path)))
3875 _bw_setting(rtwdev, path, bw, is_dav);
3877 _bw_setting(rtwdev, path, bw, is_dav);
3881 if (path == RF_PATH_B && rtwdev->hal.cv == CHIP_CAV) {
3892 static void _ch_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
3904 rf_reg18 = rtw89_read_rf(rtwdev, path, reg_reg18_addr, RFREG_MASK);
3924 rtw89_write_rf(rtwdev, path, reg_reg18_addr, RFREG_MASK, rf_reg18);
3931 u8 kpath, path;
3946 for (path = 0; path < 2; path++) {
3947 if (kpath & BIT(path)) {
3948 _ch_setting(rtwdev, path, central_ch, band, true);
3949 _ch_setting(rtwdev, path, central_ch, band, false);
3958 u8 path;
3962 for (path = 0; path < 2; path++) {
3963 if (!(kpath & BIT(path)))
3966 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x1);
3967 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M2, 0xa);
3983 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, val);
3984 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x0);
3991 int path;
3993 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
3994 lck->thermal[path] =
3995 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
3997 "[LCK] path=%d thermal=0x%x", path, lck->thermal[path]);
4004 int path = rtwdev->dbcc_en ? 2 : 1;
4012 for (i = 0; i < path; i++) {
4028 int path;
4030 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
4032 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
4033 delta = abs((int)cur_thermal - lck->thermal[path]);
4036 "[LCK] path=%d current thermal=0x%x delta=0x%x\n",
4037 path, cur_thermal, delta);
4123 u8 path;
4125 for (path = 0; path < 2; path++)
4126 _rck(rtwdev, path);
4160 u8 path, kpath;
4170 for (path = 0; path < 2; path++) {
4171 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
4172 if (!(kpath & BIT(path)))
4175 if (rtwdev->is_tssi_mode[path])
4176 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13),
4178 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
4179 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
4180 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_LO_SEL, rtwdev->dbcc_en);
4183 _set_rx_dck(rtwdev, phy, path, is_afe);
4189 _rx_dck_recover(rtwdev, path);
4193 is_fail = _rx_dck_rek_check(rtwdev, path);
4199 path, rek_cnt);
4201 rx_dck->thermal[path] = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
4202 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
4204 if (rtwdev->is_tssi_mode[path])
4205 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13),
4227 int path;
4235 for (path = 0; path < RF_PATH_NUM_8852C; path++) {
4237 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
4238 delta = abs((int)cur_thermal - rx_dck->thermal[path]);
4241 "[RX_DCK] path=%d current thermal=0x%x delta=0x%x\n",
4242 path, cur_thermal, delta);
4254 for (path = 0; path < RF_PATH_NUM_8852C; path++) {
4261 for (path = 0; path < RF_PATH_NUM_8852C; path++)
4298 u32 i, path = RF_PATH_A, path_max = RF_PATH_NUM_8852C;
4304 path = RF_PATH_A;
4307 path = RF_PATH_B;
4314 for (i = path; i < path_max; i++) {
4333 u32 i, path = RF_PATH_A, path_max = RF_PATH_NUM_8852C;
4345 path = RF_PATH_A;
4348 path = RF_PATH_B;
4355 for (i = path; i < path_max; i++) {
4427 u8 path;
4432 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++)
4433 _dpk_onoff(rtwdev, path, false);
4437 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++)
4438 _dpk_onoff(rtwdev, path, false);