realtek/rtw89/rtw8852c.c

402 				    "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
414 				    "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
544 				    "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
561 			    "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
591 			    "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
609 			    "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
635 			    "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
850 				    enum rtw89_rf_path path)
861 			reg = bb_gain_lna[i].gain_g[path];
863 			reg = bb_gain_lna[i].gain_a[path];
866 		val = gain->lna_gain[gain_band][path][i];
870 			reg = bb_gain_bypass_lna[i].gain_g[path];
873 			reg = bb_gain_bypass_lna[i].gain_a[path];
877 		val = gain->lna_gain_bypass[gain_band][path][i];
881 			reg = bb_gain_op1db_a.reg[i].lna[path];
883 			val = gain->lna_op1db[gain_band][path][i];
886 			reg = bb_gain_op1db_a.reg[i].tia_lna[path];
888 			val = gain->tia_lna_op1db[gain_band][path][i];
894 		reg = bb_gain_op1db_a.reg_tia0_lna6[path];
896 		val = gain->tia_lna_op1db[gain_band][path][7];
902 			reg = bb_gain_tia[i].gain_g[path];
904 			reg = bb_gain_tia[i].gain_a[path];
907 		val = gain->tia_gain[gain_band][path][i];
915 				     enum rtw89_rf_path path)
929 	if (rtwdev->dbcc_en && path == RF_PATH_B)
933 		offset_q0 = efuse_gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK];
943 	offset_q0 = -efuse_gain->offset[path][gain_band];
948 	rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], B_PATH0_R_G_OFST_MASK, tmp & 0xff);
951 	rtw89_phy_write32_idx(rtwdev, R_RPL_PATHAB, rpl_mask[path], tmp & 0xff, phy_idx);
952 	rtw89_phy_write32_idx(rtwdev, R_RSSI_M_PATHAB, rpl_tb_mask[path], tmp & 0xff, phy_idx);
1078 static void rtw8852c_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
1085 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
1086 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
1089 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
1090 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
1096 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
1097 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
1305 				      enum rtw89_rf_path path)
1307 	const struct rtw89_nbi_reg_def *nbi = &rtw8852c_nbi_reg_def[path];
1542 void rtw8852c_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1551 	if (path >= ARRAY_SIZE(path_cr_bases))
1554 	cr = path_cr_bases[path];
1569 void rtw8852c_bb_gpio_rfm(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1579 	if (src >= ARRAY_SIZE(masks) || path >= ARRAY_SIZE(path_cr_bases))
1583 	cr = path_cr_bases[path];
2475 void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
2477 	rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000);
2478 	rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
2479 	rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
2480 	rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
2509 		/* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
2775 	u8 path;
2779 	for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2780 		status->chains |= BIT(path);
2781 		status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);