Lines Matching refs:path
141 u8 path)
149 enum rtw89_rf_path path, bool is_bybb)
152 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
154 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
158 enum rtw89_rf_path path, bool is_bybb)
161 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1);
163 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0);
169 u8 path;
172 for (path = 0; path < RF_PATH_MAX; path++) {
173 if (!(kpath & BIT(path)))
178 rtwdev, path, 0x00, RR_MOD_MASK);
181 path, ret);
185 static void _dack_reset(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
268 enum rtw89_rf_path path, u8 index)
281 if (path == RF_PATH_A)
294 tmp |= dack->msbk_d[path][index][i + 12] << (i * 8);
303 tmp |= dack->msbk_d[path][index][i + 8] << (i * 8);
312 tmp |= dack->msbk_d[path][index][i + 4] << (i * 8);
321 tmp |= dack->msbk_d[path][index][i] << (i * 8);
329 tmp = (dack->biask_d[path][index] << 22) |
330 (dack->dadck_d[path][index] << 14);
339 static void _dack_reload(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
344 _dack_reload_by_path(rtwdev, path, index);
524 enum rtw89_rf_path path, bool is_afe)
529 "[RX_DCK] ==== S%d RX DCK (%s / CH%d / %s / by %s)====\n", path,
538 static void _rxbb_ofst_swap(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 rf_mode)
542 val_i = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_S1);
543 val_q = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_S1);
547 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_DIS, 0x1);
548 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, rf_mode);
549 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
550 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_DIS, 0x0);
557 static void _set_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 rf_mode)
562 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
563 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1);
567 rtwdev, path, RR_DCK, BIT(8));
569 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
572 path, ret);
574 _rxbb_ofst_swap(rtwdev, path, rf_mode);
580 u8 path;
586 for (path = 0; path < RF_PATH_NUM_8851B; path++) {
587 _rx_dck_info(rtwdev, phy, path, is_afe);
589 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
591 if (rtwdev->is_tssi_mode[path])
593 R_P0_TSSI_TRK + (path << 13),
596 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
597 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RF_RX);
598 _set_rx_dck(rtwdev, path, RF_RX);
599 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
601 if (rtwdev->is_tssi_mode[path])
603 R_P0_TSSI_TRK + (path << 13),
608 static void _iqk_sram(struct rtw89_dev *rtwdev, u8 path)
638 static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path)
640 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
641 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
642 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1);
645 static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path)
676 path, ret, fail1 || fail2, fail1, fail2);
682 u8 path, u8 ktype)
691 "[IQK]============ S%d ID_A_FLOK_COARSE ============\n", path);
693 iqk_cmd = 0x108 | (1 << (4 + path));
697 "[IQK]============ S%d ID_G_FLOK_COARSE ============\n", path);
699 iqk_cmd = 0x108 | (1 << (4 + path));
703 "[IQK]============ S%d ID_A_FLOK_FINE ============\n", path);
705 iqk_cmd = 0x308 | (1 << (4 + path));
709 "[IQK]============ S%d ID_G_FLOK_FINE ============\n", path);
711 iqk_cmd = 0x308 | (1 << (4 + path));
715 "[IQK]============ S%d ID_TXK ============\n", path);
717 iqk_cmd = 0x008 | (1 << (path + 4)) |
718 (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8);
722 "[IQK]============ S%d ID_RXAGC ============\n", path);
724 iqk_cmd = 0x708 | (1 << (4 + path)) | (path << 1);
728 "[IQK]============ S%d ID_RXK ============\n", path);
730 iqk_cmd = 0x008 | (1 << (path + 4)) |
731 (((0xc + iqk_info->iqk_bw[path]) & 0xf) << 8);
735 "[IQK]============ S%d ID_NBTXK ============\n", path);
739 iqk_cmd = 0x408 | (1 << (4 + path));
743 "[IQK]============ S%d ID_NBRXK ============\n", path);
747 iqk_cmd = 0x608 | (1 << (4 + path));
754 notready = _iqk_check_cal(rtwdev, path);
757 _iqk_sram(rtwdev, path);
762 path, ktype, iqk_cmd + 1, notready);
768 enum rtw89_phy_idx phy_idx, u8 path)
779 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, gp = %x\n", path, gp);
781 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM, g_idxrxgain[gp]);
782 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2, g_idxattc2[gp]);
787 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
789 rf_0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
794 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXAGC);
797 "[IQK]S%x, RXAGC 0x8008 = 0x%x, rxbb = %x\n", path,
799 rtw89_read_rf(rtwdev, path, RR_MOD, 0x003e0));
801 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
803 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK);
804 iqk_info->nb_rxcfir[path] =
807 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK);
810 "[IQK]S%x, WBRXK 0x8008 = 0x%x\n", path,
818 _iqk_sram(rtwdev, path);
821 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
822 MASKDWORD, iqk_info->nb_rxcfir[path] | 0x2);
823 iqk_info->is_wb_txiqk[path] = false;
825 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
827 iqk_info->is_wb_txiqk[path] = true;
831 "[IQK]S%x, kfail = 0x%x, 0x8%x3c = 0x%x\n", path, kfail,
832 1 << path, iqk_info->nb_rxcfir[path]);
837 enum rtw89_phy_idx phy_idx, u8 path)
851 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, gp = %x\n", path, gp);
860 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
862 rf_0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
866 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXAGC);
869 "[IQK]S%x, RXAGC 0x8008 = 0x%x, rxbb = %x\n", path,
871 rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_RXB));
873 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
875 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK);
876 iqk_info->nb_rxcfir[path] =
880 "[IQK]S%x, NBRXK 0x8008 = 0x%x\n", path,
883 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK);
886 "[IQK]S%x, WBRXK 0x8008 = 0x%x\n", path,
894 _iqk_sram(rtwdev, path);
897 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD,
898 iqk_info->nb_rxcfir[path] | 0x2);
899 iqk_info->is_wb_txiqk[path] = false;
901 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD,
903 iqk_info->is_wb_txiqk[path] = true;
907 "[IQK]S%x, kfail = 0x%x, 0x8%x3c = 0x%x\n", path, kfail,
908 1 << path, iqk_info->nb_rxcfir[path]);
913 u8 path)
925 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, gp = %x\n", path, gp);
934 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
936 rf_0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
940 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXAGC);
943 "[IQK]S%x, RXAGC 0x8008 = 0x%x, rxbb = %x\n", path,
945 rtw89_read_rf(rtwdev, path, RR_MOD, 0x003e0));
947 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
949 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK);
950 iqk_info->nb_rxcfir[path] =
954 "[IQK]S%x, NBRXK 0x8008 = 0x%x\n", path,
958 path, rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD));
964 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
966 iqk_info->is_wb_rxiqk[path] = false;
968 iqk_info->is_wb_rxiqk[path] = false;
972 "[IQK]S%x, kfail = 0x%x, 0x8%x3c = 0x%x\n", path, kfail,
973 1 << path, iqk_info->nb_rxcfir[path]);
979 u8 path)
988 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, gp = %x\n", path, gp);
990 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM, g_idxrxgain[gp]);
991 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2, g_idxattc2[gp]);
996 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
998 rf_0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
1002 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXAGC);
1006 path, rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD),
1007 rtw89_read_rf(rtwdev, path, RR_MOD, 0x003e0));
1009 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
1011 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK);
1012 iqk_info->nb_rxcfir[path] =
1016 "[IQK]S%x, NBRXK 0x8008 = 0x%x\n", path,
1020 path, rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD));
1026 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
1028 iqk_info->is_wb_rxiqk[path] = false;
1030 iqk_info->is_wb_rxiqk[path] = false;
1034 "[IQK]S%x, kfail = 0x%x, 0x8%x3c = 0x%x\n", path, kfail,
1035 1 << path, iqk_info->nb_rxcfir[path]);
1039 static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path)
1043 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_CKT, 0x1);
1045 if (iqk_info->iqk_bw[path] == RTW89_CHANNEL_WIDTH_80)
1052 enum rtw89_phy_idx phy_idx, u8 path)
1062 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, a_power_range[gp]);
1063 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, a_track_range[gp]);
1064 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, a_gain_bb[gp]);
1073 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
1074 iqk_info->nb_txcfir[path] =
1077 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1079 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK);
1086 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
1087 MASKDWORD, iqk_info->nb_txcfir[path] | 0x2);
1088 iqk_info->is_wb_txiqk[path] = false;
1090 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
1092 iqk_info->is_wb_txiqk[path] = true;
1096 "[IQK]S%x, kfail = 0x%x, 0x8%x38 = 0x%x\n", path, kfail,
1097 1 << path, iqk_info->nb_txcfir[path]);
1102 enum rtw89_phy_idx phy_idx, u8 path)
1112 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, g_power_range[gp]);
1113 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, g_track_range[gp]);
1114 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, g_gain_bb[gp]);
1123 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
1124 iqk_info->nb_txcfir[path] =
1127 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1129 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK);
1136 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
1137 MASKDWORD, iqk_info->nb_txcfir[path] | 0x2);
1138 iqk_info->is_wb_txiqk[path] = false;
1140 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
1142 iqk_info->is_wb_txiqk[path] = true;
1146 "[IQK]S%x, kfail = 0x%x, 0x8%x38 = 0x%x\n", path, kfail,
1147 1 << path, iqk_info->nb_txcfir[path]);
1152 u8 path)
1162 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, a_power_range[gp]);
1163 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, a_track_range[gp]);
1164 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, a_gain_bb[gp]);
1173 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
1174 iqk_info->nb_txcfir[path] =
1182 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
1184 iqk_info->is_wb_rxiqk[path] = false;
1186 iqk_info->is_wb_rxiqk[path] = false;
1190 "[IQK]S%x, kfail = 0x%x, 0x8%x38 = 0x%x\n", path, kfail,
1191 1 << path, iqk_info->nb_txcfir[path]);
1196 u8 path)
1206 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, g_power_range[gp]);
1207 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, g_track_range[gp]);
1208 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, g_gain_bb[gp]);
1217 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
1218 iqk_info->nb_txcfir[path] =
1219 rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8),
1227 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
1229 iqk_info->is_wb_rxiqk[path] = false;
1231 iqk_info->is_wb_rxiqk[path] = false;
1235 "[IQK]S%x, kfail = 0x%x, 0x8%x38 = 0x%x\n", path, kfail,
1236 1 << path, iqk_info->nb_txcfir[path]);
1241 u8 path)
1265 0x00000109 | (1 << (4 + path)));
1266 fail |= _iqk_check_cal(rtwdev, path);
1271 0x00000309 | (1 << (4 + path)));
1272 fail |= _iqk_check_cal(rtwdev, path);
1294 u8 path)
1318 0x00000109 | (1 << (4 + path)));
1319 fail |= _iqk_check_cal(rtwdev, path);
1325 0x00000309 | (1 << (4 + path)));
1326 fail |= _iqk_check_cal(rtwdev, path);
1347 static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path)
1351 switch (iqk_info->iqk_band[path]) {
1368 u8 path)
1377 _iqk_txk_setting(rtwdev, path);
1378 if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
1379 lok_is_fail = _iqk_2g_lok(rtwdev, phy_idx, path);
1381 lok_is_fail = _iqk_5g_lok(rtwdev, phy_idx, path);
1388 if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
1389 iqk_info->iqk_tx_fail[0][path] =
1390 _iqk_2g_nbtxk(rtwdev, phy_idx, path);
1392 iqk_info->iqk_tx_fail[0][path] =
1393 _iqk_5g_nbtxk(rtwdev, phy_idx, path);
1395 if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
1396 iqk_info->iqk_tx_fail[0][path] =
1397 _txk_2g_group_sel(rtwdev, phy_idx, path);
1399 iqk_info->iqk_tx_fail[0][path] =
1400 _txk_5g_group_sel(rtwdev, phy_idx, path);
1403 _iqk_rxclk_setting(rtwdev, path);
1404 _iqk_rxk_setting(rtwdev, path);
1405 _adc_fifo_rst(rtwdev, phy_idx, path);
1408 if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
1409 iqk_info->iqk_rx_fail[0][path] =
1410 _iqk_2g_nbrxk(rtwdev, phy_idx, path);
1412 iqk_info->iqk_rx_fail[0][path] =
1413 _iqk_5g_nbrxk(rtwdev, phy_idx, path);
1415 if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
1416 iqk_info->iqk_rx_fail[0][path] =
1417 _rxk_2g_group_sel(rtwdev, phy_idx, path);
1419 iqk_info->iqk_rx_fail[0][path] =
1420 _rxk_5g_group_sel(rtwdev, phy_idx, path);
1484 u8 path)
1490 iqk_info->iqk_band[path] = chan->band_type;
1491 iqk_info->iqk_bw[path] = chan->band_width;
1492 iqk_info->iqk_ch[path] = chan->channel;
1493 iqk_info->iqk_table_idx[path] = idx;
1496 path, phy, rtwdev->dbcc_en ? "on" : "off",
1497 iqk_info->iqk_band[path] == 0 ? "2G" :
1498 iqk_info->iqk_band[path] == 1 ? "5G" : "6G",
1499 iqk_info->iqk_ch[path],
1500 iqk_info->iqk_bw[path] == 0 ? "20M" :
1501 iqk_info->iqk_bw[path] == 1 ? "40M" : "80M");
1505 path, iqk_info->syn1to2);
1509 u8 path)
1511 _iqk_by_path(rtwdev, phy_idx, path);
1514 static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path)
1522 fail = _iqk_check_cal(rtwdev, path);
1534 enum rtw89_phy_idx phy_idx, u8 path)
1539 static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path)
1543 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1549 enum rtw89_phy_idx phy_idx, u8 path)
1559 u8 idx, path;
1578 for (path = 0; path < RF_PATH_NUM_8851B; path++) {
1579 iqk_info->lok_cor_fail[idx][path] = false;
1580 iqk_info->lok_fin_fail[idx][path] = false;
1581 iqk_info->iqk_tx_fail[idx][path] = false;
1582 iqk_info->iqk_rx_fail[idx][path] = false;
1583 iqk_info->iqk_table_idx[path] = 0x0;
1589 enum rtw89_phy_idx phy_idx, u8 path)
1605 _iqk_get_ch_info(rtwdev, phy_idx, path);
1608 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path);
1609 _iqk_macbb_setting(rtwdev, phy_idx, path);
1610 _iqk_preset(rtwdev, path);
1611 _iqk_start_iqk(rtwdev, phy_idx, path);
1612 _iqk_restore(rtwdev, path);
1613 _iqk_afebb_restore(rtwdev, phy_idx, path);
1615 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path);
1627 u32 reg_bkup[][DPK_KIP_REG_NUM_8851B], u8 path)
1632 reg_bkup[path][i] =
1633 rtw89_phy_read32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD);
1636 reg[i] + (path << 8), reg_bkup[path][i]);
1641 u32 rf_bkup[][DPK_RF_REG_NUM_8851B], u8 path)
1646 rf_bkup[path][i] = rtw89_read_rf(rtwdev, path, rf_reg[i], RFREG_MASK);
1649 path, rf_reg[i], rf_bkup[path][i]);
1654 u32 reg_bkup[][DPK_KIP_REG_NUM_8851B], u8 path)
1659 rtw89_phy_write32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD,
1660 reg_bkup[path][i]);
1664 reg[i] + (path << 8), reg_bkup[path][i]);
1669 u32 rf_bkup[][DPK_RF_REG_NUM_8851B], u8 path)
1674 rtw89_write_rf(rtwdev, path, rf_reg[i], RFREG_MASK, rf_bkup[path][i]);
1677 "[DPK] Reload RF S%d 0x%x = %x\n", path,
1678 rf_reg[i], rf_bkup[path][i]);
1683 enum rtw89_rf_path path, enum dpk_id id)
1689 dpk_cmd = ((id << 8) | (0x19 + path * 0x12));
1722 static void _dpk_onoff(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1726 u8 kidx = dpk->cur_idx[path];
1730 val = dpk->is_dpk_enable * off_reverse * dpk->bp[path][kidx].path_ok;
1732 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
1735 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path,
1739 static void _dpk_init(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
1743 u8 kidx = dpk->cur_idx[path];
1745 dpk->bp[path][kidx].path_ok = 0;
1749 enum rtw89_rf_path path)
1754 u8 kidx = dpk->cur_idx[path];
1756 dpk->bp[path][kidx].band = chan->band_type;
1757 dpk->bp[path][kidx].ch = chan->band_width;
1758 dpk->bp[path][kidx].bw = chan->channel;
1762 path, dpk->cur_idx[path], phy,
1763 rtwdev->is_tssi_mode[path] ? "on" : "off",
1765 dpk->bp[path][kidx].band == 0 ? "2G" :
1766 dpk->bp[path][kidx].band == 1 ? "5G" : "6G",
1767 dpk->bp[path][kidx].ch,
1768 dpk->bp[path][kidx].bw == 0 ? "20M" :
1769 dpk->bp[path][kidx].bw == 1 ? "40M" :
1770 dpk->bp[path][kidx].bw == 2 ? "80M" : "160M");
1773 static void _dpk_rxagc_onoff(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1776 if (path == RF_PATH_A)
1781 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d RXAGC is %s\n", path,
1785 static void _dpk_bb_afe_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
1787 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(16 + path), 0x1);
1788 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(20 + path), 0x0);
1789 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(24 + path), 0x1);
1790 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(28 + path), 0x0);
1791 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), MASKDWORD, 0xd801dffd);
1795 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(20 + path), 0x1);
1796 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(28 + path), 0x1);
1798 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d BB/AFE setting\n", path);
1801 static void _dpk_bb_afe_restore(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
1803 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG, 0x0);
1804 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(16 + path), 0x1);
1805 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(20 + path), 0x0);
1806 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(24 + path), 0x1);
1807 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(28 + path), 0x0);
1808 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), MASKDWORD, 0x00000000);
1809 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), B_P0_TXCK_ALL, 0x00);
1810 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(16 + path), 0x0);
1811 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(24 + path), 0x0);
1813 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d BB/AFE restore\n", path);
1816 static void _dpk_tssi_pause(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1819 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13),
1822 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path,
1826 static void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
1830 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80) {
1833 } else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40) {
1842 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" :
1843 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M");
1847 enum rtw89_rf_path path, bool force)
1849 rtw89_phy_write32_mask(rtwdev, R_TXPWRB + (path << 13), B_TXPWRB_ON, force);
1850 rtw89_phy_write32_mask(rtwdev, R_TXPWRB_H + (path << 13), B_TXPWRB_RDY, force);
1853 path, force ? "on" : "off");
1869 enum rtw89_rf_path path, bool ctrl_by_kip)
1871 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13),
1879 enum rtw89_rf_path path, u8 kidx)
1882 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
1883 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
1886 _dpk_kip_control_rfc(rtwdev, path, true);
1887 _dpk_one_shot(rtwdev, phy, path, D_KIP_PRESET);
1891 enum rtw89_rf_path path)
1893 _dpk_one_shot(rtwdev, phy, path, D_KIP_RESTORE);
1894 _dpk_kip_control_rfc(rtwdev, path, false);
1895 _dpk_txpwr_bb_force(rtwdev, path, false);
1897 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path);
1900 static void _dpk_kset_query(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
1904 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0x10);
1907 rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), B_RPT_PER_KSET) - 1;
1910 static void _dpk_para_query(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
1925 para = rtw89_phy_read32_mask(rtwdev, reg[kidx][cur_k_set] + (path << 8),
1928 dpk->bp[path][kidx].txagc_dpk = (para >> 10) & 0x3f;
1929 dpk->bp[path][kidx].ther_dpk = (para >> 26) & 0x3f;
1933 dpk->cur_k_set, dpk->bp[path][kidx].ther_dpk,
1934 dpk->bp[path][kidx].txagc_dpk);
1937 static bool _dpk_sync_check(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
1948 dpk->corr_idx[path][kidx] = corr_idx;
1949 dpk->corr_val[path][kidx] = corr_val;
1961 path, corr_idx, corr_val, dc_i, dc_q);
1963 dpk->dc_i[path][kidx] = dc_i;
1964 dpk->dc_q[path][kidx] = dc_q;
1974 path, rxbb,
1985 enum rtw89_rf_path path, u8 dbm,
1992 "[DPK] set S%d txagc to %ddBm\n", path, dbm);
1993 rtw89_phy_write32_mask(rtwdev, R_TXPWRB + (path << 13),
1997 _dpk_one_shot(rtwdev, phy, path, D_TXAGC);
1998 _dpk_kset_query(rtwdev, path);
2002 enum rtw89_rf_path path, u8 kidx)
2004 _dpk_kip_control_rfc(rtwdev, path, false);
2006 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
2007 _dpk_kip_control_rfc(rtwdev, path, true);
2009 _dpk_one_shot(rtwdev, phy, path, D_RXAGC);
2010 return _dpk_sync_check(rtwdev, path, kidx);
2014 enum rtw89_rf_path path)
2019 rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), B_DPD_LBK, 0x1);
2022 _dpk_kip_control_rfc(rtwdev, path, false);
2024 cur_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_RXB);
2025 rf_11 = rtw89_read_rf(rtwdev, path, RR_TXIG, RFREG_MASK);
2026 reg_81cc = rtw89_phy_read32_mask(rtwdev, R_KIP_IQP + (path << 8),
2029 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
2030 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x3);
2031 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0xd);
2032 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RXB, 0x1f);
2034 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x12);
2035 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_SW, 0x3);
2037 _dpk_kip_control_rfc(rtwdev, path, true);
2041 _dpk_one_shot(rtwdev, phy, path, LBK_RXIQK);
2043 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path,
2044 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD));
2046 _dpk_kip_control_rfc(rtwdev, path, false);
2048 rtw89_write_rf(rtwdev, path, RR_TXIG, RFREG_MASK, rf_11);
2049 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RXB, cur_rxbb);
2050 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_SW, reg_81cc);
2054 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_DI, 0x1);
2056 _dpk_kip_control_rfc(rtwdev, path, true);
2059 static void _dpk_rf_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
2063 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) {
2064 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50521);
2065 rtw89_write_rf(rtwdev, path, RR_MOD_V1, RR_MOD_MASK, RF_DPK);
2066 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTC, 0x0);
2067 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTR, 0x7);
2069 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK,
2071 rtw89_write_rf(rtwdev, path, RR_MOD_V1, RR_MOD_MASK, RF_DPK);
2072 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RAA2_SATT, 0x3);
2075 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1);
2076 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1);
2077 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0);
2078 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_EBW, 0x0);
2081 static void _dpk_bypass_rxiqc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
2083 rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), B_DPD_LBK, 0x1);
2084 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD, 0x40000002);
2115 enum rtw89_rf_path path, u8 kidx)
2117 _dpk_one_shot(rtwdev, phy, path, D_GAIN_LOSS);
2118 _dpk_kip_set_txagc(rtwdev, phy, path, 0xff, false);
2120 rtw89_phy_write32_mask(rtwdev, R_DPK_GL + (path << 8), B_DPK_GL_A1, 0xf078);
2121 rtw89_phy_write32_mask(rtwdev, R_DPK_GL + (path << 8), B_DPK_GL_A0, 0x0);
2173 enum rtw89_rf_path path, u8 kidx, u8 init_xdbm, u8 loss_only)
2187 is_fail = _dpk_kip_set_rxagc(rtwdev, phy, path, kidx);
2197 _dpk_one_shot(rtwdev, phy, path, D_SYNC);
2202 if (dpk->bp[path][kidx].band == RTW89_BAND_2G)
2203 _dpk_bypass_rxiqc(rtwdev, path);
2205 _dpk_lbk_rxiqk(rtwdev, phy, path);
2211 tmp_gl_idx = _dpk_gainloss(rtwdev, phy, path, kidx);
2231 _dpk_kip_set_txagc(rtwdev, phy, path, tmp_dbm, true);
2244 _dpk_kip_set_txagc(rtwdev, phy, path, tmp_dbm, true);
2251 _dpk_kip_control_rfc(rtwdev, path, false);
2252 tmp_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_RXB);
2255 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RXB, tmp_rxbb);
2260 _dpk_kip_control_rfc(rtwdev, path, true);
2312 enum rtw89_rf_path path, u8 kidx)
2326 _dpk_one_shot(rtwdev, phy, path, D_MDPK_IDL);
2357 enum rtw89_rf_path path, u8 kidx, bool is_execute)
2372 rtw89_phy_write32_mask(rtwdev, R_DPK_GN + (path << 8),
2374 rtw89_phy_write32_mask(rtwdev, R_DPK_GN + (path << 8),
2377 _dpk_one_shot(rtwdev, phy, path, D_GAIN_NORM);
2379 rtw89_phy_write32_mask(rtwdev, reg[kidx][cur_k_set] + (path << 8),
2383 dpk->bp[path][kidx].gs =
2384 rtw89_phy_read32_mask(rtwdev, reg[kidx][cur_k_set] + (path << 8),
2389 enum rtw89_rf_path path, u8 kidx)
2393 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1);
2394 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x0);
2395 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2398 dpk->bp[path][kidx].path_ok =
2399 dpk->bp[path][kidx].path_ok | BIT(dpk->cur_k_set);
2402 path, kidx, dpk->bp[path][kidx].path_ok);
2404 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2405 B_DPD_MEN, dpk->bp[path][kidx].path_ok);
2407 _dpk_gain_normalize(rtwdev, phy, path, kidx, false);
2411 enum rtw89_rf_path path)
2414 u8 kidx = dpk->cur_idx[path];
2418 if (dpk->bp[path][kidx].band != RTW89_BAND_2G)
2421 _dpk_kip_control_rfc(rtwdev, path, false);
2422 _rfk_rf_direct_cntrl(rtwdev, path, false);
2423 rtw89_write_rf(rtwdev, path, RR_BBDC, RFREG_MASK, 0x03ffd);
2425 _dpk_rf_setting(rtwdev, path, kidx);
2426 _set_rx_dck(rtwdev, path, RF_DPK);
2429 _dpk_kip_preset(rtwdev, phy, path, kidx);
2430 _dpk_txpwr_bb_force(rtwdev, path, true);
2431 _dpk_kip_set_txagc(rtwdev, phy, path, init_xdbm, true);
2432 _dpk_tpg_sel(rtwdev, path, kidx);
2433 is_fail = _dpk_agc(rtwdev, phy, path, kidx, init_xdbm, false);
2437 _dpk_idl_mpa(rtwdev, phy, path, kidx);
2438 _dpk_para_query(rtwdev, path, kidx);
2440 _dpk_on(rtwdev, phy, path, kidx);
2442 _dpk_kip_control_rfc(rtwdev, path, false);
2443 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RF_RX);
2445 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d]_K%d %s\n", path, kidx,
2458 u8 path;
2460 for (path = 0; path < RF_PATH_NUM_8851B; path++)
2461 dpk->cur_idx[path] = 0;
2463 for (path = 0; path < RF_PATH_NUM_8851B; path++) {
2464 if (!(kpath & BIT(path)))
2466 _dpk_bkup_kip(rtwdev, dpk_kip_reg, kip_bkup, path);
2467 _dpk_bkup_rf(rtwdev, dpk_rf_reg, rf_bkup, path);
2468 _dpk_information(rtwdev, phy, path);
2469 _dpk_init(rtwdev, path);
2471 if (rtwdev->is_tssi_mode[path])
2472 _dpk_tssi_pause(rtwdev, path, true);
2475 for (path = 0; path < RF_PATH_NUM_8851B; path++) {
2476 if (!(kpath & BIT(path)))
2481 path, dpk->cur_idx[path]);
2483 _dpk_rxagc_onoff(rtwdev, path, false);
2484 _rfk_drf_direct_cntrl(rtwdev, path, false);
2485 _dpk_bb_afe_setting(rtwdev, path);
2487 is_fail = _dpk_main(rtwdev, phy, path);
2488 _dpk_onoff(rtwdev, path, is_fail);
2491 for (path = 0; path < RF_PATH_NUM_8851B; path++) {
2492 if (!(kpath & BIT(path)))
2495 _dpk_kip_restore(rtwdev, phy, path);
2496 _dpk_reload_kip(rtwdev, dpk_kip_reg, kip_bkup, path);
2497 _dpk_reload_rf(rtwdev, dpk_rf_reg, rf_bkup, path);
2498 _dpk_bb_afe_restore(rtwdev, path);
2499 _dpk_rxagc_onoff(rtwdev, path, true);
2501 if (rtwdev->is_tssi_mode[path])
2502 _dpk_tssi_pause(rtwdev, path, false);
2523 u8 path, kidx;
2527 for (path = 0; path < RF_PATH_NUM_8851B; path++) {
2528 kidx = dpk->cur_idx[path];
2532 path, kidx, dpk->bp[path][kidx].ch);
2534 txagc_rf = rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
2536 txagc_bb = rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
2538 txagc_bb_tp = rtw89_phy_read32_mask(rtwdev, R_TXAGC_BTP + (path << 13),
2541 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8),
2543 cur_ther = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8),
2545 txagc_ofst = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8),
2547 pwsf_tssi_ofst = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8),
2551 delta_ther = cur_ther - dpk->bp[path][kidx].ther_dpk;
2557 delta_ther, cur_ther, dpk->bp[path][kidx].ther_dpk);
2561 txagc_rf - dpk->bp[path][kidx].txagc_dpk,
2562 txagc_rf, dpk->bp[path][kidx].txagc_dpk);
2578 R_DPD_BND + (path << 8) + (kidx << 2),
2584 static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
2591 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path);
2593 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
2595 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
2596 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
2599 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
2602 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240);
2605 false, rtwdev, path, RR_RCKS, BIT(3));
2607 rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA);
2612 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val);
2613 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
2616 rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK));
2620 enum rtw89_rf_path path)
2634 enum rtw89_rf_path path)
2641 enum rtw89_rf_path path)
2647 enum rtw89_rf_path path)
2653 enum rtw89_rf_path path)
2697 if (path == RF_PATH_A) {
2752 enum rtw89_rf_path path)
2758 enum rtw89_rf_path path)
2769 enum rtw89_rf_path path, bool all)
2780 enum rtw89_rf_path path)
2786 enum rtw89_rf_path path)
2793 enum rtw89_rf_path path)
2947 enum rtw89_rf_path path)
2960 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", path, gidx);
2965 de_1st = tssi_info->tssi_mcs[path][gidx_1st];
2966 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
2970 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
2971 path, val, de_1st, de_2nd);
2973 val = tssi_info->tssi_mcs[path][gidx];
2976 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
2983 enum rtw89_rf_path path)
2996 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
2997 path, tgidx);
3002 tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
3003 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
3007 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
3008 path, val, tde_1st, tde_2nd);
3010 val = tssi_info->tssi_trim[path][tgidx];
3013 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
3014 path, val);
3040 "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n",
3057 "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n",
3075 static void _tssi_alimentk_dump_result(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
3080 R_TSSI_PA_K1 + (path << 13),
3081 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K1 + (path << 13), MASKDWORD),
3082 R_TSSI_PA_K2 + (path << 13),
3083 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K2 + (path << 13), MASKDWORD),
3084 R_P0_TSSI_ALIM1 + (path << 13),
3085 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD),
3086 R_P0_TSSI_ALIM3 + (path << 13),
3087 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD),
3088 R_TSSI_PA_K5 + (path << 13),
3089 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K5 + (path << 13), MASKDWORD),
3090 R_P0_TSSI_ALIM2 + (path << 13),
3091 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD),
3092 R_P0_TSSI_ALIM4 + (path << 13),
3093 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD),
3094 R_TSSI_PA_K8 + (path << 13),
3095 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K8 + (path << 13), MASKDWORD));
3099 enum rtw89_phy_idx phy, enum rtw89_rf_path path)
3107 "======>%s phy=%d path=%d\n", __func__, phy, path);
3120 if (tssi_info->alignment_done[path][band]) {
3121 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD,
3122 tssi_info->alignment_value[path][band][0]);
3123 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD,
3124 tssi_info->alignment_value[path][band][1]);
3125 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD,
3126 tssi_info->alignment_value[path][band][2]);
3127 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD,
3128 tssi_info->alignment_value[path][band][3]);
3131 _tssi_alimentk_dump_result(rtwdev, path);
3197 "[LCK] path=%d thermal=0x%x", RF_PATH_A, lck->thermal[RF_PATH_A]);
3234 "[LCK] path=%d current thermal=0x%x delta=0x%x\n",
3402 static void _bw_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
3410 rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK);
3413 "[RFK]Invalid RF_0x18 for Path-%d\n", path);
3437 rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18);
3439 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set %x at path%d, %x =0x%x\n",
3440 bw, path, reg18_addr,
3441 rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK));
3528 static void _ch_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
3537 rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK);
3550 if (path == RF_PATH_A && dav)
3553 rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18);
3555 rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 0);
3556 rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 1);
3560 central_ch, path, reg18_addr,
3561 rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK));
3571 enum rtw89_rf_path path)
3573 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x1);
3574 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M2, 0x12);
3577 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x1b);
3579 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x13);
3581 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0xb);
3583 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x3);
3585 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set S%d RXBB BW 0x3F = 0x%x\n", path,
3586 rtw89_read_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB));
3588 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x0);
3594 u8 kpath, path;
3598 for (path = 0; path < RF_PATH_NUM_8851B; path++) {
3599 if (!(kpath & BIT(path)))
3602 _set_rxbb_bw(rtwdev, bw, path);