Lines Matching defs:wl
1850 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/
2004 struct rtw89_btc_wl_info wl;
2452 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
2453 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
2454 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2478 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2479 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2480 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2484 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2485 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2603 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2627 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2654 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
3553 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
6282 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
6286 chip->ops->cfg_ctrl_path(rtwdev, wl);