realtek/rtw88/phy.c

1530 				       u8 bw, u8 rs, u8 ch, s8 pwr_limit)
1541 	if (regd >= RTW_REGD_MAX || bw >= RTW_CHANNEL_WIDTH_MAX ||
1544 		     "wrong txpwr_lmt regd=%u, band=%u bw=%u, rs=%u, ch_idx=%u, pwr_limit=%d\n",
1545 		     regd, band, bw, rs, ch_idx, pwr_limit);
1550 		hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit;
1551 		ww = hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx];
1553 		hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1555 		hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit;
1556 		ww = hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx];
1558 		hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1565 		      u8 bw, u8 ch_idx, u8 rs_ht, u8 rs_vht)
1569 	s8 lmt_ht = hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx];
1570 	s8 lmt_vht = hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx];
1576 		hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx] = lmt_vht;
1579 		hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx] = lmt_ht;
1584 rtw_xref_txpwr_lmt_by_rs(struct rtw_dev *rtwdev, u8 regd, u8 bw, u8 ch_idx)
1594 		rtw_xref_5g_txpwr_lmt(rtwdev, regd, bw, ch_idx, rs_ht, rs_vht);
1600 rtw_xref_5g_txpwr_lmt_by_ch(struct rtw_dev *rtwdev, u8 regd, u8 bw)
1605 		rtw_xref_txpwr_lmt_by_rs(rtwdev, regd, bw, ch_idx);
1612 	u8 bw;
1614 	for (bw = RTW_CHANNEL_WIDTH_20; bw <= RTW_CHANNEL_WIDTH_40; bw++)
1615 		rtw_xref_5g_txpwr_lmt_by_ch(rtwdev, regd, bw);
1628 __cfg_txpwr_lmt_by_alt(struct rtw_hal *hal, u8 regd, u8 regd_alt, u8 bw, u8 rs)
1633 		hal->tx_pwr_limit_2g[regd][bw][rs][ch] =
1634 			hal->tx_pwr_limit_2g[regd_alt][bw][rs][ch];
1637 		hal->tx_pwr_limit_5g[regd][bw][rs][ch] =
1638 			hal->tx_pwr_limit_5g[regd_alt][bw][rs][ch];
1644 	u8 bw, rs;
1646 	for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
1649 					       bw, rs);
1664 					   p->bw, p->rs, p->ch, p->txpwr_lmt);
2026 				     enum rtw_bandwidth bw, u8 rf_path,
2045 		bw = RTW_CHANNEL_WIDTH_20;
2049 		bw = min_t(u8, bw, RTW_CHANNEL_WIDTH_40);
2052 	for (cur_bw = RTW_CHANNEL_WIDTH_20; cur_bw <= bw; cur_bw++) {
2069 	WARN(1, "invalid arguments, band=%d, bw=%d, path=%d, rate=%d, ch=%d\n",
2070 	     band, bw, rf_path, rate, channel);
2095 void rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path, u8 rate, u8 bw,
2116 						      bw, rate, group);
2122 						      bw, rate, group);
2126 	*limit = rtw_phy_get_tx_power_limit(rtwdev, band, bw, path,
2170 	u8 bw;
2178 	bw = hal->current_band_width;
2182 						     bw, ch, regd);
2274 __rtw_phy_tx_power_limit_config(struct rtw_hal *hal, u8 regd, u8 bw, u8 rs)
2281 		hal->tx_pwr_limit_2g[regd][bw][rs][ch] -= base;
2286 		hal->tx_pwr_limit_5g[regd][bw][rs][ch] -= base;
2292 	u8 regd, bw, rs;
2298 		for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
2300 				__rtw_phy_tx_power_limit_config(hal, regd, bw, rs);
2304 					u8 regd, u8 bw, u8 rs)
2312 		hal->tx_pwr_limit_2g[regd][bw][rs][ch] = max_power_index;
2316 		hal->tx_pwr_limit_5g[regd][bw][rs][ch] = max_power_index;
2322 	u8 regd, path, rate, rs, bw;
2334 		for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
2336 				rtw_phy_init_tx_power_limit(rtwdev, regd, bw,