rtlwifi/rtl8192c/phy_common.c

75 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
76 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
129 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
130 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
171 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
181 	if (rtlphy->rf_type == RF_1T2R) {
186 		rtlphy->pwrgroup_cnt = 0;
200 	rtlphy->cck_high_power =
213 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
216 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
220 			rtlphy->pwrgroup_cnt,
221 			rtlphy->mcs_txpwrlevel_origoffset
222 			[rtlphy->pwrgroup_cnt][0]);
225 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
229 			rtlphy->pwrgroup_cnt,
230 			rtlphy->mcs_txpwrlevel_origoffset
231 			[rtlphy->pwrgroup_cnt][1]);
234 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
238 			rtlphy->pwrgroup_cnt,
239 			rtlphy->mcs_txpwrlevel_origoffset
240 			[rtlphy->pwrgroup_cnt][6]);
243 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] =
247 			rtlphy->pwrgroup_cnt,
248 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
252 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
256 			rtlphy->pwrgroup_cnt,
257 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
261 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
265 			rtlphy->pwrgroup_cnt,
266 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
270 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
274 			rtlphy->pwrgroup_cnt,
275 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
279 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
283 			rtlphy->pwrgroup_cnt,
284 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
288 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] =
292 			rtlphy->pwrgroup_cnt,
293 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
297 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] =
301 			rtlphy->pwrgroup_cnt,
302 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
306 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] =
310 			rtlphy->pwrgroup_cnt,
311 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
315 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] =
319 			rtlphy->pwrgroup_cnt,
320 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
324 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] =
328 			rtlphy->pwrgroup_cnt,
329 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
333 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] =
337 			rtlphy->pwrgroup_cnt,
338 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
342 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] =
346 			rtlphy->pwrgroup_cnt,
347 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
351 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] =
355 			rtlphy->pwrgroup_cnt,
356 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
359 		rtlphy->pwrgroup_cnt++;
367 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
369 	rtlphy->default_initialgain[0] =
371 	rtlphy->default_initialgain[1] =
373 	rtlphy->default_initialgain[2] =
375 	rtlphy->default_initialgain[3] =
380 		rtlphy->default_initialgain[0],
381 		rtlphy->default_initialgain[1],
382 		rtlphy->default_initialgain[2],
383 		rtlphy->default_initialgain[3]);
385 	rtlphy->framesync = (u8)rtl_get_bbreg(hw,
387 	rtlphy->framesync_c34 = rtl_get_bbreg(hw,
392 		ROFDM0_RXDETECTOR3, rtlphy->framesync);
398 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
400 	rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
401 	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
402 	rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
403 	rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
405 	rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
406 	rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
407 	rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
408 	rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
410 	rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
411 	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
413 	rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
414 	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
416 	rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
418 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
421 	rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
422 	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
423 	rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
424 	rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
426 	rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
427 	rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
428 	rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
429 	rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
431 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
432 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
434 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
435 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
437 	rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
438 	rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
439 	rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
440 	rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
442 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
443 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
444 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
445 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
447 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
448 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
449 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
450 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
452 	rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
453 	rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
454 	rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
455 	rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
457 	rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
458 	rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
459 	rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
460 	rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
462 	rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
463 	rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
464 	rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
465 	rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
467 	rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
468 	rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
469 	rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
470 	rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
472 	rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
473 	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
474 	rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
475 	rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
477 	rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
478 	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
486 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
491 	txpwr_level = rtlphy->cur_cck_txpwridx;
494 	txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
501 	txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
514 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
522 	if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
527 	} else if (get_rf_type(rtlphy) == RF_2T2R) {
540 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
542 	rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
543 	rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
567 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
591 	rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
656 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
658 	u8 tmp_bw = rtlphy->current_chan_bw;
660 	if (rtlphy->set_bwmode_inprogress)
662 	rtlphy->set_bwmode_inprogress = true;
668 		rtlphy->set_bwmode_inprogress = false;
669 		rtlphy->current_chan_bw = tmp_bw;
678 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
682 		"switch to channel%d\n", rtlphy->current_channel);
686 		if (!rtlphy->sw_chnl_inprogress)
689 		    (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
690 		     &rtlphy->sw_chnl_step, &delay)) {
696 			rtlphy->sw_chnl_inprogress = false;
707 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
710 	if (rtlphy->sw_chnl_inprogress)
712 	if (rtlphy->set_bwmode_inprogress)
714 	WARN_ONCE((rtlphy->current_channel > 14),
716 	rtlphy->sw_chnl_inprogress = true;
717 	rtlphy->sw_chnl_stage = 0;
718 	rtlphy->sw_chnl_step = 0;
723 		rtlphy->sw_chnl_inprogress = false;
727 		rtlphy->sw_chnl_inprogress = false;
736 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
741 		    rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
782 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
791 	u8 num_total_rfpath = rtlphy->num_total_rfpath;
863 				rtlphy->rfreg_chnlval[rfpath] =
864 				    ((rtlphy->rfreg_chnlval[rfpath] &
870 					      rtlphy->rfreg_chnlval[rfpath]);
1198 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1216 						rtlphy->adda_backup, 16);
1218 					       rtlphy->iqk_mac_backup);
1222 		rtlphy->rfpi_enable =
1227 	if (!rtlphy->rfpi_enable)
1230 		rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
1231 		rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
1232 		rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
1242 					    rtlphy->iqk_mac_backup);
1301 	rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
1302 	rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
1303 	rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
1309 		if (!rtlphy->rfpi_enable)
1312 						  rtlphy->adda_backup, 16);
1314 						 rtlphy->iqk_mac_backup);
1353 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1378 						  rtlphy->iqk_bb_backup, 10);
1440 		rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
1441 		rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
1443 		rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
1444 		rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
1449 		rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
1450 		rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
1464 					rtlphy->iqk_bb_backup, 10);
1505 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1510 		iotype, rtlphy->set_io_inprogress);
1529 	if (postprocessing && !rtlphy->set_io_inprogress) {
1530 		rtlphy->set_io_inprogress = true;
1531 		rtlphy->current_io_type = iotype;
1544 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1549 		rtlphy->current_io_type, rtlphy->set_io_inprogress);
1550 	switch (rtlphy->current_io_type) {
1552 		dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
1554 		rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1557 		rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
1564 			rtlphy->current_io_type);
1567 	rtlphy->set_io_inprogress = false;
1569 		"(%#x)\n", rtlphy->current_io_type);