Lines Matching refs:rtlphy
144 struct rtl_phy *rtlphy = &rtlpriv->phy;
145 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
194 struct rtl_phy *rtlphy = &rtlpriv->phy;
195 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
334 struct rtl_phy *rtlphy = &rtlpriv->phy;
345 rtlphy->pwrgroup_cnt = 0;
359 rtlphy->cck_high_power =
507 struct rtl_phy *rtlphy = &rtlpriv->phy;
508 int count = rtlphy->pwrgroup_cnt;
511 rtlphy->mcs_txpwrlevel_origoffset[count][0] = data;
515 rtlphy->mcs_txpwrlevel_origoffset[count][0]);
518 rtlphy->mcs_txpwrlevel_origoffset[count][1] = data;
522 rtlphy->mcs_txpwrlevel_origoffset[count][1]);
525 rtlphy->mcs_txpwrlevel_origoffset[count][6] = data;
529 rtlphy->mcs_txpwrlevel_origoffset[count][6]);
532 rtlphy->mcs_txpwrlevel_origoffset[count][7] = data;
536 rtlphy->mcs_txpwrlevel_origoffset[count][7]);
539 rtlphy->mcs_txpwrlevel_origoffset[count][2] = data;
543 rtlphy->mcs_txpwrlevel_origoffset[count][2]);
546 rtlphy->mcs_txpwrlevel_origoffset[count][3] = data;
550 rtlphy->mcs_txpwrlevel_origoffset[count][3]);
553 rtlphy->mcs_txpwrlevel_origoffset[count][4] = data;
557 rtlphy->mcs_txpwrlevel_origoffset[count][4]);
560 rtlphy->mcs_txpwrlevel_origoffset[count][5] = data;
561 if (get_rf_type(rtlphy) == RF_1T1R) {
563 rtlphy->pwrgroup_cnt = count;
568 rtlphy->mcs_txpwrlevel_origoffset[count][5]);
571 rtlphy->mcs_txpwrlevel_origoffset[count][8] = data;
575 rtlphy->mcs_txpwrlevel_origoffset[count][8]);
578 rtlphy->mcs_txpwrlevel_origoffset[count][9] = data;
582 rtlphy->mcs_txpwrlevel_origoffset[count][9]);
585 rtlphy->mcs_txpwrlevel_origoffset[count][14] = data;
589 rtlphy->mcs_txpwrlevel_origoffset[count][14]);
592 rtlphy->mcs_txpwrlevel_origoffset[count][15] = data;
596 rtlphy->mcs_txpwrlevel_origoffset[count][15]);
599 rtlphy->mcs_txpwrlevel_origoffset[count][10] = data;
603 rtlphy->mcs_txpwrlevel_origoffset[count][10]);
606 rtlphy->mcs_txpwrlevel_origoffset[count][11] = data;
610 rtlphy->mcs_txpwrlevel_origoffset[count][11]);
613 rtlphy->mcs_txpwrlevel_origoffset[count][12] = data;
617 rtlphy->mcs_txpwrlevel_origoffset[count][12]);
620 rtlphy->mcs_txpwrlevel_origoffset[count][13] = data;
624 rtlphy->mcs_txpwrlevel_origoffset[count][13]);
625 if (get_rf_type(rtlphy) != RF_1T1R) {
627 rtlphy->pwrgroup_cnt = count;
778 struct rtl_phy *rtlphy = &rtlpriv->phy;
780 rtlphy->default_initialgain[0] =
782 rtlphy->default_initialgain[1] =
784 rtlphy->default_initialgain[2] =
786 rtlphy->default_initialgain[3] =
791 rtlphy->default_initialgain[0],
792 rtlphy->default_initialgain[1],
793 rtlphy->default_initialgain[2],
794 rtlphy->default_initialgain[3]);
796 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
798 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
803 ROFDM0_RXDETECTOR3, rtlphy->framesync);
809 struct rtl_phy *rtlphy = &rtlpriv->phy;
811 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
812 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
813 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
814 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
816 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
817 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
818 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
819 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
821 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
822 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
824 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
825 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
827 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
829 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
832 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
833 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
834 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
835 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
837 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
838 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
839 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
840 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
842 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
843 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
845 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
846 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
848 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl =
850 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl =
852 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl =
854 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl =
857 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
858 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
859 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
860 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
862 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
863 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
864 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
865 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
867 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
868 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
869 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
870 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
872 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
873 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
874 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
875 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
877 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
878 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
879 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
880 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
882 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
883 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
885 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
886 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
888 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
889 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
895 struct rtl_phy *rtlphy = &rtlpriv->phy;
899 txpwr_level = rtlphy->cur_cck_txpwridx;
902 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
909 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
981 struct rtl_phy *rtlphy = &rtlpriv->phy;
983 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
984 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
985 rtlphy->cur_bw20_txpwridx = bw20powerlevel[0];
986 rtlphy->cur_bw40_txpwridx = bw40powerlevel[0];
1067 struct rtl_phy *rtlphy = &rtlpriv->phy;
1074 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1078 rtlphy->set_bwmode_inprogress = false;
1085 switch (rtlphy->current_chan_bw) {
1099 rtlphy->current_chan_bw);
1103 switch (rtlphy->current_chan_bw) {
1124 rtlphy->current_chan_bw);
1127 rtl88e_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1128 rtlphy->set_bwmode_inprogress = false;
1136 struct rtl_phy *rtlphy = &rtlpriv->phy;
1138 u8 tmp_bw = rtlphy->current_chan_bw;
1140 if (rtlphy->set_bwmode_inprogress)
1142 rtlphy->set_bwmode_inprogress = true;
1148 rtlphy->set_bwmode_inprogress = false;
1149 rtlphy->current_chan_bw = tmp_bw;
1157 struct rtl_phy *rtlphy = &rtlpriv->phy;
1161 "switch to channel%d\n", rtlphy->current_channel);
1165 if (!rtlphy->sw_chnl_inprogress)
1168 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
1169 &rtlphy->sw_chnl_step, &delay)) {
1175 rtlphy->sw_chnl_inprogress = false;
1185 struct rtl_phy *rtlphy = &rtlpriv->phy;
1188 if (rtlphy->sw_chnl_inprogress)
1190 if (rtlphy->set_bwmode_inprogress)
1192 WARN_ONCE((rtlphy->current_channel > 14),
1194 rtlphy->sw_chnl_inprogress = true;
1195 rtlphy->sw_chnl_stage = 0;
1196 rtlphy->sw_chnl_step = 0;
1201 rtlphy->current_channel);
1202 rtlphy->sw_chnl_inprogress = false;
1206 rtlphy->sw_chnl_inprogress = false;
1216 struct rtl_phy *rtlphy = &rtlpriv->phy;
1225 u8 num_total_rfpath = rtlphy->num_total_rfpath;
1295 rtlphy->rfreg_chnlval[rfpath] =
1296 ((rtlphy->rfreg_chnlval[rfpath] &
1302 rtlphy->rfreg_chnlval[rfpath]);
1677 struct rtl_phy *rtlphy = &rtlpriv->phy;
1698 rtlphy->adda_backup, 16);
1700 rtlphy->iqk_mac_backup);
1702 rtlphy->iqk_bb_backup,
1707 rtlphy->rfpi_enable =
1711 if (!rtlphy->rfpi_enable)
1729 rtlphy->iqk_mac_backup);
1803 if (!rtlphy->rfpi_enable)
1806 rtlphy->adda_backup, 16);
1808 rtlphy->iqk_mac_backup);
1810 rtlphy->iqk_bb_backup,
1921 struct rtl_phy *rtlphy = &rtlpriv->phy;
1943 rtlphy->iqk_bb_backup, 9);
1959 if (get_rf_type(rtlphy) == RF_2T2R)
2006 rtlphy->reg_eb4 = reg_eb4;
2007 rtlphy->reg_ebc = reg_ebc;
2008 rtlphy->reg_e94 = reg_e94;
2009 rtlphy->reg_e9c = reg_e9c;
2012 rtlphy->reg_e94 = 0x100;
2013 rtlphy->reg_eb4 = 0x100;
2014 rtlphy->reg_e9c = 0x0;
2015 rtlphy->reg_ebc = 0x0;
2023 rtlphy->iqk_matrix[0].value[0][i] =
2025 rtlphy->iqk_matrix[0].iqk_done = true;
2029 rtlphy->iqk_bb_backup, 9);
2035 struct rtl_phy *rtlphy = &rtlpriv->phy;
2044 rtlphy->lck_inprogress = true;
2051 rtlphy->lck_inprogress = false;
2062 struct rtl_phy *rtlphy = &rtlpriv->phy;
2067 iotype, rtlphy->set_io_inprogress);
2086 if (postprocessing && !rtlphy->set_io_inprogress) {
2087 rtlphy->set_io_inprogress = true;
2088 rtlphy->current_io_type = iotype;
2100 struct rtl_phy *rtlphy = &rtlpriv->phy;
2105 rtlphy->current_io_type, rtlphy->set_io_inprogress);
2106 switch (rtlphy->current_io_type) {
2108 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
2110 rtl88e_phy_set_txpower_level(hw, rtlphy->current_channel);
2114 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
2121 rtlphy->current_io_type);
2124 rtlphy->set_io_inprogress = false;
2126 "(%#x)\n", rtlphy->current_io_type);