realtek/rtl8xxxu/rtl8xxxu_8723b.c

377 	u8 val8;
380 	val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
381 	val8 &= ~BIT(1);
382 	rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
384 	val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
385 	val8 &= ~BIT(0);
386 	rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
392 	val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
393 	val8 &= ~BIT(1);
394 	rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
396 	val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
397 	val8 |= BIT(0);
398 	rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
516 	u8 val8;
526 	val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
527 	rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
1244 	u8 val8;
1263 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1264 	val8 |= BIT(1);
1265 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1268 		val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1269 		if ((val8 & BIT(1)) == 0)
1282 	val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
1283 	val8 &= ~AFE_MISC_WL_XTAL_CTRL;
1284 	rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
1287 	val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
1288 	val8 |= SYS_ISO_ANALOG_IPS;
1289 	rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
1292 	val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
1293 	val8 &= ~LDOA15_ENABLE;
1294 	rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
1302 	u8 val8;
1307 	val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
1308 	val8 |= LDOA15_ENABLE;
1309 	rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
1312 	val8 = rtl8xxxu_read8(priv, 0x0067);
1313 	val8 &= ~BIT(4);
1314 	rtl8xxxu_write8(priv, 0x0067, val8);
1319 	val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
1320 	val8 &= ~SYS_ISO_ANALOG_IPS;
1321 	rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
1379 	val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
1380 	val8 |= AFE_MISC_WL_XTAL_CTRL;
1381 	rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
1384 	val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1);
1385 	val8 |= BIT(1);
1386 	rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8);
1389 	val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1);
1390 	val8 |= BIT(1);
1391 	rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8);
1394 	val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2);
1395 	val8 &= ~BIT(1);
1396 	rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8);
1399 	val8 = rtl8xxxu_read8(priv, REG_HSIMR);
1400 	val8 |= BIT(0);
1401 	rtl8xxxu_write8(priv, REG_HSIMR, val8);
1404 	val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2);
1405 	val8 |= BIT(1);
1406 	rtl8xxxu_write8(priv, REG_HSIMR + 2, val8);
1408 	val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL);
1409 	val8 |= MULTI_WIFI_HW_ROF_EN;
1410 	rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8);
1413 	val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1);
1414 	val8 |= BIT(6);
1415 	rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8);
1423 	u8 val8;
1470 	val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
1471 	val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA;
1472 	rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
1479 	u8 val8;
1487 	val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
1488 	val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
1489 	rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
1509 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1510 	val8 |= BIT(3); /* APS_FSMCO_HW_SUSPEND */
1511 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1514 	val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
1515 	val8 |= BIT(0);
1516 	rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
1523 	u8 val8;
1541 	val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
1542 	val8 |= BIT(5);
1543 	rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
1565 	val8 = rtl8xxxu_read8(priv, 0x0067);
1566 	val8 |= BIT(5);
1567 	rtl8xxxu_write8(priv, 0x0067, val8);
1592 	val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
1593 	val8 &= ~BIT(0);
1594 	rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);