realtek/rtl8xxxu/rtl8xxxu_8192e.c

670 	u8 val8;
678 	val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
679 	rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
685 	val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
686 	rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
1348 	u8 val8;
1354 	val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
1355 	val8 &= 0xfb;
1356 	rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
1366 	val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
1367 	val8 &= 0xbf;
1368 	rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
1380 	u8 val8;
1383 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1384 	val8 &= ~(BIT(3) | BIT(4));
1385 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1390 	u8 val8;
1395 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1396 	val8 &= ~BIT(7);
1397 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1400 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1401 	val8 &= ~BIT(2);
1402 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1405 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1406 	val8 &= ~(BIT(3) | BIT(4));
1407 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1426 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
1427 	val8 |= BIT(0);
1428 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
1456 	u8 val8;
1483 	val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
1484 	val8 &= ~SYS_FUNC_BBRSTB;
1485 	rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
1490 	val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
1491 	val8 &= ~SYS_FUNC_BB_GLB_RSTN;
1492 	rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
1504 	val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
1505 	val8 |= DUAL_TSF_TX_OK;
1506 	rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
1514 	u8 val8;
1518 	val8 = rtl8xxxu_read8(priv, REG_RF_CTRL);
1519 	val8 &= ~RF_ENABLE;
1520 	rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
1523 	val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
1524 	val8 &= ~LEDCFG2_DPDT_SELECT;
1525 	rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
1528 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1529 	val8 |= BIT(1);
1530 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1533 		val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1534 		if ((val8 & BIT(1)) == 0)
1552 	u8 val8;
1555 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1556 	val8 &= ~(BIT(3) | BIT(4));
1557 	val8 |= BIT(3);
1558 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1613 	u8 val8;
1618 	val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
1619 	val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
1620 	rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
1648 	u8 val8;
1654 	val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
1655 	val8 |= BIT(5);
1656 	rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
1681 	val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
1682 	val8 &= ~BIT(0);
1683 	rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);