realtek/rtl8xxxu/core.c

5132 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc)
5134 	__le16 *ptr = (__le16 *)tx_desc;
5142 	tx_desc->csum = cpu_to_le16(0);
5147 	tx_desc->csum |= cpu_to_le16(csum);
5281 			struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
5294 			 __func__, rate, le16_to_cpu(tx_desc->pkt_size));
5298 	tx_desc->txdw5 = cpu_to_le32(rate);
5301 		tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
5303 	tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
5306 		tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE);
5308 		tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK);
5311 		tx_desc->txdw5 = cpu_to_le32(rate);
5312 		tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
5313 		tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
5314 		tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
5318 		tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
5321 		tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
5324 		tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
5329 	tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT);
5331 		tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
5332 		tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5334 		tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE);
5335 		tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5420 			struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
5436 		tx_desc->txdw5 = cpu_to_le32(rate);
5437 		tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
5438 		tx_desc->txdw4 |= le32_encode_bits(ra->pt_stage, TXDESC32_PT_STAGE_MASK);
5440 		tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
5445 			 __func__, rate, le16_to_cpu(tx_desc->pkt_size));
5447 	tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
5450 		tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
5452 		tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
5455 		tx_desc->txdw5 = cpu_to_le32(rate);
5456 		tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
5457 		tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
5458 		tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
5462 		tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
5465 			tx_desc->txdw4 |= cpu_to_le32(TXDESC_DATA_BW);
5468 				tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_UPPER);
5470 				tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_LOWER);
5475 		tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
5478 		tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
5483 	tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT);
5485 		tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
5486 		tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5488 		tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE);
5489 		tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5492 	tx_desc->txdw2 |= cpu_to_le32(TXDESC_ANTENNA_SELECT_A |
5494 	tx_desc->txdw7 |= cpu_to_le16(TXDESC_ANTENNA_SELECT_C >> 16);
5504 	struct rtl8xxxu_txdesc32 *tx_desc;
5546 	tx_desc = skb_push(skb, tx_desc_size);
5548 	memset(tx_desc, 0, tx_desc_size);
5549 	tx_desc->pkt_size = cpu_to_le16(pktlen);
5550 	tx_desc->pkt_offset = tx_desc_size;
5554 		tx_desc->txdw0 =
5558 		tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
5563 	tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
5571 			tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
5574 			tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
5580 			tx_desc->txdw1 |= cpu_to_le32(TXDESC_EN_DESC_ID);
5595 			tx_desc->txdw2 |= cpu_to_le32(val32);
5626 	priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble,
5629 	rtl8xxxu_calc_tx_desc_csum(tx_desc);
5633 		tx_desc->csum = ~tx_desc->csum;