realtek/rtl8xxxu/core.c

660 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
790 	val32 = rtl8xxxu_read32(priv, addr);
799 	val32 = rtl8xxxu_read32(priv, addr);
811 	orig = rtl8xxxu_read32(priv, addr);
874 	hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
876 		val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
895 	val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
897 		retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
899 		retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
928 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
943 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1061 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1070 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1080 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1104 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1111 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1116 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1218 	rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1229 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1233 		val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1237 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1260 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1264 		val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1272 		val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1278 		val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1286 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1290 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1356 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1360 		val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1364 		val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1381 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1385 		val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1393 		val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1399 		val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1407 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1516 	val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1521 	val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1526 	val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1531 	val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1764 	val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1766 		val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1775 	val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1796 		val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
1938 		val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
1949 	val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
1962 		val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
2028 	val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
2253 	val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2302 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2307 		val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2312 		val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2319 		val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2325 		val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2330 		val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2335 		val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2340 		val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2345 		val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2350 		val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2444 	val32 = rtl8xxxu_read32(priv, reg_int_oe);
2449 	val32 = rtl8xxxu_read32(priv, reg_int_oe);
2457 	val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2462 	val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2489 		value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2544 	val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2549 		val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2654 			val32 = rtl8xxxu_read32(priv, REG_TRXDMA_CTRL);
2706 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2714 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2719 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2730 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
2735 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2740 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2753 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2760 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2767 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
2783 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2791 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2796 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2807 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
2812 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2817 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2830 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2837 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2847 		val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_RSSI_TABLE);
3003 	backup[i] = rtl8xxxu_read32(priv, reg[i]);
3023 		backup[i] = rtl8xxxu_read32(priv, regs[i]);
3102 	reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3103 	reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3104 	reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3105 	reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3138 	reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3139 	reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3140 	reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3141 	reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3142 	reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3207 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3218 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3227 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3233 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3236 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3262 			val32 = rtl8xxxu_read32(priv,
3265 			val32 = rtl8xxxu_read32(priv,
3268 			val32 = rtl8xxxu_read32(priv,
3271 			val32 = rtl8xxxu_read32(priv,
3280 			val32 = rtl8xxxu_read32(priv,
3283 			val32 = rtl8xxxu_read32(priv,
3306 				val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3308 				val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3310 				val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3312 				val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3317 				val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3319 				val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3395 	rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3484 	lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3678 		val32 = rtl8xxxu_read32(priv, 0x5f8);
3775 	val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3783 		val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3839 	val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
3854 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3913 	val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
4256 	val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4327 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4417 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4426 	val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4435 		val32 = rtl8xxxu_read32(priv, REG_AFE_MISC);
4445 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
4449 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_HSSI_PARM2);
4459 		val32 = rtl8xxxu_read32(priv, REG_AGC_RPT);
4477 		val32 = rtl8xxxu_read32(priv, REG_WL_RF_PSS_8710B);
4482 	val32 = rtl8xxxu_read32(priv, 0xa9c);
4487 		val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING);
4818 	val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4899 		val32 = rtl8xxxu_read32(priv, reg_edca_param[i]);
5029 		val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6099 		val32 = rtl8xxxu_read32(priv, 0x770);
6668 	val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
7296 	val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING);