Lines Matching refs:rtl8xxxu_read32
321 sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG);
368 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
373 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
432 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH);
437 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH);
442 reg948 = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
447 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
455 initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
458 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
477 do_notch = rtl8xxxu_read32(priv, REG_FPGA0_PSD_REPORT) >= threshold;
486 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
499 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING);
509 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING);
533 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
538 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
544 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
549 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
555 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
560 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
566 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_AFE);
571 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR);
575 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR);
596 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
602 val32 = rtl8xxxu_read32(priv, REG_DATA_SUBCHANNEL);
611 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
651 val32 = rtl8xxxu_read32(priv, REG_DWBCN0_CTRL_8188F);
661 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
684 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
689 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
695 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
782 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
826 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
845 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
869 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
879 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
880 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
881 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
899 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
920 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
950 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
957 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
958 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
959 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
975 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
995 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1024 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1034 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
1035 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
1080 rx_initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
1094 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
1099 path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
1108 val32 = rtl8xxxu_read32(priv, REG_TX_PTCL_CTRL);
1113 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1123 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1127 val32 = rtl8xxxu_read32(priv,
1131 val32 = rtl8xxxu_read32(priv,
1141 val32 = rtl8xxxu_read32(priv,
1145 val32 = rtl8xxxu_read32(priv,
1156 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1189 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
1193 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
1216 path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
1331 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1359 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1401 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1459 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD);
1598 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1610 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1627 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
1643 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);