Lines Matching refs:rfcsr
1571 .rfcsr = {
2449 u8 rfcsr, prev_rfcsr;
2454 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
2455 prev_rfcsr = rfcsr;
2457 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
2458 if (rfcsr == prev_rfcsr)
2474 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
2475 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2552 u8 rfcsr, calib_tx, calib_rx;
2556 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2557 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2558 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2560 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2561 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2562 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2564 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2565 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2566 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2568 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2569 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2570 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2572 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2573 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2574 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2576 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2578 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2579 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2581 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2583 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2585 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2586 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2587 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2602 rfcsr = rt2800_rfcsr_read(rt2x00dev, 24);
2603 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2604 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2606 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
2607 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2608 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2610 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2611 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2612 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2614 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2615 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2616 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2620 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2621 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2630 u8 rfcsr;
2644 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2645 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2647 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2649 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2650 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2652 rfcsr = rt2800_rfcsr_read(rt2x00dev, 5);
2654 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2656 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2657 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2659 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2661 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2662 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2665 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2666 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2670 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2672 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2674 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2675 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2678 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2679 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2683 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2685 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2686 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2687 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2688 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2689 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2690 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2691 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2694 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2695 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2697 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2698 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2702 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2705 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2711 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2714 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2718 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2720 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2721 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2722 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2738 rfcsr = 0x4c;
2739 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2741 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2750 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2751 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2752 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2753 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2754 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2755 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2760 rfcsr = 0x7a;
2761 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2763 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2791 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2792 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2793 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2804 u8 rfcsr;
2834 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2835 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2836 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2838 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2839 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2841 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2843 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2844 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2846 rfcsr = rt2800_rfcsr_read(rt2x00dev, 53);
2848 rfcsr = 0;
2849 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2853 rfcsr = 0x40;
2855 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2859 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2861 rfcsr = rt2800_rfcsr_read(rt2x00dev, 55);
2863 rfcsr = 0;
2864 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2868 rfcsr = 0x40;
2870 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2874 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2876 rfcsr = rt2800_rfcsr_read(rt2x00dev, 54);
2878 rfcsr = 0;
2879 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2883 rfcsr = 0x40;
2885 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2889 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2891 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2892 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2893 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2894 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2895 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2896 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2897 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2898 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2899 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2903 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2906 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2909 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2915 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2918 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2921 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2924 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2943 rfcsr = rt2800_rfcsr_read(rt2x00dev, 32);
2944 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2947 rfcsr = 0xa0;
2949 rfcsr = 0x80;
2950 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2952 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2953 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2954 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2955 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2958 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
2960 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2962 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2963 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2965 rfcsr = rt2800_rfcsr_read(rt2x00dev, 34);
2967 rfcsr = 0x3c;
2969 rfcsr = 0x20;
2970 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2972 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2974 rfcsr = 0x1a;
2976 rfcsr = 0x12;
2977 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2979 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2981 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2983 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2985 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2987 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2988 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2990 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2991 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2992 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3004 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
3005 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
3006 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
3008 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
3010 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
3011 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
3013 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
3014 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
3016 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
3018 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3020 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
3022 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
3025 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
3027 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3029 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3030 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
3031 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3033 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
3035 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
3037 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
3038 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
3049 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3051 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3053 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
3054 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
3055 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
3056 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
3057 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
3058 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3060 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3063 rfcsr = 0x23;
3065 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
3066 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3070 rfcsr = 0x36;
3072 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
3077 rfcsr = 0x32;
3079 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
3080 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3084 rfcsr = 0x30;
3086 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
3087 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3098 u8 rfcsr;
3128 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3129 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3130 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3131 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
3132 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
3133 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3134 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3135 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3136 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3140 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
3143 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3146 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3152 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
3155 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3158 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3161 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3165 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
3167 rfcsr &= ~(0x06);
3169 rfcsr |= 0x06;
3170 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3188 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
3190 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
3192 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
3193 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
3196 rfcsr = 0x23;
3198 rfcsr = 0x36;
3200 rfcsr = 0x32;
3202 rfcsr = 0x30;
3205 rfcsr |= 0x40;
3207 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3215 rfcsr = 0xbb;
3217 rfcsr = 0xeb;
3219 rfcsr = 0xb3;
3221 rfcsr = 0x9b;
3222 rt2800_rfcsr_write(rt2x00dev, 45, rfcsr);
3225 rfcsr = 0x8e;
3227 rfcsr = 0x8a;
3230 rfcsr |= 0x20;
3232 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3236 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
3242 rfcsr = rt2800_rfcsr_read(rt2x00dev, 52);
3277 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
3284 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3285 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3286 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3306 u8 rfcsr;
3310 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3311 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
3312 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3314 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3316 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
3318 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3319 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3343 u8 rfcsr;
3364 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3365 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3366 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3369 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3371 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
3374 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3376 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
3378 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3379 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3381 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3391 u8 rfcsr;
3396 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3397 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
3398 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3400 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3402 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
3404 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3405 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3408 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3410 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
3412 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
3414 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3417 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3419 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3420 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3422 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3423 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3424 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3425 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3426 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3489 u8 rfcsr, ep_reg;
3505 rfcsr = rt2800_rfcsr_read(rt2x00dev, 9);
3506 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
3507 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
3508 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
3509 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
3511 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3512 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
3513 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
3514 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3550 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
3551 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
3552 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
3679 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3681 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
3683 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3685 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
3686 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3688 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3690 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
3692 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
3694 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
3695 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3697 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3698 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3699 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3701 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
3703 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
3705 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3707 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
3709 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
3711 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3713 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3730 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3731 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3732 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3766 u8 rfcsr;
3772 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
3773 rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620,
3775 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
3781 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
3782 rfcsr = (rf->rf1 & 0x00ff);
3783 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3785 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3786 rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0);
3787 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3792 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3793 rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0);
3794 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3799 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
3800 rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0);
3801 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3808 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
3809 rfcsr = rf->rf2;
3810 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3812 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
3813 rfcsr = rf->rf3;
3814 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
3816 rfcsr = rt2800_rfcsr_read(rt2x00dev, 19);
3817 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
3818 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
3821 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3822 rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
3823 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3825 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3826 rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
3827 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3829 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3830 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
3832 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3834 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
3835 rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620,
3837 rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620,
3839 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3841 rfcsr = rt2800_rfcsr_read(rt2x00dev, 42);
3842 rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620,
3844 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
3869 rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
3870 rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
3872 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
3882 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
3883 rfcsr &= (~0x3F);
3884 rfcsr |= rx_agc_fc;
3885 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
3886 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
3887 rfcsr &= (~0x3F);
3888 rfcsr |= rx_agc_fc;
3889 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
3890 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6);
3891 rfcsr &= (~0x3F);
3892 rfcsr |= rx_agc_fc;
3893 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
3894 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7);
3895 rfcsr &= (~0x3F);
3896 rfcsr |= rx_agc_fc;
3897 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
3899 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
3900 rfcsr &= (~0x3F);
3901 rfcsr |= tx_agc_fc;
3902 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
3903 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
3904 rfcsr &= (~0x3F);
3905 rfcsr |= tx_agc_fc;
3906 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
3907 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58);
3908 rfcsr &= (~0x3F);
3909 rfcsr |= tx_agc_fc;
3910 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
3911 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59);
3912 rfcsr &= (~0x3F);
3913 rfcsr |= tx_agc_fc;
3914 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
4167 u8 bbp, rfcsr;
4237 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
4239 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M,
4241 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M,
4244 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M,
4246 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M,
4249 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4251 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
4252 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4253 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
5543 u8 rfcsr;
5565 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
5566 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
5567 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
5581 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
5582 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
5583 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
5589 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4);
5590 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1);
5591 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
7324 u8 rfcsr;
7336 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
7337 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
7338 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
7340 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7341 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
7342 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7387 u8 rfcsr;
7389 rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg);
7390 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
7391 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7393 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
7394 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7402 u8 rfcsr, bbp;
7431 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7432 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
7433 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7446 u8 min_gain, rfcsr, bbp;
7449 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
7451 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
7457 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
7462 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
7466 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
7480 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27);
7482 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
7484 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
7485 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
7486 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
7487 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
7488 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
7492 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7493 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
7494 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7495 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7496 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
7497 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
7498 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7500 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15);
7501 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
7502 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
7504 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
7505 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
7506 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
7508 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
7509 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
7510 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
7517 u8 rfcsr;
7520 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
7521 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
7522 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7524 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
7527 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
7528 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
7530 rfcsr = rt2800_rfcsr_read(rt2x00dev, 38);
7531 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
7532 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
7534 rfcsr = rt2800_rfcsr_read(rt2x00dev, 39);
7535 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
7536 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
7538 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7539 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
7540 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
7541 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7543 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
7544 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
7545 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
7619 u8 rfcsr;
7655 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7656 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7657 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7689 u8 rfcsr;
7740 rfcsr = rt2800_rfcsr_read(rt2x00dev, 29);
7741 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
7742 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
7754 u8 rfcsr;
7791 rfcsr = 0x01;
7793 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1);
7795 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1);
7796 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
7803 rfcsr = 0x52;
7805 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1);
7806 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1);
7808 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr);
7809 rfcsr = 0x52;
7811 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1);
7812 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1);
7814 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
7822 rfcsr = 0x2d;
7824 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1);
7826 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1);
7827 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7901 u8 rfcsr;
7938 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7939 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7940 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
8008 u8 rfcsr;
8052 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
8053 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
8054 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8058 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
8059 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
8060 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
8159 u8 rfcsr;
8266 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
8267 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0);
8268 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
8269 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8271 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
8272 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8274 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
8275 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
8276 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
8278 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
8279 rfcsr |= 0xc0;
8280 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
8282 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
8283 rfcsr |= 0x20;
8284 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
8286 rfcsr = rt2800_rfcsr_read(rt2x00dev, 46);
8287 rfcsr |= 0x20;
8288 rt2800_rfcsr_write(rt2x00dev, 46, rfcsr);
8290 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
8291 rfcsr &= ~0xee;
8292 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);