Lines Matching defs:rt2x00dev
45 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
50 mutex_lock(&rt2x00dev->csr_mutex);
56 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
63 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
66 mutex_unlock(&rt2x00dev->csr_mutex);
69 static u8 rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
75 mutex_lock(&rt2x00dev->csr_mutex);
85 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
91 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
93 WAIT_FOR_BBP(rt2x00dev, ®);
98 mutex_unlock(&rt2x00dev->csr_mutex);
103 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
108 mutex_lock(&rt2x00dev->csr_mutex);
114 if (WAIT_FOR_RF(rt2x00dev, ®)) {
121 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
122 rt2x00_rf_write(rt2x00dev, word, value);
125 mutex_unlock(&rt2x00dev->csr_mutex);
130 struct rt2x00_dev *rt2x00dev = eeprom->data;
133 reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
145 struct rt2x00_dev *rt2x00dev = eeprom->data;
155 rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
193 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
197 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
210 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
217 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
228 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
231 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
236 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
240 led->rt2x00dev = rt2x00dev;
251 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
261 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
269 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
271 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) &&
272 !rt2x00dev->intf_ap_count);
274 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
277 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
290 reg = rt2x00mmio_register_read(rt2x00dev, BCNCSR1);
292 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
297 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
299 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
303 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
307 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
312 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
325 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR1);
330 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
332 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR2);
337 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
339 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR3);
344 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
346 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR4);
351 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
353 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR5);
358 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
362 rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
365 reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
367 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
369 reg = rt2x00mmio_register_read(rt2x00dev, CSR18);
372 rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
374 reg = rt2x00mmio_register_read(rt2x00dev, CSR19);
377 rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
381 reg = rt2x00mmio_register_read(rt2x00dev, CSR12);
386 rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
390 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
403 r4 = rt2400pci_bbp_read(rt2x00dev, 4);
404 r1 = rt2400pci_bbp_read(rt2x00dev, 1);
438 rt2400pci_bbp_write(rt2x00dev, 4, r4);
439 rt2400pci_bbp_write(rt2x00dev, 1, r1);
442 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
451 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
452 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
453 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
458 if (rt2x00_rf(rt2x00dev, RF2420))
466 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
467 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
468 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
472 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
473 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
474 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
484 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
485 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
490 rf->rf1 = rt2x00mmio_register_read(rt2x00dev, CNT0);
493 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
495 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
498 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
503 reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
508 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
511 static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
520 reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
522 (rt2x00dev->beacon_int - 20) * 16);
528 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
531 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
533 reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
535 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
538 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
541 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
546 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
548 rt2400pci_config_txpower(rt2x00dev,
551 rt2400pci_config_retry_limit(rt2x00dev, libconf);
553 rt2400pci_config_ps(rt2x00dev, libconf);
556 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
561 reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
564 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
570 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
579 reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
585 bbp = rt2400pci_bbp_read(rt2x00dev, 39);
589 static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
593 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
599 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
602 rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
605 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
619 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
621 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
629 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
634 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
636 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
639 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
643 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
652 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
657 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
659 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
662 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
664 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
667 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
669 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
678 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
685 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
687 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
690 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
692 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
695 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
699 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
704 tasklet_kill(&rt2x00dev->tbtt_tasklet);
757 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
765 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR2);
766 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
767 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
768 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
769 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
770 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
772 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
773 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR3);
776 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
778 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
779 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR5);
782 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
784 entry_priv = rt2x00dev->atim->entries[0].priv_data;
785 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR4);
788 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
790 entry_priv = rt2x00dev->bcn->entries[0].priv_data;
791 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR6);
794 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
796 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR1);
797 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
798 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
799 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
801 entry_priv = rt2x00dev->rx->entries[0].priv_data;
802 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR2);
805 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
810 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
814 rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002);
815 rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002);
816 rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00023f20);
817 rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);
819 reg = rt2x00mmio_register_read(rt2x00dev, TIMECSR);
823 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
825 reg = rt2x00mmio_register_read(rt2x00dev, CSR9);
827 (rt2x00dev->rx->data_size / 128));
828 rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
830 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
839 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
841 rt2x00mmio_register_write(rt2x00dev, CNT3, 0x3f080000);
843 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR0);
848 rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg);
850 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR3);
857 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
859 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
861 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
864 rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00217223);
865 rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);
867 reg = rt2x00mmio_register_read(rt2x00dev, MACCSR2);
869 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
871 reg = rt2x00mmio_register_read(rt2x00dev, RALINKCSR);
876 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
878 reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
882 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
884 reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
887 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
894 reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
895 reg = rt2x00mmio_register_read(rt2x00dev, CNT4);
900 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
906 value = rt2400pci_bbp_read(rt2x00dev, 0);
912 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
916 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
923 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
926 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
927 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
928 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
929 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
930 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
931 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
932 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
933 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
934 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
935 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
936 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
937 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
938 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
939 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
942 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i);
947 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
957 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
969 reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
970 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
977 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
979 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
985 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
987 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
994 tasklet_kill(&rt2x00dev->txstatus_tasklet);
995 tasklet_kill(&rt2x00dev->rxdone_tasklet);
996 tasklet_kill(&rt2x00dev->tbtt_tasklet);
1000 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1005 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
1006 rt2400pci_init_registers(rt2x00dev) ||
1007 rt2400pci_init_bbp(rt2x00dev)))
1013 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1018 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0);
1021 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1032 reg = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);
1037 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1045 reg2 = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);
1050 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1057 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1064 retval = rt2400pci_enable_radio(rt2x00dev);
1067 rt2400pci_disable_radio(rt2x00dev);
1071 rt2400pci_toggle_irq(rt2x00dev, state);
1077 retval = rt2400pci_set_state(rt2x00dev, state);
1085 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1168 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1175 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
1177 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1180 rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n");
1195 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1201 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1210 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1239 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw, NULL);
1254 entry->queue->rt2x00dev->rssi_offset;
1265 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1268 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1304 static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1313 spin_lock_irq(&rt2x00dev->irqmask_lock);
1315 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1317 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1319 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1324 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
1331 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1332 rt2400pci_txdone(rt2x00dev, QID_AC_VO);
1333 rt2400pci_txdone(rt2x00dev, QID_AC_VI);
1338 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1339 spin_lock_irq(&rt2x00dev->irqmask_lock);
1341 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1345 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1347 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1353 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, tbtt_tasklet);
1354 rt2x00lib_beacondone(rt2x00dev);
1355 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1356 rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1361 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
1363 if (rt2x00mmio_rxdone(rt2x00dev))
1364 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1365 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1366 rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1371 struct rt2x00_dev *rt2x00dev = dev_instance;
1378 reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
1379 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1384 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1393 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1396 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1401 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1414 spin_lock(&rt2x00dev->irqmask_lock);
1416 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1418 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1420 spin_unlock(&rt2x00dev->irqmask_lock);
1430 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1437 reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
1439 eeprom.data = rt2x00dev;
1449 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1455 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1456 rt2x00lib_set_mac_address(rt2x00dev, mac);
1458 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
1460 rt2x00_err(rt2x00dev, "Invalid EEPROM data detected\n");
1467 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1476 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
1482 reg = rt2x00mmio_register_read(rt2x00dev, CSR0);
1483 rt2x00_set_chip(rt2x00dev, RT2460, value,
1486 if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
1487 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
1494 rt2x00dev->default_ant.tx =
1496 rt2x00dev->default_ant.rx =
1505 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1506 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1507 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1508 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1516 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1520 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1528 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1534 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1560 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1562 struct hw_mode_spec *spec = &rt2x00dev->spec;
1570 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
1571 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
1572 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
1573 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
1575 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1576 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1577 rt2x00_eeprom_addr(rt2x00dev,
1598 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1607 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1615 retval = rt2400pci_validate_eeprom(rt2x00dev);
1619 retval = rt2400pci_init_eeprom(rt2x00dev);
1627 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
1629 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
1634 retval = rt2400pci_probe_hw_mode(rt2x00dev);
1641 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1642 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1643 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1648 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1661 struct rt2x00_dev *rt2x00dev = hw->priv;
1677 rt2400pci_config_cw(rt2x00dev,
1678 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1686 struct rt2x00_dev *rt2x00dev = hw->priv;
1690 reg = rt2x00mmio_register_read(rt2x00dev, CSR17);
1692 reg = rt2x00mmio_register_read(rt2x00dev, CSR16);
1700 struct rt2x00_dev *rt2x00dev = hw->priv;
1703 reg = rt2x00mmio_register_read(rt2x00dev, CSR15);