qtnfmac/pcie/pearl_pcie.c

100 static inline void qtnf_init_hdp_irqs(struct qtnf_pcie_pearl_state *ps)
104 	spin_lock_irqsave(&ps->irq_lock, flags);
105 	ps->pcie_irq_mask = (PCIE_HDP_INT_RX_BITS | PCIE_HDP_INT_TX_BITS);
106 	spin_unlock_irqrestore(&ps->irq_lock, flags);
109 static inline void qtnf_enable_hdp_irqs(struct qtnf_pcie_pearl_state *ps)
113 	spin_lock_irqsave(&ps->irq_lock, flags);
114 	writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
115 	spin_unlock_irqrestore(&ps->irq_lock, flags);
118 static inline void qtnf_disable_hdp_irqs(struct qtnf_pcie_pearl_state *ps)
122 	spin_lock_irqsave(&ps->irq_lock, flags);
123 	writel(0x0, PCIE_HDP_INT_EN(ps->pcie_reg_base));
124 	spin_unlock_irqrestore(&ps->irq_lock, flags);
127 static inline void qtnf_en_rxdone_irq(struct qtnf_pcie_pearl_state *ps)
131 	spin_lock_irqsave(&ps->irq_lock, flags);
132 	ps->pcie_irq_mask |= PCIE_HDP_INT_RX_BITS;
133 	writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
134 	spin_unlock_irqrestore(&ps->irq_lock, flags);
137 static inline void qtnf_dis_rxdone_irq(struct qtnf_pcie_pearl_state *ps)
141 	spin_lock_irqsave(&ps->irq_lock, flags);
142 	ps->pcie_irq_mask &= ~PCIE_HDP_INT_RX_BITS;
143 	writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
144 	spin_unlock_irqrestore(&ps->irq_lock, flags);
147 static inline void qtnf_en_txdone_irq(struct qtnf_pcie_pearl_state *ps)
151 	spin_lock_irqsave(&ps->irq_lock, flags);
152 	ps->pcie_irq_mask |= PCIE_HDP_INT_TX_BITS;
153 	writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
154 	spin_unlock_irqrestore(&ps->irq_lock, flags);
157 static inline void qtnf_dis_txdone_irq(struct qtnf_pcie_pearl_state *ps)
161 	spin_lock_irqsave(&ps->irq_lock, flags);
162 	ps->pcie_irq_mask &= ~PCIE_HDP_INT_TX_BITS;
163 	writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
164 	spin_unlock_irqrestore(&ps->irq_lock, flags);
167 static void qtnf_deassert_intx(struct qtnf_pcie_pearl_state *ps)
169 	void __iomem *reg = ps->base.sysctl_bar + PEARL_PCIE_CFG0_OFFSET;
177 static void qtnf_pearl_reset_ep(struct qtnf_pcie_pearl_state *ps)
180 	void __iomem *reg = ps->base.sysctl_bar +
185 	pci_restore_state(ps->base.pdev);
190 	const struct qtnf_pcie_pearl_state *ps = arg;
192 	void __iomem *reg = ps->base.sysctl_bar +
232 static int pearl_alloc_bd_table(struct qtnf_pcie_pearl_state *ps)
234 	struct qtnf_pcie_bus_priv *priv = &ps->base;
248 	ps->bd_table_vaddr = vaddr;
249 	ps->bd_table_paddr = paddr;
250 	ps->bd_table_len = len;
252 	ps->tx_bd_vbase = vaddr;
253 	ps->tx_bd_pbase = paddr;
265 	ps->rx_bd_vbase = vaddr;
266 	ps->rx_bd_pbase = paddr;
270 	       PCIE_HDP_TX_HOST_Q_BASE_H(ps->pcie_reg_base));
273 	       PCIE_HDP_TX_HOST_Q_BASE_L(ps->pcie_reg_base));
275 	       PCIE_HDP_TX_HOST_Q_SZ_CTRL(ps->pcie_reg_base));
282 static int pearl_skb2rbd_attach(struct qtnf_pcie_pearl_state *ps, u16 index)
284 	struct qtnf_pcie_bus_priv *priv = &ps->base;
296 	rxbd = &ps->rx_bd_vbase[index];
317 	       PCIE_HDP_HHBM_BUF_PTR_H(ps->pcie_reg_base));
320 	       PCIE_HDP_HHBM_BUF_PTR(ps->pcie_reg_base));
322 	writel(index, PCIE_HDP_TX_HOST_Q_WR_PTR(ps->pcie_reg_base));
326 static int pearl_alloc_rx_buffers(struct qtnf_pcie_pearl_state *ps)
331 	memset(ps->rx_bd_vbase, 0x0,
332 	       ps->base.rx_bd_num * sizeof(struct qtnf_pearl_rx_bd));
334 	for (i = 0; i < ps->base.rx_bd_num; i++) {
335 		ret = pearl_skb2rbd_attach(ps, i);
344 static void qtnf_pearl_free_xfer_buffers(struct qtnf_pcie_pearl_state *ps)
346 	struct qtnf_pcie_bus_priv *priv = &ps->base;
356 			rxbd = &ps->rx_bd_vbase[i];
370 			txbd = &ps->tx_bd_vbase[i];
382 static int pearl_hhbm_init(struct qtnf_pcie_pearl_state *ps)
386 	val = readl(PCIE_HHBM_CONFIG(ps->pcie_reg_base));
388 	writel(val, PCIE_HHBM_CONFIG(ps->pcie_reg_base));
394 	writel(val, PCIE_HHBM_CONFIG(ps->pcie_reg_base));
395 	writel(ps->base.rx_bd_num, PCIE_HHBM_Q_LIMIT_REG(ps->pcie_reg_base));
400 static int qtnf_pcie_pearl_init_xfer(struct qtnf_pcie_pearl_state *ps,
404 	struct qtnf_pcie_bus_priv *priv = &ps->base;
437 	ret = pearl_hhbm_init(ps);
449 	ret = pearl_alloc_bd_table(ps);
455 	ret = pearl_alloc_rx_buffers(ps);
464 static void qtnf_pearl_data_tx_reclaim(struct qtnf_pcie_pearl_state *ps)
466 	struct qtnf_pcie_bus_priv *priv = &ps->base;
477 	tx_done_index = readl(PCIE_HDP_RX0DMA_CNT(ps->pcie_reg_base))
485 			txbd = &ps->tx_bd_vbase[i];
516 static int qtnf_tx_queue_ready(struct qtnf_pcie_pearl_state *ps)
518 	struct qtnf_pcie_bus_priv *priv = &ps->base;
522 		qtnf_pearl_data_tx_reclaim(ps);
537 	struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus);
538 	struct qtnf_pcie_bus_priv *priv = &ps->base;
548 	if (!qtnf_tx_queue_ready(ps)) {
570 	txbd = &ps->tx_bd_vbase[i];
581 	txbd_paddr = ps->tx_bd_pbase + i * sizeof(struct qtnf_pearl_tx_bd);
585 	       PCIE_HDP_HOST_WR_DESC0_H(ps->pcie_reg_base));
588 	       PCIE_HDP_HOST_WR_DESC0(ps->pcie_reg_base));
606 	qtnf_pearl_data_tx_reclaim(ps);
646 	struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus);
647 	struct qtnf_pcie_bus_priv *priv = &ps->base;
651 	status = readl(PCIE_HDP_INT_STATUS(ps->pcie_reg_base));
656 	if (!(status & ps->pcie_irq_mask))
660 		ps->pcie_irq_rx_count++;
663 		ps->pcie_irq_tx_count++;
666 		ps->pcie_irq_uf_count++;
669 		qtnf_dis_rxdone_irq(ps);
674 		qtnf_dis_txdone_irq(ps);
680 	qtnf_non_posted_write(~0U, PCIE_HDP_INT_STATUS(ps->pcie_reg_base));
683 		qtnf_deassert_intx(ps);
688 static int qtnf_rx_data_ready(struct qtnf_pcie_pearl_state *ps)
690 	u16 index = ps->base.rx_bd_r_index;
694 	rxbd = &ps->rx_bd_vbase[index];
706 	struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus);
707 	struct qtnf_pcie_bus_priv *priv = &ps->base;
721 		if (!qtnf_rx_data_ready(ps))
725 		rxbd = &ps->rx_bd_vbase[r_idx];
787 			ret = pearl_skb2rbd_attach(ps, w_idx);
801 		qtnf_en_rxdone_irq(ps);
810 	struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus);
812 	tasklet_hi_schedule(&ps->base.reclaim_tq);
817 	struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus);
819 	qtnf_enable_hdp_irqs(ps);
825 	struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus);
828 	qtnf_disable_hdp_irqs(ps);
854 	struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus);
855 	u32 reg = readl(PCIE_HDP_INT_EN(ps->pcie_reg_base));
858 	seq_printf(s, "pcie_irq_count(%u)\n", ps->base.pcie_irq_count);
859 	seq_printf(s, "pcie_irq_tx_count(%u)\n", ps->pcie_irq_tx_count);
863 	seq_printf(s, "pcie_irq_rx_count(%u)\n", ps->pcie_irq_rx_count);
867 	seq_printf(s, "pcie_irq_uf_count(%u)\n", ps->pcie_irq_uf_count);
878 	struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus);
879 	struct qtnf_pcie_bus_priv *priv = &ps->base;
888 		   readl(PCIE_HDP_RX0DMA_CNT(ps->pcie_reg_base))
897 		   readl(PCIE_HDP_TX0DMA_CNT(ps->pcie_reg_base))
955 qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *ps, const u8 *fw, u32 fw_size)
972 		len = qtnf_ep_fw_send(ps->base.pdev, fw_size, blk, pblk, fw);
978 			qtnf_set_state(&ps->bda->bda_rc_state,
980 			if (qtnf_poll_state(&ps->bda->bda_ep_state,
987 			qtnf_clear_state(&ps->bda->bda_ep_state,
990 			if (qtnf_is_state(&ps->bda->bda_ep_state,
1003 				qtnf_clear_state(&ps->bda->bda_ep_state,
1010 			qtnf_pearl_data_tx_reclaim(ps);
1024 	struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus);
1027 	struct pci_dev *pdev = ps->base.pdev;
1031 	if (ps->base.flashboot) {
1041 	qtnf_set_state(&ps->bda->bda_rc_state, state);
1043 	if (qtnf_poll_state(&ps->bda->bda_ep_state, QTN_EP_FW_LOADRDY,
1047 		if (!ps->base.flashboot)
1053 	qtnf_clear_state(&ps->bda->bda_ep_state, QTN_EP_FW_LOADRDY);
1055 	if (ps->base.flashboot) {
1061 		ret = qtnf_ep_fw_load(ps, fw->data, fw->size);
1069 	if (qtnf_poll_state(&ps->bda->bda_ep_state, QTN_EP_FW_DONE,
1075 	if (qtnf_poll_state(&ps->bda->bda_ep_state,
1096 	struct qtnf_pcie_pearl_state *ps = from_tasklet(ps, t, base.reclaim_tq);
1098 	qtnf_pearl_data_tx_reclaim(ps);
1099 	qtnf_en_txdone_irq(ps);
1115 	struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus);
1116 	struct pci_dev *pdev = ps->base.pdev;
1120 	spin_lock_init(&ps->irq_lock);
1123 	ps->pcie_reg_base = ps->base.dmareg_bar;
1124 	ps->bda = ps->base.epmem_bar;
1125 	writel(ps->base.msi_enabled, &ps->bda->bda_rc_msi_enabled);
1127 	ret = qtnf_pcie_pearl_init_xfer(ps, tx_bd_size, rx_bd_size);
1134 	qtnf_init_hdp_irqs(ps);
1137 	qtnf_disable_hdp_irqs(ps);
1144 		qtnf_pearl_free_xfer_buffers(ps);
1148 	tasklet_setup(&ps->base.reclaim_tq, qtnf_pearl_reclaim_tasklet_fn);
1153 	ipc_int.arg = ps;
1154 	qtnf_pcie_init_shm_ipc(&ps->base, &ps->bda->bda_shm_reg1,
1155 			       &ps->bda->bda_shm_reg2, &ipc_int);
1162 	struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus);
1164 	qtnf_pearl_reset_ep(ps);
1165 	qtnf_pearl_free_xfer_buffers(ps);
1183 	struct qtnf_pcie_pearl_state *ps;
1185 	bus = devm_kzalloc(&pdev->dev, sizeof(*bus) + sizeof(*ps), GFP_KERNEL);
1189 	ps = get_bus_priv(bus);
1190 	ps->base.probe_cb = qtnf_pcie_pearl_probe;
1191 	ps->base.remove_cb = qtnf_pcie_pearl_remove;
1192 	ps->base.dma_mask_get_cb = qtnf_pearl_dma_mask_get;
1194 	ps->base.resume_cb = qtnf_pcie_pearl_resume;
1195 	ps->base.suspend_cb = qtnf_pcie_pearl_suspend;