Lines Matching defs:WILC_SPI_REG_BASE
85 #define WILC_SPI_REG_BASE 0xe800
86 #define WILC_SPI_CTL WILC_SPI_REG_BASE
87 #define WILC_SPI_MASTER_DMA_ADDR (WILC_SPI_REG_BASE + 0x4)
88 #define WILC_SPI_MASTER_DMA_COUNT (WILC_SPI_REG_BASE + 0x8)
89 #define WILC_SPI_SLAVE_DMA_ADDR (WILC_SPI_REG_BASE + 0xc)
90 #define WILC_SPI_SLAVE_DMA_COUNT (WILC_SPI_REG_BASE + 0x10)
91 #define WILC_SPI_TX_MODE (WILC_SPI_REG_BASE + 0x20)
92 #define WILC_SPI_PROTOCOL_CONFIG (WILC_SPI_REG_BASE + 0x24)
93 #define WILC_SPI_INTR_CTL (WILC_SPI_REG_BASE + 0x2c)
94 #define WILC_SPI_INT_STATUS (WILC_SPI_REG_BASE + 0x40)
95 #define WILC_SPI_INT_CLEAR (WILC_SPI_REG_BASE + 0x44)
109 WILC_SPI_REG_BASE)