Lines Matching refs:dev
16 mt7601u_set_wlan_state(struct mt7601u_dev *dev, u32 val, bool enable)
32 mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val);
36 set_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state);
38 clear_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state);
43 val = mt7601u_rr(dev, MT_CMB_CTRL);
56 dev_err(dev->dev, "Error: PLL and XTAL check failed!\n");
59 static void mt7601u_chip_onoff(struct mt7601u_dev *dev, bool enable, bool reset)
63 mutex_lock(&dev->hw_atomic_mutex);
65 val = mt7601u_rr(dev, MT_WLAN_FUN_CTRL);
74 mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val);
82 mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val);
85 mt7601u_set_wlan_state(dev, val, enable);
87 mutex_unlock(&dev->hw_atomic_mutex);
90 static void mt7601u_reset_csr_bbp(struct mt7601u_dev *dev)
92 mt7601u_wr(dev, MT_MAC_SYS_CTRL, (MT_MAC_SYS_CTRL_RESET_CSR |
94 mt7601u_wr(dev, MT_USB_DMA_CFG, 0);
96 mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);
99 static void mt7601u_init_usb_dma(struct mt7601u_dev *dev)
108 if (dev->in_max_packet == 512)
110 mt7601u_wr(dev, MT_USB_DMA_CFG, val);
113 mt7601u_wr(dev, MT_USB_DMA_CFG, val);
115 mt7601u_wr(dev, MT_USB_DMA_CFG, val);
118 static int mt7601u_init_bbp(struct mt7601u_dev *dev)
122 ret = mt7601u_wait_bbp_ready(dev);
126 ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, bbp_common_vals,
131 return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, bbp_chip_vals,
136 mt76_init_beacon_offsets(struct mt7601u_dev *dev)
143 u16 addr = dev->beacon_offsets[i];
149 mt7601u_wr(dev, MT_BCN_OFFSET(i), regs[i]);
152 static int mt7601u_write_mac_initvals(struct mt7601u_dev *dev)
156 ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_WLAN, mac_common_vals,
160 ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_WLAN,
165 mt76_init_beacon_offsets(dev);
167 mt7601u_wr(dev, MT_AUX_CLK_CFG, 0);
172 static int mt7601u_init_wcid_mem(struct mt7601u_dev *dev)
186 ret = mt7601u_burst_write_regs(dev, MT_WCID_ADDR_BASE,
193 static int mt7601u_init_key_mem(struct mt7601u_dev *dev)
197 return mt7601u_burst_write_regs(dev, MT_SKEY_MODE_BASE_0,
201 static int mt7601u_init_wcid_attr_mem(struct mt7601u_dev *dev)
213 ret = mt7601u_burst_write_regs(dev, MT_WCID_ATTR_BASE,
220 static void mt7601u_reset_counters(struct mt7601u_dev *dev)
222 mt7601u_rr(dev, MT_RX_STA_CNT0);
223 mt7601u_rr(dev, MT_RX_STA_CNT1);
224 mt7601u_rr(dev, MT_RX_STA_CNT2);
225 mt7601u_rr(dev, MT_TX_STA_CNT0);
226 mt7601u_rr(dev, MT_TX_STA_CNT1);
227 mt7601u_rr(dev, MT_TX_STA_CNT2);
230 int mt7601u_mac_start(struct mt7601u_dev *dev)
232 mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
234 if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
238 dev->rxfilter = MT_RX_FILTR_CFG_CRC_ERR |
245 mt7601u_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
247 mt7601u_wr(dev, MT_MAC_SYS_CTRL,
250 if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
257 static void mt7601u_mac_stop_hw(struct mt7601u_dev *dev)
261 if (test_bit(MT7601U_STATE_REMOVED, &dev->state))
264 mt76_clear(dev, MT_BEACON_TIME_CFG, MT_BEACON_TIME_CFG_TIMER_EN |
268 if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_TX_BUSY, 0, 1000))
269 dev_warn(dev->dev, "Warning: TX DMA did not stop!\n");
273 while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) ||
274 (mt76_rr(dev, 0x0a30) & 0x000000ff) ||
275 (mt76_rr(dev, 0x0a34) & 0x00ff00ff)))
278 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000))
279 dev_warn(dev->dev, "Warning: MAC TX did not stop!\n");
281 mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX |
288 if (!(mt76_rr(dev, MT_RXQ_STA) & 0x00ff0000) &&
289 !mt76_rr(dev, 0x0a30) &&
290 !mt76_rr(dev, 0x0a34)) {
298 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000))
299 dev_warn(dev->dev, "Warning: MAC RX did not stop!\n");
301 if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_RX_BUSY, 0, 1000))
302 dev_warn(dev->dev, "Warning: RX DMA did not stop!\n");
305 void mt7601u_mac_stop(struct mt7601u_dev *dev)
307 mt7601u_mac_stop_hw(dev);
308 flush_delayed_work(&dev->stat_work);
309 cancel_delayed_work_sync(&dev->stat_work);
312 static void mt7601u_stop_hardware(struct mt7601u_dev *dev)
314 mt7601u_chip_onoff(dev, false, false);
317 int mt7601u_init_hardware(struct mt7601u_dev *dev)
328 dev->beacon_offsets = beacon_offsets;
330 mt7601u_chip_onoff(dev, true, false);
332 ret = mt7601u_wait_asic_ready(dev);
335 ret = mt7601u_mcu_init(dev);
339 if (!mt76_poll_msec(dev, MT_WPDMA_GLO_CFG,
347 ret = mt7601u_wait_asic_ready(dev);
351 mt7601u_reset_csr_bbp(dev);
352 mt7601u_init_usb_dma(dev);
354 ret = mt7601u_mcu_cmd_init(dev);
357 ret = mt7601u_dma_init(dev);
360 ret = mt7601u_write_mac_initvals(dev);
364 if (!mt76_poll_msec(dev, MT_MAC_STATUS,
370 ret = mt7601u_init_bbp(dev);
373 ret = mt7601u_init_wcid_mem(dev);
376 ret = mt7601u_init_key_mem(dev);
379 ret = mt7601u_init_wcid_attr_mem(dev);
383 mt76_clear(dev, MT_BEACON_TIME_CFG, (MT_BEACON_TIME_CFG_TIMER_EN |
388 mt7601u_reset_counters(dev);
390 mt7601u_rmw(dev, MT_US_CYC_CFG, MT_US_CYC_CNT, 0x1e);
392 mt7601u_wr(dev, MT_TXOP_CTRL_CFG,
396 ret = mt7601u_eeprom_init(dev);
400 ret = mt7601u_phy_init(dev);
404 mt7601u_set_rx_path(dev, 0);
405 mt7601u_set_tx_dac(dev, 0);
407 mt7601u_mac_set_ctrlch(dev, false);
408 mt7601u_bbp_set_ctrlch(dev, false);
409 mt7601u_bbp_set_bw(dev, MT_BW_20);
414 mt7601u_dma_cleanup(dev);
416 mt7601u_mcu_cmd_deinit(dev);
418 mt7601u_chip_onoff(dev, false, false);
422 void mt7601u_cleanup(struct mt7601u_dev *dev)
424 if (!test_and_clear_bit(MT7601U_STATE_INITIALIZED, &dev->state))
427 mt7601u_stop_hardware(dev);
428 mt7601u_dma_cleanup(dev);
429 mt7601u_mcu_cmd_deinit(dev);
435 struct mt7601u_dev *dev;
437 hw = ieee80211_alloc_hw(sizeof(*dev), &mt7601u_ops);
441 dev = hw->priv;
442 dev->dev = pdev;
443 dev->hw = hw;
444 mutex_init(&dev->vendor_req_mutex);
445 mutex_init(&dev->reg_atomic_mutex);
446 mutex_init(&dev->hw_atomic_mutex);
447 mutex_init(&dev->mutex);
448 spin_lock_init(&dev->tx_lock);
449 spin_lock_init(&dev->rx_lock);
450 spin_lock_init(&dev->lock);
451 spin_lock_init(&dev->mac_lock);
452 spin_lock_init(&dev->con_mon_lock);
453 atomic_set(&dev->avg_ampdu_len, 1);
454 skb_queue_head_init(&dev->tx_skb_done);
456 dev->stat_wq = alloc_workqueue("mt7601u", WQ_UNBOUND, 0);
457 if (!dev->stat_wq) {
462 return dev;
518 mt76_init_sband(struct mt7601u_dev *dev, struct ieee80211_supported_band *sband,
527 chanlist = devm_kmemdup(dev->dev, chan, size, GFP_KERNEL);
550 dev->chandef.chan = &sband->channels[0];
556 mt76_init_sband_2g(struct mt7601u_dev *dev)
558 dev->sband_2g = devm_kzalloc(dev->dev, sizeof(*dev->sband_2g),
560 if (!dev->sband_2g)
563 dev->hw->wiphy->bands[NL80211_BAND_2GHZ] = dev->sband_2g;
565 WARN_ON(dev->ee->reg.start - 1 + dev->ee->reg.num >
568 return mt76_init_sband(dev, dev->sband_2g,
569 &mt76_channels_2ghz[dev->ee->reg.start - 1],
570 dev->ee->reg.num,
574 int mt7601u_register_device(struct mt7601u_dev *dev)
576 struct ieee80211_hw *hw = dev->hw;
583 dev->wcid_mask[0] |= 1;
586 dev->mon_wcid = devm_kmalloc(dev->dev, sizeof(*dev->mon_wcid),
588 if (!dev->mon_wcid)
590 dev->mon_wcid->idx = 0xff;
591 dev->mon_wcid->hw_key_idx = -1;
593 SET_IEEE80211_DEV(hw, dev->dev);
609 SET_IEEE80211_PERM_ADDR(hw, dev->macaddr);
617 ret = mt76_init_sband_2g(dev);
621 INIT_DELAYED_WORK(&dev->mac_work, mt7601u_mac_work);
622 INIT_DELAYED_WORK(&dev->stat_work, mt7601u_tx_stat);
628 mt7601u_init_debugfs(dev);