Lines Matching refs:mt76
61 if (idx >= ARRAY_SIZE(dev->mt76.wcid))
64 wcid = rcu_dereference(dev->mt76.wcid[idx]);
109 spin_lock_bh(&dev->mt76.sta_poll_lock);
110 list_splice_init(&dev->mt76.sta_poll_list, &sta_poll_list);
111 spin_unlock_bh(&dev->mt76.sta_poll_lock);
121 spin_lock_bh(&dev->mt76.sta_poll_lock);
123 spin_unlock_bh(&dev->mt76.sta_poll_lock);
129 spin_unlock_bh(&dev->mt76.sta_poll_lock);
185 mt76_rx_signal(msta->vif->phy->mt76->antenna_mask, rssi);
315 i = mt76_get_rate(&dev->mt76, sband, i, cck);
418 mtk_wed_device_ppe_check(&dev->mt76.mmio.wed, skb,
428 struct mt76_phy *mphy = &dev->mt76.phy;
457 mphy = dev->mt76.phys[band_idx];
481 spin_lock_bh(&dev->mt76.sta_poll_lock);
484 &dev->mt76.sta_poll_list);
485 spin_unlock_bh(&dev->mt76.sta_poll_lock);
684 mt7996_wed_check_ppe(dev, &dev->mt76.q_rx[q], msta, skb,
878 if (is_mt7996(&dev->mt76))
917 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
931 wcid = &dev->mt76.global_wcid;
971 txp->fw.bss_idx = mvif->mt76.idx;
1052 struct mt76_dev *mdev = &dev->mt76;
1083 struct mt76_dev *mdev = &dev->mt76;
1126 wcid = rcu_dereference(dev->mt76.wcid[idx]);
1171 mt76_set_tx_blocked(&dev->mt76, false);
1173 mt76_worker_schedule(&dev->mt76.tx_worker);
1187 struct mt76_dev *mdev = &dev->mt76;
1216 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && wcid->sta) {
1351 wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
1362 spin_lock_bh(&dev->mt76.sta_poll_lock);
1364 list_add_tail(&msta->wcid.poll_list, &dev->mt76.sta_poll_list);
1365 spin_unlock_bh(&dev->mt76.sta_poll_lock);
1373 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
1406 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
1422 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2) &&
1445 mt76_rx(&dev->mt76, q, skb);
1458 u32 reg = MT_WF_PHYRX_BAND_RX_CTRL1(phy->mt76->band_idx);
1467 u8 band_idx = phy->mt76->band_idx;
1473 phy->mt76->survey_time = ktime_get_boottime();
1475 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats));
1495 u8 band_idx = phy->mt76->band_idx;
1498 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
1535 for (ant = 0; ant < hweight8(phy->mt76->antenna_mask); ant++) {
1599 ieee80211_iterate_active_interfaces(dev->mt76.hw,
1601 mt7996_update_vif_beacon, dev->mt76.hw);
1603 phy2 = dev->mt76.phys[MT_BAND1];
1611 phy3 = dev->mt76.phys[MT_BAND2];
1625 spin_lock_bh(&dev->mt76.token_lock);
1626 idr_for_each_entry(&dev->mt76.token, txwi, id) {
1628 dev->mt76.token_count--;
1630 spin_unlock_bh(&dev->mt76.token_lock);
1631 idr_destroy(&dev->mt76.token);
1638 struct mt76_dev *mdev = &dev->mt76;
1657 wake_up(&dev->mt76.mcu.wait);
1659 set_bit(MT76_RESET, &phy2->mt76->state);
1661 set_bit(MT76_RESET, &phy3->mt76->state);
1666 mt76_txq_schedule_all(phy2->mt76);
1668 mt76_txq_schedule_all(phy3->mt76);
1671 mt76_worker_disable(&dev->mt76.tx_worker);
1673 if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
1678 napi_disable(&dev->mt76.napi[i]);
1680 napi_disable(&dev->mt76.tx_napi);
1684 idr_init(&dev->mt76.token);
1690 if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
1695 napi_enable(&dev->mt76.napi[i]);
1696 napi_schedule(&dev->mt76.napi[i]);
1703 mt76_wr(dev, MT_INT_MASK_CSR, dev->mt76.mmio.irqmask);
1706 mt76_wr(dev, MT_INT1_MASK_CSR, dev->mt76.mmio.irqmask);
1737 if (phy2 && test_bit(MT76_STATE_RUNNING, &phy2->mt76->state)) {
1738 ret = mt7996_run(phy2->mt76->hw);
1743 if (phy3 && test_bit(MT76_STATE_RUNNING, &phy3->mt76->state)) {
1744 ret = mt7996_run(phy3->mt76->hw);
1753 clear_bit(MT76_RESET, &phy2->mt76->state);
1755 clear_bit(MT76_RESET, &phy3->mt76->state);
1758 napi_enable(&dev->mt76.tx_napi);
1759 napi_schedule(&dev->mt76.tx_napi);
1762 mt76_worker_enable(&dev->mt76.tx_worker);
1776 wake_up(&dev->mt76.mcu.wait);
1779 ieee80211_stop_queues(phy2->mt76->hw);
1781 ieee80211_stop_queues(phy3->mt76->hw);
1786 cancel_delayed_work_sync(&phy2->mt76->mac_work);
1788 cancel_delayed_work_sync(&phy3->mt76->mac_work);
1790 mutex_lock(&dev->mt76.mutex);
1795 mutex_unlock(&dev->mt76.mutex);
1798 dev_err(dev->mt76.dev, "chip full reset failed\n");
1802 ieee80211_restart_hw(phy2->mt76->hw);
1804 ieee80211_restart_hw(phy3->mt76->hw);
1808 ieee80211_wake_queues(phy2->mt76->hw);
1810 ieee80211_wake_queues(phy3->mt76->hw);
1817 ieee80211_queue_delayed_work(phy2->mt76->hw,
1818 &phy2->mt76->mac_work,
1821 ieee80211_queue_delayed_work(phy3->mt76->hw,
1822 &phy3->mt76->mac_work,
1864 dev_info(dev->mt76.dev,"\n%s L1 SER recovery start.",
1865 wiphy_name(dev->mt76.hw->wiphy));
1867 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2))
1868 mtk_wed_device_stop(&dev->mt76.mmio.wed_hif2);
1870 if (mtk_wed_device_active(&dev->mt76.mmio.wed))
1871 mtk_wed_device_stop(&dev->mt76.mmio.wed);
1875 ieee80211_stop_queues(phy2->mt76->hw);
1877 ieee80211_stop_queues(phy3->mt76->hw);
1881 wake_up(&dev->mt76.mcu.wait);
1886 set_bit(MT76_RESET, &phy2->mt76->state);
1887 cancel_delayed_work_sync(&phy2->mt76->mac_work);
1890 set_bit(MT76_RESET, &phy3->mt76->state);
1891 cancel_delayed_work_sync(&phy3->mt76->mac_work);
1893 mt76_worker_disable(&dev->mt76.tx_worker);
1894 mt76_for_each_q_rx(&dev->mt76, i) {
1895 if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
1896 mt76_queue_is_wed_rro(&dev->mt76.q_rx[i]))
1899 napi_disable(&dev->mt76.napi[i]);
1901 napi_disable(&dev->mt76.tx_napi);
1903 mutex_lock(&dev->mt76.mutex);
1911 idr_init(&dev->mt76.token);
1923 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
1925 dev->mt76.mmio.irqmask;
1927 if (mtk_wed_get_rx_capa(&dev->mt76.mmio.wed))
1932 mtk_wed_device_start_hw_rro(&dev->mt76.mmio.wed, wed_irq_mask,
1938 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2)) {
1940 mtk_wed_device_start(&dev->mt76.mmio.wed_hif2,
1947 clear_bit(MT76_RESET, &phy2->mt76->state);
1949 clear_bit(MT76_RESET, &phy3->mt76->state);
1952 mt76_for_each_q_rx(&dev->mt76, i) {
1953 if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
1954 mt76_queue_is_wed_rro(&dev->mt76.q_rx[i]))
1957 napi_enable(&dev->mt76.napi[i]);
1958 napi_schedule(&dev->mt76.napi[i]);
1962 tasklet_schedule(&dev->mt76.irq_tasklet);
1964 mt76_worker_enable(&dev->mt76.tx_worker);
1967 napi_enable(&dev->mt76.tx_napi);
1968 napi_schedule(&dev->mt76.tx_napi);
1973 ieee80211_wake_queues(phy2->mt76->hw);
1975 ieee80211_wake_queues(phy3->mt76->hw);
1977 mutex_unlock(&dev->mt76.mutex);
1984 ieee80211_queue_delayed_work(phy2->mt76->hw,
1985 &phy2->mt76->mac_work,
1988 ieee80211_queue_delayed_work(phy3->mt76->hw,
1989 &phy3->mt76->mac_work,
1991 dev_info(dev->mt76.dev,"\n%s L1 SER recovery completed.",
1992 wiphy_name(dev->mt76.hw->wiphy));
2030 dev_warn(dev->mt76.dev, "%s len %zu is too large\n",
2061 queue_work(dev->mt76.wq, &dev->reset_work);
2075 dev_info(dev->mt76.dev,
2077 wiphy_name(dev->mt76.hw->wiphy));
2080 queue_work(dev->mt76.wq, &dev->dump_work);
2084 queue_work(dev->mt76.wq, &dev->reset_work);
2092 u8 band_idx = phy->mt76->band_idx;
2225 phy->mt76->aggr_stats[i] += cnt;
2238 spin_lock_bh(&dev->mt76.sta_poll_lock);
2246 spin_unlock_bh(&dev->mt76.sta_poll_lock);
2260 spin_lock_bh(&dev->mt76.sta_poll_lock);
2263 spin_unlock_bh(&dev->mt76.sta_poll_lock);
2284 if (mtk_wed_device_active(&phy->dev->mt76.mmio.wed)) {
2314 switch (dev->mt76.region) {
2338 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2340 u8 band_idx = phy->mt76->band_idx;
2374 switch (dev->mt76.region) {
2407 prev_state = phy->mt76->dfs_state;
2408 dfs_state = mt76_phy_dfs_state(phy->mt76);
2428 phy->mt76->dfs_state = MT_DFS_STATE_CAC;
2435 phy->mt76->band_idx, MT_RX_SEL0, 0);
2437 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN;
2441 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE;
2446 phy->mt76->band_idx, MT_RX_SEL0, 0);
2451 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED;
2574 mutex_lock(&dev->mt76.mutex);
2639 mutex_unlock(&dev->mt76.mutex);
2653 lockdep_assert_held(&dev->mt76.mutex);