mt76/mt7996/dma.c

176 	u32 hif1_ofs = 0;
179 		hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
191 			mt76_clear(dev, MT_WFDMA0_RST + hif1_ofs,
195 			mt76_set(dev, MT_WFDMA0_RST + hif1_ofs,
210 		mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
222 	u32 hif1_ofs = 0;
226 		hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
244 			mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
280 	u32 hif1_ofs = 0;
283 		hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
288 		mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR + hif1_ofs, ~0);
296 		mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0 + hif1_ofs, 0);
297 		mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1 + hif1_ofs, 0);
298 		mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2 + hif1_ofs, 0);
311 		mt76_set(dev, MT_WFDMA0_BUSY_ENA + hif1_ofs,
336 		mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs,
341 		mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT1 + hif1_ofs,
353 		mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_45_TH + hif1_ofs, 0xc000c);
354 		mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_67_TH + hif1_ofs, 0x10008);
355 		mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_89_TH + hif1_ofs, 0x10008);
356 		mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_RRO_TH + hif1_ofs, 0x20);
365 			mt76_set(dev, MT_WFDMA0_RX_INT_PCIE_SEL + hif1_ofs,
447 	u32 hif1_ofs = 0;
455 		hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
540 		rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND2) + hif1_ofs;
566 		rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND1) + hif1_ofs;
576 		rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND1_WA) + hif1_ofs;
621 					       MT_RXQ_RING_BASE(MT_RXQ_RRO_BAND2) + hif1_ofs);
634 					       MT_RXQ_RING_BASE(MT_RXQ_TXFREE_BAND2) + hif1_ofs);
657 	u32 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
665 		mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,