mt76/mt76x2/pci_init.c

13 mt76x2_mac_pbf_init(struct mt76x02_dev *dev)
23 	mt76_set(dev, MT_PBF_SYS_CTRL, val);
24 	mt76_clear(dev, MT_PBF_SYS_CTRL, val);
26 	mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f);
27 	mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf);
31 mt76x2_fixup_xtal(struct mt76x02_dev *dev)
36 	eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_2);
46 		eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_1);
54 	mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset);
55 	mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL);
57 	eep_val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2);
60 		mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
63 		mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0);
70 int mt76x2_mac_reset(struct mt76x02_dev *dev, bool hard)
72 	const u8 *macaddr = dev->mphy.macaddr;
76 	if (!mt76x02_wait_for_mac(&dev->mt76))
79 	val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
88 	mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
90 	mt76x2_mac_pbf_init(dev);
91 	mt76_write_mac_initvals(dev);
92 	mt76x2_fixup_xtal(dev);
94 	mt76_clear(dev, MT_MAC_SYS_CTRL,
98 	if (is_mt7612(dev))
99 		mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN);
101 	mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000);
102 	mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31));
104 	mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000);
105 	mt76_wr(dev, MT_RF_SETTING_0, 0x08800000);
107 	mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000);
109 	mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401);
110 	mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
112 	mt76x02_mac_setaddr(dev, macaddr);
113 	mt76x02e_init_beacon_config(dev);
118 		mt76_wr(dev, MT_WCID_DROP_BASE + i * 4, 0);
121 		mt76x02_mac_wcid_setup(dev, i, 0, NULL);
122 		mt76_wr(dev, MT_WCID_TX_RATE(i), 0);
123 		mt76_wr(dev, MT_WCID_TX_RATE(i) + 4, 0);
127 		mt76x02_mac_wcid_setup(dev, MT_VIF_WCID(i), i, NULL);
131 			mt76x02_mac_shared_key_setup(dev, i, k, NULL);
134 		mt76_rr(dev, MT_TX_STAT_FIFO);
136 	mt76x02_set_tx_ackto(dev);
142 mt76x2_power_on_rf_patch(struct mt76x02_dev *dev)
144 	mt76_set(dev, 0x10130, BIT(0) | BIT(16));
147 	mt76_clear(dev, 0x1001c, 0xff);
148 	mt76_set(dev, 0x1001c, 0x30);
150 	mt76_wr(dev, 0x10014, 0x484f);
153 	mt76_set(dev, 0x10130, BIT(17));
156 	mt76_clear(dev, 0x10130, BIT(16));
159 	mt76_set(dev, 0x1014c, BIT(19) | BIT(20));
163 mt76x2_power_on_rf(struct mt76x02_dev *dev, int unit)
168 	mt76_set(dev, 0x10130, BIT(0) << shift);
172 	mt76_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift);
176 	mt76_clear(dev, 0x10130, BIT(2) << shift);
179 	mt76x2_power_on_rf_patch(dev);
181 	mt76_set(dev, 0x530, 0xf);
185 mt76x2_power_on(struct mt76x02_dev *dev)
190 	mt76_set(dev, MT_WLAN_MTC_CTRL, MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP);
196 	mt76_poll(dev, MT_WLAN_MTC_CTRL, val, val, 1000);
198 	mt76_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16);
201 	mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
204 	mt76_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
205 	mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xfff);
208 	mt76_clear(dev, 0x11204, BIT(3));
211 	mt76_set(dev, 0x10080, BIT(0));
214 	mt76_clear(dev, 0x10064, BIT(18));
216 	mt76x2_power_on_rf(dev, 0);
217 	mt76x2_power_on_rf(dev, 1);
220 int mt76x2_resume_device(struct mt76x02_dev *dev)
224 	mt76x02_dma_disable(dev);
225 	mt76x2_reset_wlan(dev, true);
226 	mt76x2_power_on(dev);
228 	err = mt76x2_mac_reset(dev, true);
232 	mt76x02_mac_start(dev);
234 	return mt76x2_mcu_init(dev);
237 static int mt76x2_init_hardware(struct mt76x02_dev *dev)
241 	mt76x02_dma_disable(dev);
242 	mt76x2_reset_wlan(dev, true);
243 	mt76x2_power_on(dev);
245 	ret = mt76x2_eeprom_init(dev);
249 	ret = mt76x2_mac_reset(dev, true);
253 	dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
255 	ret = mt76x02_dma_init(dev);
259 	set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
260 	mt76x02_mac_start(dev);
262 	ret = mt76x2_mcu_init(dev);
266 	mt76x2_mac_stop(dev, false);
271 void mt76x2_stop_hardware(struct mt76x02_dev *dev)
273 	cancel_delayed_work_sync(&dev->cal_work);
274 	cancel_delayed_work_sync(&dev->mphy.mac_work);
275 	cancel_delayed_work_sync(&dev->wdt_work);
276 	clear_bit(MT76_RESTART, &dev->mphy.state);
277 	mt76x02_mcu_set_radio_state(dev, false);
278 	mt76x2_mac_stop(dev, false);
281 void mt76x2_cleanup(struct mt76x02_dev *dev)
283 	tasklet_disable(&dev->dfs_pd.dfs_tasklet);
284 	tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
285 	mt76x2_stop_hardware(dev);
286 	mt76_dma_cleanup(&dev->mt76);
287 	mt76x02_mcu_cleanup(dev);
290 int mt76x2_register_device(struct mt76x02_dev *dev)
294 	INIT_DELAYED_WORK(&dev->cal_work, mt76x2_phy_calibrate);
295 	ret = mt76x02_init_device(dev);
299 	ret = mt76x2_init_hardware(dev);
303 	mt76x02_config_mac_addr_list(dev);
305 	ret = mt76_register_device(&dev->mt76, true, mt76x02_rates,
310 	mt76x02_init_debugfs(dev);
311 	mt76x2_init_txpower(dev, &dev->mphy.sband_2g.sband);
312 	mt76x2_init_txpower(dev, &dev->mphy.sband_5g.sband);
317 	mt76x2_stop_hardware(dev);