Lines Matching refs:trans
22 static void iwl_pcie_gen2_update_byte_tbl(struct iwl_trans *trans,
46 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
50 WARN_ON(trans->txqs.bc_table_dword);
58 WARN_ON(!trans->txqs.bc_table_dword);
69 void iwl_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq)
73 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq->id, txq->write_ptr);
79 iwl_write32(trans, HBUS_TARG_WRPTR, txq->write_ptr | (txq->id << 16));
82 static u8 iwl_txq_gen2_get_num_tbs(struct iwl_trans *trans,
88 int iwl_txq_gen2_set_tb(struct iwl_trans *trans, struct iwl_tfh_tfd *tfd,
91 int idx = iwl_txq_gen2_get_num_tbs(trans, tfd);
109 if (le16_to_cpu(tfd->num_tbs) >= trans->txqs.tfd.max_tbs) {
110 IWL_ERR(trans, "Error can not send more than %d chunks\n",
111 trans->txqs.tfd.max_tbs);
123 static void iwl_txq_set_tfd_invalid_gen2(struct iwl_trans *trans,
128 iwl_txq_gen2_set_tb(trans, tfd, trans->invalid_tx_cmd.dma,
129 trans->invalid_tx_cmd.size);
132 void iwl_txq_gen2_tfd_unmap(struct iwl_trans *trans, struct iwl_cmd_meta *meta,
138 num_tbs = iwl_txq_gen2_get_num_tbs(trans, tfd);
140 if (num_tbs > trans->txqs.tfd.max_tbs) {
141 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
148 dma_unmap_page(trans->dev,
153 dma_unmap_single(trans->dev,
159 iwl_txq_set_tfd_invalid_gen2(trans, tfd);
162 void iwl_txq_gen2_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
175 iwl_txq_gen2_tfd_unmap(trans, &txq->entries[idx].meta,
176 iwl_txq_get_tfd(trans, txq, idx));
185 iwl_op_mode_free_skb(trans->op_mode, skb);
190 static struct page *get_workaround_page(struct iwl_trans *trans,
196 page_ptr = (void *)((u8 *)skb->cb + trans->txqs.page_offs);
215 static int iwl_txq_gen2_set_tb_with_wa(struct iwl_trans *trans,
225 if (unlikely(dma_mapping_error(trans->dev, phys)))
229 ret = iwl_txq_gen2_set_tb(trans, tfd, phys, len);
255 page = get_workaround_page(trans, skb);
263 phys = dma_map_single(trans->dev, page_address(page), len,
265 if (unlikely(dma_mapping_error(trans->dev, phys)))
267 ret = iwl_txq_gen2_set_tb(trans, tfd, phys, len);
274 IWL_DEBUG_TX(trans,
282 dma_unmap_page(trans->dev, oldphys, len, DMA_TO_DEVICE);
284 dma_unmap_single(trans->dev, oldphys, len, DMA_TO_DEVICE);
286 trace_iwlwifi_dev_tx_tb(trans->dev, skb, virt, phys, len);
292 struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len,
295 struct iwl_tso_hdr_page *p = this_cpu_ptr(trans->txqs.tso_hdr_page);
298 page_ptr = (void *)((u8 *)skb->cb + trans->txqs.page_offs);
337 static int iwl_txq_gen2_build_amsdu(struct iwl_trans *trans,
353 trace_iwlwifi_dev_tx(trans->dev, skb, tfd, sizeof(*tfd),
366 hdr_page = get_page_hdr(trans, hdr_room, skb);
418 tb_phys = dma_map_single(trans->dev, start_hdr,
420 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
427 iwl_txq_gen2_set_tb(trans, tfd, tb_phys, tb_len);
428 trace_iwlwifi_dev_tx_tb(trans->dev, skb, start_hdr,
441 tb_phys = dma_map_single(trans->dev, tso.data,
443 ret = iwl_txq_gen2_set_tb_with_wa(trans, skb, tfd,
465 iwl_tfh_tfd *iwl_txq_gen2_build_tx_amsdu(struct iwl_trans *trans,
474 struct iwl_tfh_tfd *tfd = iwl_txq_get_tfd(trans, txq, idx);
486 iwl_txq_gen2_set_tb(trans, tfd, tb_phys, IWL_FIRST_TB_SIZE);
501 tb_phys = dma_map_single(trans->dev, tb1_addr, len, DMA_TO_DEVICE);
502 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
508 iwl_txq_gen2_set_tb(trans, tfd, tb_phys, len);
510 if (iwl_txq_gen2_build_amsdu(trans, skb, tfd, len + IWL_FIRST_TB_SIZE,
519 iwl_txq_gen2_tfd_unmap(trans, out_meta, tfd);
523 static int iwl_txq_gen2_tx_add_frags(struct iwl_trans *trans,
539 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
541 ret = iwl_txq_gen2_set_tb_with_wa(trans, skb, tfd, tb_phys,
552 iwl_tfh_tfd *iwl_txq_gen2_build_tx(struct iwl_trans *trans,
562 struct iwl_tfh_tfd *tfd = iwl_txq_get_tfd(trans, txq, idx);
578 iwl_txq_gen2_set_tb(trans, tfd, tb_phys, IWL_FIRST_TB_SIZE);
596 tb_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
597 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
603 iwl_txq_gen2_set_tb(trans, tfd, tb_phys, tb1_len);
604 trace_iwlwifi_dev_tx(trans->dev, skb, tfd, sizeof(*tfd), &dev_cmd->hdr,
613 tb_phys = dma_map_single(trans->dev, skb->data + hdr_len,
615 ret = iwl_txq_gen2_set_tb_with_wa(trans, skb, tfd, tb_phys,
622 if (iwl_txq_gen2_tx_add_frags(trans, skb, tfd, out_meta))
628 tb_phys = dma_map_single(trans->dev, frag->data,
630 ret = iwl_txq_gen2_set_tb_with_wa(trans, skb, tfd, tb_phys,
635 if (iwl_txq_gen2_tx_add_frags(trans, frag, tfd, out_meta))
642 iwl_txq_gen2_tfd_unmap(trans, out_meta, tfd);
647 struct iwl_tfh_tfd *iwl_txq_gen2_build_tfd(struct iwl_trans *trans,
655 struct iwl_tfh_tfd *tfd = iwl_txq_get_tfd(trans, txq, idx);
671 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
688 return iwl_txq_gen2_build_tx_amsdu(trans, txq, dev_cmd, skb,
690 return iwl_txq_gen2_build_tx(trans, txq, dev_cmd, skb, out_meta,
694 int iwl_txq_space(struct iwl_trans *trans, const struct iwl_txq *q)
705 if (q->n_window < trans->trans_cfg->base_params->max_tfd_queue_size)
708 max = trans->trans_cfg->base_params->max_tfd_queue_size - 1;
715 (trans->trans_cfg->base_params->max_tfd_queue_size - 1);
723 int iwl_txq_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
727 struct iwl_txq *txq = trans->txqs.txq[txq_id];
736 if (WARN_ONCE(!test_bit(txq_id, trans->txqs.queue_used),
741 skb_shinfo(skb)->nr_frags > IWL_TRANS_MAX_FRAGS(trans) &&
747 if (iwl_txq_space(trans, txq) < txq->high_mark) {
748 iwl_txq_stop(trans, txq);
751 if (unlikely(iwl_txq_space(trans, txq) < 3)) {
755 trans->txqs.dev_cmd_offs);
778 tfd = iwl_txq_gen2_build_tfd(trans, txq, dev_cmd, skb, out_meta);
784 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
797 iwl_pcie_gen2_update_byte_tbl(trans, txq, cmd_len,
798 iwl_txq_gen2_get_num_tbs(trans, tfd));
805 txq->write_ptr = iwl_txq_inc_wrap(trans, txq->write_ptr);
806 iwl_txq_inc_wr_ptr(trans, txq);
820 void iwl_txq_gen2_unmap(struct iwl_trans *trans, int txq_id)
822 struct iwl_txq *txq = trans->txqs.txq[txq_id];
826 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
829 if (txq_id != trans->txqs.cmd.q_id) {
834 iwl_txq_free_tso_page(trans, skb);
836 iwl_txq_gen2_free_tfd(trans, txq);
837 txq->read_ptr = iwl_txq_inc_wrap(trans, txq->read_ptr);
843 iwl_op_mode_free_skb(trans->op_mode, skb);
849 iwl_wake_queue(trans, txq);
852 static void iwl_txq_gen2_free_memory(struct iwl_trans *trans,
855 struct device *dev = trans->dev;
860 trans->txqs.tfd.size * txq->n_window,
869 dma_pool_free(trans->txqs.bc_pool,
882 static void iwl_txq_gen2_free(struct iwl_trans *trans, int txq_id)
891 txq = trans->txqs.txq[txq_id];
896 iwl_txq_gen2_unmap(trans, txq_id);
899 if (txq_id == trans->txqs.cmd.q_id)
906 iwl_txq_gen2_free_memory(trans, txq);
908 trans->txqs.txq[txq_id] = NULL;
910 clear_bit(txq_id, trans->txqs.queue_used);
939 int iwl_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, int slots_num,
944 trans->trans_cfg->base_params->max_tfd_queue_size;
973 void iwl_txq_free_tso_page(struct iwl_trans *trans, struct sk_buff *skb)
978 page_ptr = (void *)((u8 *)skb->cb + trans->txqs.page_offs);
991 void iwl_txq_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
998 if (trans->trans_cfg->gen2) {
999 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
1005 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
1009 IWL_ERR(trans,
1014 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
1015 (trans->trans_cfg->base_params->max_tfd_queue_size - 1),
1016 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
1017 (trans->trans_cfg->base_params->max_tfd_queue_size - 1),
1018 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
1024 struct iwl_trans *trans = txq->trans;
1034 iwl_txq_log_scd_error(trans, txq);
1036 iwl_force_nmi(trans);
1039 static void iwl_txq_set_tfd_invalid_gen1(struct iwl_trans *trans,
1044 iwl_pcie_gen1_tfd_set_tb(trans, tfd, 0, trans->invalid_tx_cmd.dma,
1045 trans->invalid_tx_cmd.size);
1048 int iwl_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq, int slots_num,
1051 size_t num_entries = trans->trans_cfg->gen2 ?
1052 slots_num : trans->trans_cfg->base_params->max_tfd_queue_size;
1063 tfd_sz = trans->txqs.tfd.size * num_entries;
1066 txq->trans = trans;
1088 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
1097 txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz,
1104 void *tfd = iwl_txq_get_tfd(trans, txq, i);
1106 if (trans->trans_cfg->gen2)
1107 iwl_txq_set_tfd_invalid_gen2(trans, tfd);
1109 iwl_txq_set_tfd_invalid_gen1(trans, tfd);
1114 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr);
1127 iwl_txq_dyn_alloc_dma(struct iwl_trans *trans, int size, unsigned int timeout)
1133 WARN_ON(!trans->txqs.bc_tbl_size);
1135 bc_tbl_size = trans->txqs.bc_tbl_size;
1145 txq->bc_tbl.addr = dma_pool_alloc(trans->txqs.bc_pool, GFP_KERNEL,
1148 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
1153 ret = iwl_txq_alloc(trans, txq, size, false);
1155 IWL_ERR(trans, "Tx queue alloc failed\n");
1158 ret = iwl_txq_init(trans, txq, size, false);
1160 IWL_ERR(trans, "Tx queue init failed\n");
1169 iwl_txq_gen2_free_memory(trans, txq);
1173 static int iwl_txq_alloc_response(struct iwl_trans *trans, struct iwl_txq *txq,
1190 if (qid >= ARRAY_SIZE(trans->txqs.txq)) {
1196 if (test_and_set_bit(qid, trans->txqs.queue_used)) {
1202 if (WARN_ONCE(trans->txqs.txq[qid],
1209 trans->txqs.txq[qid] = txq;
1210 wr_ptr &= (trans->trans_cfg->base_params->max_tfd_queue_size - 1);
1216 IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d\n", qid);
1223 iwl_txq_gen2_free_memory(trans, txq);
1227 int iwl_txq_dyn_alloc(struct iwl_trans *trans, u32 flags, u32 sta_mask,
1240 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_BZ &&
1241 trans->hw_rev_step == SILICON_A_STEP)
1244 txq = iwl_txq_dyn_alloc_dma(trans, size, timeout);
1248 if (trans->txqs.queue_alloc_cmd_ver == 0) {
1265 } else if (trans->txqs.queue_alloc_cmd_ver == 3) {
1283 ret = iwl_trans_send_cmd(trans, &hcmd);
1287 return iwl_txq_alloc_response(trans, txq, &hcmd);
1290 iwl_txq_gen2_free_memory(trans, txq);
1294 void iwl_txq_dyn_free(struct iwl_trans *trans, int queue)
1306 if (!test_and_clear_bit(queue, trans->txqs.queue_used)) {
1307 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1312 iwl_txq_gen2_free(trans, queue);
1314 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", queue);
1317 void iwl_txq_gen2_tx_free(struct iwl_trans *trans)
1321 memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used));
1324 for (i = 0; i < ARRAY_SIZE(trans->txqs.txq); i++) {
1325 if (!trans->txqs.txq[i])
1328 iwl_txq_gen2_free(trans, i);
1332 int iwl_txq_gen2_init(struct iwl_trans *trans, int txq_id, int queue_size)
1338 if (!trans->txqs.txq[txq_id]) {
1341 IWL_ERR(trans, "Not enough memory for tx queue\n");
1344 trans->txqs.txq[txq_id] = queue;
1345 ret = iwl_txq_alloc(trans, queue, queue_size, true);
1347 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
1351 queue = trans->txqs.txq[txq_id];
1354 ret = iwl_txq_init(trans, queue, queue_size,
1355 (txq_id == trans->txqs.cmd.q_id));
1357 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
1360 trans->txqs.txq[txq_id]->id = txq_id;
1361 set_bit(txq_id, trans->txqs.queue_used);
1366 iwl_txq_gen2_tx_free(trans);
1370 static inline dma_addr_t iwl_txq_gen1_tfd_tb_get_addr(struct iwl_trans *trans,
1392 void iwl_txq_gen1_tfd_unmap(struct iwl_trans *trans,
1397 struct iwl_tfd *tfd = iwl_txq_get_tfd(trans, txq, index);
1400 num_tbs = iwl_txq_gen1_tfd_get_num_tbs(trans, tfd);
1402 if (num_tbs > trans->txqs.tfd.max_tbs) {
1403 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
1412 dma_unmap_page(trans->dev,
1413 iwl_txq_gen1_tfd_tb_get_addr(trans,
1415 iwl_txq_gen1_tfd_tb_get_len(trans,
1419 dma_unmap_single(trans->dev,
1420 iwl_txq_gen1_tfd_tb_get_addr(trans,
1422 iwl_txq_gen1_tfd_tb_get_len(trans,
1429 iwl_txq_set_tfd_invalid_gen1(trans, tfd);
1438 void iwl_txq_gen1_update_byte_cnt_tbl(struct iwl_trans *trans,
1452 scd_bc_tbl = trans->txqs.scd_bc_tbls.addr;
1467 if (trans->txqs.bc_table_dword)
1482 void iwl_txq_gen1_inval_byte_cnt_tbl(struct iwl_trans *trans,
1485 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans->txqs.scd_bc_tbls.addr;
1495 if (txq_id != trans->txqs.cmd.q_id)
1509 * @trans - transport private data
1516 void iwl_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
1533 if (trans->trans_cfg->gen2)
1534 iwl_txq_gen2_tfd_unmap(trans, &txq->entries[idx].meta,
1535 iwl_txq_get_tfd(trans, txq, rd_ptr));
1537 iwl_txq_gen1_tfd_unmap(trans, &txq->entries[idx].meta,
1548 iwl_op_mode_free_skb(trans->op_mode, skb);
1578 void iwl_txq_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1581 struct iwl_txq *txq = trans->txqs.txq[txq_id];
1585 if (WARN_ON(txq_id == trans->txqs.cmd.q_id))
1596 if (!test_bit(txq_id, trans->txqs.queue_used)) {
1597 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
1605 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d (%d) -> %d (%d)\n",
1610 last_to_free = iwl_txq_dec_wrap(trans, tfd_num);
1613 IWL_ERR(trans,
1616 trans->trans_cfg->base_params->max_tfd_queue_size,
1619 iwl_op_mode_time_point(trans->op_mode,
1630 txq->read_ptr = iwl_txq_inc_wrap(trans, txq->read_ptr),
1638 iwl_txq_free_tso_page(trans, skb);
1644 if (!trans->trans_cfg->gen2)
1645 iwl_txq_gen1_inval_byte_cnt_tbl(trans, txq);
1647 iwl_txq_free_tfd(trans, txq);
1652 if (iwl_txq_space(trans, txq) > txq->low_mark &&
1653 test_bit(txq_id, trans->txqs.queue_stopped)) {
1683 trans->txqs.dev_cmd_offs);
1690 iwl_trans_tx(trans, skb, dev_cmd_ptr, txq_id);
1693 if (iwl_txq_space(trans, txq) > txq->low_mark)
1694 iwl_wake_queue(trans, txq);
1705 void iwl_txq_set_q_ptrs(struct iwl_trans *trans, int txq_id, int ptr)
1707 struct iwl_txq *txq = trans->txqs.txq[txq_id];
1717 void iwl_trans_txq_freeze_timer(struct iwl_trans *trans, unsigned long txqs,
1723 struct iwl_txq *txq = trans->txqs.txq[queue];
1733 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1771 static int iwl_trans_txq_send_hcmd_sync(struct iwl_trans *trans,
1774 const char *cmd_str = iwl_get_cmd_string(trans, cmd->id);
1775 struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id];
1779 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", cmd_str);
1782 &trans->status),
1786 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", cmd_str);
1788 cmd_idx = trans->ops->send_cmd(trans, cmd);
1791 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1792 IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
1797 ret = wait_event_timeout(trans->wait_command_queue,
1799 &trans->status),
1802 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1805 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1808 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1809 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1813 iwl_trans_sync_nmi(trans);
1817 if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1819 &trans->status)) {
1820 IWL_ERR(trans, "FW error in SYNC CMD %s\n", cmd_str);
1828 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
1829 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1835 IWL_ERR(trans, "Error: Response NULL in '%s'\n", cmd_str);
1861 int iwl_trans_txq_send_hcmd(struct iwl_trans *trans,
1865 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
1869 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
1870 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1875 if (unlikely(trans->system_pm_mode == IWL_PLAT_PM_MODE_D3 &&
1877 IWL_DEBUG_WOWLAN(trans, "Dropping CMD 0x%x: D3\n", cmd->id);
1888 ret = trans->ops->send_cmd(trans, cmd);
1890 IWL_ERR(trans,
1892 iwl_get_cmd_string(trans, cmd->id), ret);
1898 return iwl_trans_txq_send_hcmd_sync(trans, cmd);