Lines Matching refs:_il_wr
434 _il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
2071 _il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
4094 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
4120 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
4126 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
4352 _il_wr(il, CSR_INT, inta);
4358 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
4653 _il_wr(il, CSR_RESET, 0);
5122 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
5382 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
5540 _il_wr(il, CSR_INT, 0xFFFFFFFF);
5553 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5554 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5557 _il_wr(il, CSR_INT, 0xFFFFFFFF);
5561 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5562 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5840 _il_wr(il, CSR_INT, 0xFFFFFFFF);
6559 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);