intel/iwlegacy/4965-mac.c

1655 	int txq_id;
1725 	txq_id = skb_get_queue_mapping(skb);
1746 			txq_id = il->stations[sta_id].tid[tid].agg.txq_id;
1751 	txq = &il->txq[txq_id];
1785 			(QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
1943 	int txq_id;
1947 		for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1948 			if (txq_id == il->cmd_queue)
1951 				il_tx_queue_free(il, txq_id);
1968 	int ret, txq_id;
2004 	for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
2005 		ret = il_tx_queue_init(il, txq_id);
2007 			IL_ERR("Tx %d queue init failed\n", txq_id);
2026 	int txq_id;
2039 	for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2040 		il_tx_queue_reset(il, txq_id);
2046 	int txq_id;
2052 	for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2053 		if (txq_id == il->cmd_queue)
2056 			il_tx_queue_unmap(il, txq_id);
2092 	int txq_id;
2094 	for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2095 		if (!test_and_set_bit(txq_id, &il->txq_ctx_active_msk))
2096 			return txq_id;
2104 il4965_tx_queue_stop_scheduler(struct il_priv *il, u16 txq_id)
2108 	il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
2117 il4965_tx_queue_set_q2ratid(struct il_priv *il, u16 ra_tid, u16 txq_id)
2126 	    il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
2130 	if (txq_id & 0x1)
2143  * NOTE:  txq_id must be greater than IL49_FIRST_AMPDU_QUEUE,
2147 il4965_txq_agg_enable(struct il_priv *il, int txq_id, int tx_fifo, int sta_id,
2154 	if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2156 	     il->cfg->num_of_ampdu_queues <= txq_id)) {
2158 			txq_id, IL49_FIRST_AMPDU_QUEUE,
2174 	il4965_tx_queue_stop_scheduler(il, txq_id);
2177 	il4965_tx_queue_set_q2ratid(il, ra_tid, txq_id);
2180 	il_set_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2184 	il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2185 	il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2186 	il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2191 			  IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
2197 			  IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
2202 	il_set_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2205 	il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 1);
2218 	int txq_id;
2243 	txq_id = il4965_txq_ctx_activate_free(il);
2244 	if (txq_id == -1) {
2252 	tid_data->agg.txq_id = txq_id;
2253 	il_set_swq_id(&il->txq[txq_id], il4965_get_ac_from_tid(tid), txq_id);
2256 	ret = il4965_txq_agg_enable(il, txq_id, tx_fifo, sta_id, tid, *ssn);
2276  * txq_id must be greater than IL49_FIRST_AMPDU_QUEUE
2280 il4965_txq_agg_disable(struct il_priv *il, u16 txq_id, u16 ssn_idx, u8 tx_fifo)
2282 	if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2284 	     il->cfg->num_of_ampdu_queues <= txq_id)) {
2286 			txq_id, IL49_FIRST_AMPDU_QUEUE,
2292 	il4965_tx_queue_stop_scheduler(il, txq_id);
2294 	il_clear_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2296 	il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2297 	il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2299 	il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2301 	il_clear_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2302 	il_txq_ctx_deactivate(il, txq_id);
2303 	il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0);
2312 	int tx_fifo_id, txq_id, sta_id, ssn;
2333 	txq_id = tid_data->agg.txq_id;
2351 	write_ptr = il->txq[txq_id].q.write_ptr;
2352 	read_ptr = il->txq[txq_id].q.read_ptr;
2378 	il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo_id);
2387 il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id)
2389 	struct il_queue *q = &il->txq[txq_id].q;
2399 		if (txq_id == tid_data->agg.txq_id &&
2404 			il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo);
2452 il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
2454 	struct il_tx_queue *txq = &il->txq[txq_id];
2462 		       "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
2479 		il4965_tx_status(il, skb, txq_id >= IL4965_FIRST_AMPDU_QUEUE);
2644 			  struct il4965_tx_resp *tx_resp, int txq_id,
2671 		info = IEEE80211_SKB_CB(il->txq[txq_id].skbs[idx]);
2694 			txq_id = SEQ_TO_QUEUE(seq);
2701 			D_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
2702 				   agg->frame_count, txq_id, idx);
2704 			skb = il->txq[txq_id].skbs[idx];
2759 	int txq_id = SEQ_TO_QUEUE(sequence);
2761 	struct il_tx_queue *txq = &il->txq[txq_id];
2774 		IL_ERR("Read idx for DMA queue txq_id (%d) idx %d "
2775 		       "is out of range [0-%d] %d %d\n", txq_id, idx,
2821 		il4965_tx_status_reply_tx(il, agg, tx_resp, txq_id, idx);
2832 			freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2848 			   "rate_n_flags 0x%x retries %d\n", txq_id,
2853 		freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2865 		il4965_txq_check_empty(il, sta_id, tid, txq_id);
2930 	if (unlikely(agg->txq_id != scd_flow)) {
2937 		D_TX_REPLY("BA scd_flow %d does not match txq_id %d\n",
2938 			   scd_flow, agg->txq_id);
3996 	int txq_id = txq->q.id;
3999 	il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id), txq->q.dma_addr >> 8);
6274 il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx)
6276 	il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8));
6277 	il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx);
6284 	int txq_id = txq->q.id;
6287 	int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0;
6290 	il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
6300 	       scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);