Lines Matching defs:txq_id
272 il3945_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
274 struct il_tx_queue *txq = &il->txq[txq_id];
278 BUG_ON(txq_id == IL39_CMD_QUEUE_NUM);
289 if (il_queue_space(q) > q->low_mark && txq_id >= 0 &&
290 txq_id != IL39_CMD_QUEUE_NUM && il->mac80211_registered)
302 int txq_id = SEQ_TO_QUEUE(sequence);
304 struct il_tx_queue *txq = &il->txq[txq_id];
312 IL_ERR("Read idx for DMA queue txq_id (%d) idx %d "
313 "is out of range [0-%d] %d %d\n", txq_id, idx,
350 D_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n", txq_id,
355 il3945_tx_queue_reclaim(il, txq_id, idx);
839 int rc, txq_id;
854 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
855 rc = il_tx_queue_init(il, txq_id);
857 IL_ERR("Tx %d queue init failed\n", txq_id);
1004 int txq_id;
1008 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1009 if (txq_id == IL39_CMD_QUEUE_NUM)
1012 il_tx_queue_free(il, txq_id);
1022 int txq_id;
1029 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
1030 _il_wr(il, FH39_TCSR_CONFIG(txq_id), 0x0);
1032 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1033 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
2199 int txq_id = txq->q.id;
2203 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32) txq->q.dma_addr);
2205 il_wr(il, FH39_CBCC_CTRL(txq_id), 0);
2206 il_wr(il, FH39_CBCC_BASE(txq_id), 0);
2208 il_wr(il, FH39_TCSR_CONFIG(txq_id),