Lines Matching refs:il
80 * @il: eeprom and antenna fields are used to determine antenna flags
82 * il->eeprom39 is used to determine if antenna AUX/MAIN are reversed
90 il3945_get_antenna_flags(const struct il_priv *il)
92 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
117 il3945_set_ccmp_dynamic_key_info(struct il_priv *il,
127 if (sta_id == il->hw_params.bcast_id)
134 spin_lock_irqsave(&il->sta_lock, flags);
135 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
136 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
137 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
139 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
141 if ((il->stations[sta_id].sta.key.
143 il->stations[sta_id].sta.key.key_offset =
144 il_get_free_ucode_key_idx(il);
148 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
151 il->stations[sta_id].sta.key.key_flags = key_flags;
152 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
153 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
157 ret = il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
159 spin_unlock_irqrestore(&il->sta_lock, flags);
165 il3945_set_tkip_dynamic_key_info(struct il_priv *il,
172 il3945_set_wep_dynamic_key_info(struct il_priv *il,
179 il3945_clear_sta_key_info(struct il_priv *il, u8 sta_id)
184 spin_lock_irqsave(&il->sta_lock, flags);
185 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
186 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
187 il->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
188 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
189 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
190 memcpy(&sta_cmd, &il->stations[sta_id].sta,
192 spin_unlock_irqrestore(&il->sta_lock, flags);
195 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
199 il3945_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
208 ret = il3945_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
211 ret = il3945_set_tkip_dynamic_key_info(il, keyconf, sta_id);
215 ret = il3945_set_wep_dynamic_key_info(il, keyconf, sta_id);
229 il3945_remove_static_key(struct il_priv *il)
235 il3945_set_static_key(struct il_priv *il, struct ieee80211_key_conf *key)
246 il3945_clear_free_frames(struct il_priv *il)
250 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
252 while (!list_empty(&il->free_frames)) {
253 element = il->free_frames.next;
256 il->frames_count--;
259 if (il->frames_count) {
261 il->frames_count);
262 il->frames_count = 0;
267 il3945_get_free_frame(struct il_priv *il)
271 if (list_empty(&il->free_frames)) {
278 il->frames_count++;
282 element = il->free_frames.next;
288 il3945_free_frame(struct il_priv *il, struct il3945_frame *frame)
291 list_add(&frame->list, &il->free_frames);
295 il3945_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
299 if (!il_is_associated(il) || !il->beacon_skb)
302 if (il->beacon_skb->len > left)
305 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
307 return il->beacon_skb->len;
311 il3945_send_beacon_cmd(struct il_priv *il)
318 frame = il3945_get_free_frame(il);
326 rate = il_get_lowest_plcp(il);
328 frame_size = il3945_hw_get_beacon_cmd(il, frame, rate);
330 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
332 il3945_free_frame(il, frame);
338 il3945_unset_hw_params(struct il_priv *il)
340 if (il->_3945.shared_virt)
341 dma_free_coherent(&il->pci_dev->dev,
343 il->_3945.shared_virt, il->_3945.shared_phys);
347 il3945_build_tx_cmd_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
352 struct il_hw_key *keyinfo = &il->stations[sta_id].keyinfo;
391 il3945_build_tx_cmd_basic(struct il_priv *il, struct il_device_cmd *cmd,
424 il_tx_cmd_protection(il, info, fc, &tx_flags);
445 il3945_tx_skb(struct il_priv *il,
467 spin_lock_irqsave(&il->lock, flags);
468 if (il_is_rfkill(il)) {
473 if ((ieee80211_get_tx_rate(il->hw, info)->hw_value & 0xFF) ==
490 spin_unlock_irqrestore(&il->lock, flags);
495 sta_id = il_sta_id_or_broadcast(il, sta);
511 txq = &il->txq[txq_id];
517 spin_lock_irqsave(&il->lock, flags);
545 il3945_build_tx_cmd_hwcrypto(il, info, out_cmd, skb, sta_id);
548 il3945_build_tx_cmd_basic(il, out_cmd, info, hdr, sta_id);
550 il3945_hw_build_tx_cmd_rate(il, out_cmd, info, hdr, sta_id);
574 txcmd_phys = dma_map_single(&il->pci_dev->dev, &out_cmd->hdr, firstlen,
576 if (unlikely(dma_mapping_error(&il->pci_dev->dev, txcmd_phys)))
583 phys_addr = dma_map_single(&il->pci_dev->dev, skb->data + hdr_len,
585 if (unlikely(dma_mapping_error(&il->pci_dev->dev, phys_addr)))
591 il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0);
595 il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, secondlen, 0,
605 il_update_stats(il, true, fc, skb->len);
609 il_print_hex_dump(il, IL_DL_TX, tx_cmd, sizeof(*tx_cmd));
610 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr,
615 il_txq_update_write_ptr(il, txq);
616 spin_unlock_irqrestore(&il->lock, flags);
618 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
620 spin_lock_irqsave(&il->lock, flags);
622 il_txq_update_write_ptr(il, txq);
623 spin_unlock_irqrestore(&il->lock, flags);
626 il_stop_queue(il, txq);
632 spin_unlock_irqrestore(&il->lock, flags);
638 il3945_get_measurement(struct il_priv *il,
653 if (il_is_associated(il))
655 il_usecs_to_beacons(il,
657 il->_3945.last_tsf,
658 le16_to_cpu(il->timing.beacon_interval));
669 if (il_is_associated(il))
671 il_add_beacon_time(il, il->_3945.last_beacon_time, add_time,
672 le16_to_cpu(il->timing.beacon_interval));
679 if (il->active.flags & RXON_FLG_BAND_24G_MSK)
684 rc = il_send_cmd_sync(il, &cmd);
700 il->measurement_status &= ~MEASUREMENT_READY;
702 il->measurement_status |= MEASUREMENT_ACTIVE;
711 il_free_pages(il, cmd.reply_page);
717 il3945_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
730 memcpy(&il->card_alive_init, &pkt->u.alive_frame,
732 pwork = &il->init_alive_start;
735 memcpy(&il->card_alive, &pkt->u.alive_frame,
737 pwork = &il->alive_start;
738 il3945_disable_events(il);
744 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
750 il3945_hdl_add_sta(struct il_priv *il, struct il_rx_buf *rxb)
758 il3945_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
772 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
779 il3945_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
783 unsigned long status = il->status;
789 _il_wr(il, CSR_UCODE_DRV_GP1_SET, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
792 set_bit(S_RFKILL, &il->status);
794 clear_bit(S_RFKILL, &il->status);
796 il_scan_cancel(il);
799 test_bit(S_RFKILL, &il->status)))
800 wiphy_rfkill_set_hw_state(il->hw->wiphy,
801 test_bit(S_RFKILL, &il->status));
803 wake_up(&il->wait_command_queue);
816 il3945_setup_handlers(struct il_priv *il)
818 il->handlers[N_ALIVE] = il3945_hdl_alive;
819 il->handlers[C_ADD_STA] = il3945_hdl_add_sta;
820 il->handlers[N_ERROR] = il_hdl_error;
821 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
822 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
823 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
824 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
825 il->handlers[N_BEACON] = il3945_hdl_beacon;
832 il->handlers[C_STATS] = il3945_hdl_c_stats;
833 il->handlers[N_STATS] = il3945_hdl_stats;
835 il_setup_rx_scan_handlers(il);
836 il->handlers[N_CARD_STATE] = il3945_hdl_card_state;
839 il3945_hw_handler_setup(il);
910 il3945_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
927 il3945_rx_queue_restock(struct il_priv *il)
929 struct il_rx_queue *rxq = &il->rxq;
943 il3945_dma_addr2rbd_ptr(il, rxb->page_dma);
952 queue_work(il->workqueue, &il->rx_replenish);
961 il_rx_queue_update_write_ptr(il, rxq);
974 il3945_rx_allocate(struct il_priv *il, gfp_t priority)
976 struct il_rx_queue *rxq = &il->rxq;
995 if (il->hw_params.rx_page_order > 0)
999 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
1016 dma_map_page(&il->pci_dev->dev, page, 0,
1017 PAGE_SIZE << il->hw_params.rx_page_order,
1020 if (unlikely(dma_mapping_error(&il->pci_dev->dev, page_dma))) {
1021 __free_pages(page, il->hw_params.rx_page_order);
1029 dma_unmap_page(&il->pci_dev->dev, page_dma,
1030 PAGE_SIZE << il->hw_params.rx_page_order,
1032 __free_pages(page, il->hw_params.rx_page_order);
1044 il->alloc_rxb_page++;
1051 il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
1063 dma_unmap_page(&il->pci_dev->dev,
1065 PAGE_SIZE << il->hw_params.rx_page_order,
1067 __il_free_pages(il, rxq->pool[i].page);
1084 struct il_priv *il = data;
1087 il3945_rx_allocate(il, GFP_KERNEL);
1089 spin_lock_irqsave(&il->lock, flags);
1090 il3945_rx_queue_restock(il);
1091 spin_unlock_irqrestore(&il->lock, flags);
1095 il3945_rx_replenish_now(struct il_priv *il)
1097 il3945_rx_allocate(il, GFP_ATOMIC);
1099 il3945_rx_queue_restock(il);
1108 il3945_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
1113 dma_unmap_page(&il->pci_dev->dev,
1115 PAGE_SIZE << il->hw_params.rx_page_order,
1117 __il_free_pages(il, rxq->pool[i].page);
1122 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
1124 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
1171 * Uses the il->handlers callback function array to invoke
1176 il3945_rx_handle(struct il_priv *il)
1180 struct il_rx_queue *rxq = &il->rxq;
1214 dma_unmap_page(&il->pci_dev->dev, rxb->page_dma,
1215 PAGE_SIZE << il->hw_params.rx_page_order,
1218 reclaim = il_need_reclaim(il, pkt);
1223 if (il->handlers[pkt->hdr.cmd]) {
1226 il->isr_stats.handlers[pkt->hdr.cmd]++;
1227 il->handlers[pkt->hdr.cmd] (il, rxb);
1246 il_tx_cmd_complete(il, rxb);
1257 dma_map_page(&il->pci_dev->dev, rxb->page, 0,
1258 PAGE_SIZE << il->hw_params.rx_page_order,
1260 if (unlikely(dma_mapping_error(&il->pci_dev->dev,
1262 __il_free_pages(il, rxb->page);
1281 il3945_rx_replenish_now(il);
1290 il3945_rx_replenish_now(il);
1292 il3945_rx_queue_restock(il);
1297 il3945_synchronize_irq(struct il_priv *il)
1300 synchronize_irq(il->pci_dev->irq);
1301 tasklet_kill(&il->irq_tasklet);
1329 il3945_dump_nic_error_log(struct il_priv *il)
1335 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
1342 count = il_read_targ_mem(il, base);
1346 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
1354 desc = il_read_targ_mem(il, base + i);
1355 time = il_read_targ_mem(il, base + i + 1 * sizeof(u32));
1356 blink1 = il_read_targ_mem(il, base + i + 2 * sizeof(u32));
1357 blink2 = il_read_targ_mem(il, base + i + 3 * sizeof(u32));
1358 ilink1 = il_read_targ_mem(il, base + i + 4 * sizeof(u32));
1359 ilink2 = il_read_targ_mem(il, base + i + 5 * sizeof(u32));
1360 data1 = il_read_targ_mem(il, base + i + 6 * sizeof(u32));
1371 struct il_priv *il = from_tasklet(il, t, irq_tasklet);
1379 spin_lock_irqsave(&il->lock, flags);
1384 inta = _il_rd(il, CSR_INT);
1385 _il_wr(il, CSR_INT, inta);
1390 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
1391 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
1394 if (il_get_debug_level(il) & IL_DL_ISR) {
1396 inta_mask = _il_rd(il, CSR_INT_MASK);
1402 spin_unlock_irqrestore(&il->lock, flags);
1418 il_disable_interrupts(il);
1420 il->isr_stats.hw++;
1421 il_irq_handle_error(il);
1428 if (il_get_debug_level(il) & (IL_DL_ISR)) {
1433 il->isr_stats.sch++;
1439 il->isr_stats.alive++;
1450 il->isr_stats.sw++;
1451 il_irq_handle_error(il);
1458 il_rx_queue_update_write_ptr(il, &il->rxq);
1460 spin_lock_irqsave(&il->lock, flags);
1461 il_txq_update_write_ptr(il, &il->txq[0]);
1462 il_txq_update_write_ptr(il, &il->txq[1]);
1463 il_txq_update_write_ptr(il, &il->txq[2]);
1464 il_txq_update_write_ptr(il, &il->txq[3]);
1465 il_txq_update_write_ptr(il, &il->txq[4]);
1466 spin_unlock_irqrestore(&il->lock, flags);
1468 il->isr_stats.wakeup++;
1476 il3945_rx_handle(il);
1477 il->isr_stats.rx++;
1483 il->isr_stats.tx++;
1485 _il_wr(il, CSR_FH_INT_STATUS, (1 << 6));
1486 il_wr(il, FH39_TCSR_CREDIT(FH39_SRVC_CHNL), 0x0);
1492 il->isr_stats.unhandled++;
1495 if (inta & ~il->inta_mask) {
1497 inta & ~il->inta_mask);
1503 if (test_bit(S_INT_ENABLED, &il->status))
1504 il_enable_interrupts(il);
1507 if (il_get_debug_level(il) & (IL_DL_ISR)) {
1508 inta = _il_rd(il, CSR_INT);
1509 inta_mask = _il_rd(il, CSR_INT_MASK);
1510 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
1518 il3945_get_channels_for_scan(struct il_priv *il, enum nl80211_band band,
1530 sband = il_get_hw_mode(il, band);
1534 active_dwell = il_get_active_dwell_time(il, band, n_probes);
1535 passive_dwell = il_get_passive_dwell_time(il, band, vif);
1540 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
1541 chan = il->scan_request->channels[i];
1548 ch_info = il_get_channel_info(il, band, scan_ch->channel);
1563 if (IL_UCODE_API(il->ucode_ver) == 1)
1574 if (IL_UCODE_API(il->ucode_ver) >= 2) {
1612 il3945_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
1639 il3945_dealloc_ucode_pci(struct il_priv *il)
1641 il_free_fw_desc(il->pci_dev, &il->ucode_code);
1642 il_free_fw_desc(il->pci_dev, &il->ucode_data);
1643 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
1644 il_free_fw_desc(il->pci_dev, &il->ucode_init);
1645 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
1646 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
1654 il3945_verify_inst_full(struct il_priv *il, __le32 * image, u32 len)
1663 il_wr(il, HBUS_TARG_MEM_RADDR, IL39_RTC_INST_LOWER_BOUND);
1670 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
1694 il3945_verify_inst_sparse(struct il_priv *il, __le32 * image, u32 len)
1707 il_wr(il, HBUS_TARG_MEM_RADDR, i + IL39_RTC_INST_LOWER_BOUND);
1708 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
1730 il3945_verify_ucode(struct il_priv *il)
1737 image = (__le32 *) il->ucode_boot.v_addr;
1738 len = il->ucode_boot.len;
1739 rc = il3945_verify_inst_sparse(il, image, len);
1746 image = (__le32 *) il->ucode_init.v_addr;
1747 len = il->ucode_init.len;
1748 rc = il3945_verify_inst_sparse(il, image, len);
1755 image = (__le32 *) il->ucode_code.v_addr;
1756 len = il->ucode_code.len;
1757 rc = il3945_verify_inst_sparse(il, image, len);
1768 image = (__le32 *) il->ucode_boot.v_addr;
1769 len = il->ucode_boot.len;
1770 rc = il3945_verify_inst_full(il, image, len);
1776 il3945_nic_start(struct il_priv *il)
1779 _il_wr(il, CSR_RESET, 0);
1812 il3945_read_ucode(struct il_priv *il)
1818 const char *name_pre = il->cfg->fw_name_pre;
1819 const unsigned int api_max = il->cfg->ucode_api_max;
1820 const unsigned int api_min = il->cfg->ucode_api_min;
1830 ret = request_firmware(&ucode_raw, buf, &il->pci_dev->dev);
1862 il->ucode_ver = le32_to_cpu(ucode->ver);
1863 api_ver = IL_UCODE_API(il->ucode_ver);
1879 il->ucode_ver = 0;
1890 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
1891 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
1893 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
1894 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
1895 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
1896 IL_UCODE_SERIAL(il->ucode_ver));
1898 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
1952 il->ucode_code.len = inst_size;
1953 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
1955 il->ucode_data.len = data_size;
1956 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
1958 il->ucode_data_backup.len = data_size;
1959 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
1961 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
1962 !il->ucode_data_backup.v_addr)
1967 il->ucode_init.len = init_size;
1968 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
1970 il->ucode_init_data.len = init_data_size;
1971 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
1973 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
1979 il->ucode_boot.len = boot_size;
1980 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
1982 if (!il->ucode_boot.v_addr)
1991 memcpy(il->ucode_code.v_addr, src, len);
1995 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
2001 memcpy(il->ucode_data.v_addr, src, len);
2002 memcpy(il->ucode_data_backup.v_addr, src, len);
2009 memcpy(il->ucode_init.v_addr, src, len);
2017 memcpy(il->ucode_init_data.v_addr, src, len);
2024 memcpy(il->ucode_boot.v_addr, src, len);
2033 il3945_dealloc_ucode_pci(il);
2052 il3945_set_ucode_ptrs(struct il_priv *il)
2058 pinst = il->ucode_code.p_addr;
2059 pdata = il->ucode_data_backup.p_addr;
2062 il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
2063 il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
2064 il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, il->ucode_data.len);
2068 il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
2069 il->ucode_code.len | BSM_DRAM_INST_LOAD);
2084 il3945_init_alive_start(struct il_priv *il)
2087 if (il->card_alive_init.is_valid != UCODE_VALID_OK) {
2097 if (il3945_verify_ucode(il)) {
2108 if (il3945_set_ucode_ptrs(il)) {
2117 queue_work(il->workqueue, &il->restart);
2126 il3945_alive_start(struct il_priv *il)
2133 if (il->card_alive.is_valid != UCODE_VALID_OK) {
2143 if (il3945_verify_ucode(il)) {
2150 rfkill = il_rd_prph(il, APMG_RFKILL_REG);
2154 clear_bit(S_RFKILL, &il->status);
2157 while (il3945_hw_get_temperature(il) == 0) {
2166 set_bit(S_RFKILL, &il->status);
2169 set_bit(S_ALIVE, &il->status);
2172 il_setup_watchdog(il);
2174 if (il_is_rfkill(il))
2177 ieee80211_wake_queues(il->hw);
2179 il->active_rate = RATES_MASK_3945;
2181 il_power_update_mode(il, true);
2183 if (il_is_associated(il)) {
2185 (struct il3945_rxon_cmd *)(&il->active);
2187 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2191 il_connection_init_rx_config(il);
2195 il_send_bt_config(il);
2197 set_bit(S_READY, &il->status);
2200 il3945_commit_rxon(il);
2202 il3945_reg_txpower_periodic(il);
2205 wake_up(&il->wait_command_queue);
2210 queue_work(il->workqueue, &il->restart);
2213 static void il3945_cancel_deferred_work(struct il_priv *il);
2216 __il3945_down(struct il_priv *il)
2223 il_scan_cancel_timeout(il, 200);
2225 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
2229 del_timer_sync(&il->watchdog);
2232 il_clear_ucode_stations(il);
2233 il_dealloc_bcast_stations(il);
2234 il_clear_driver_stations(il);
2237 wake_up_all(&il->wait_command_queue);
2242 clear_bit(S_EXIT_PENDING, &il->status);
2245 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2248 spin_lock_irqsave(&il->lock, flags);
2249 il_disable_interrupts(il);
2250 spin_unlock_irqrestore(&il->lock, flags);
2251 il3945_synchronize_irq(il);
2253 if (il->mac80211_registered)
2254 ieee80211_stop_queues(il->hw);
2258 if (!il_is_init(il)) {
2259 il->status =
2260 test_bit(S_RFKILL, &il->status) << S_RFKILL |
2261 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
2262 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
2268 il->status &=
2269 test_bit(S_RFKILL, &il->status) << S_RFKILL |
2270 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
2271 test_bit(S_FW_ERROR, &il->status) << S_FW_ERROR |
2272 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
2279 spin_lock_irq(&il->reg_lock);
2282 il3945_hw_txq_ctx_stop(il);
2283 il3945_hw_rxq_stop(il);
2285 _il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2288 _il_apm_stop(il);
2290 spin_unlock_irq(&il->reg_lock);
2292 il3945_hw_txq_ctx_free(il);
2294 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
2295 dev_kfree_skb(il->beacon_skb);
2296 il->beacon_skb = NULL;
2299 il3945_clear_free_frames(il);
2303 il3945_down(struct il_priv *il)
2305 mutex_lock(&il->mutex);
2306 __il3945_down(il);
2307 mutex_unlock(&il->mutex);
2309 il3945_cancel_deferred_work(il);
2315 il3945_alloc_bcast_station(struct il_priv *il)
2320 spin_lock_irqsave(&il->sta_lock, flags);
2321 sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
2324 spin_unlock_irqrestore(&il->sta_lock, flags);
2329 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
2330 il->stations[sta_id].used |= IL_STA_BCAST;
2331 spin_unlock_irqrestore(&il->sta_lock, flags);
2337 __il3945_up(struct il_priv *il)
2341 rc = il3945_alloc_bcast_station(il);
2345 if (test_bit(S_EXIT_PENDING, &il->status)) {
2350 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
2356 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2357 clear_bit(S_RFKILL, &il->status);
2359 set_bit(S_RFKILL, &il->status);
2363 _il_wr(il, CSR_INT, 0xFFFFFFFF);
2365 rc = il3945_hw_nic_init(il);
2372 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2373 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2376 _il_wr(il, CSR_INT, 0xFFFFFFFF);
2377 il_enable_interrupts(il);
2380 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2381 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2386 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
2387 il->ucode_data.len);
2390 if (test_bit(S_RFKILL, &il->status))
2398 rc = il->ops->load_ucode(il);
2406 il3945_nic_start(il);
2413 set_bit(S_EXIT_PENDING, &il->status);
2414 __il3945_down(il);
2415 clear_bit(S_EXIT_PENDING, &il->status);
2432 struct il_priv *il =
2435 mutex_lock(&il->mutex);
2436 if (test_bit(S_EXIT_PENDING, &il->status))
2439 il3945_init_alive_start(il);
2441 mutex_unlock(&il->mutex);
2447 struct il_priv *il =
2450 mutex_lock(&il->mutex);
2451 if (test_bit(S_EXIT_PENDING, &il->status) || il->txq == NULL)
2454 il3945_alive_start(il);
2456 mutex_unlock(&il->mutex);
2468 struct il_priv *il =
2470 bool old_rfkill = test_bit(S_RFKILL, &il->status);
2472 !(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
2476 set_bit(S_RFKILL, &il->status);
2478 clear_bit(S_RFKILL, &il->status);
2480 wiphy_rfkill_set_hw_state(il->hw->wiphy, new_rfkill);
2488 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
2494 il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
2508 lockdep_assert_held(&il->mutex);
2510 if (!il->scan_cmd) {
2511 il->scan_cmd =
2514 if (!il->scan_cmd) {
2519 scan = il->scan_cmd;
2525 if (il_is_associated(il)) {
2555 if (il->scan_request->n_ssids) {
2558 for (i = 0; i < il->scan_request->n_ssids; i++) {
2560 if (!il->scan_request->ssids[i].ssid_len)
2564 il->scan_request->ssids[i].ssid_len;
2566 il->scan_request->ssids[i].ssid,
2567 il->scan_request->ssids[i].ssid_len);
2578 scan->tx_cmd.sta_id = il->hw_params.bcast_id;
2583 switch (il->scan_band) {
2607 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
2608 vif->addr, il->scan_request->ie,
2609 il->scan_request->ie_len,
2614 scan->flags |= il3945_get_antenna_flags(il);
2617 il3945_get_channels_for_scan(il, band, is_active, n_probes,
2630 set_bit(S_SCAN_HW, &il->status);
2631 ret = il_send_cmd_sync(il, &cmd);
2633 clear_bit(S_SCAN_HW, &il->status);
2638 il3945_post_scan(struct il_priv *il)
2644 if (memcmp(&il->staging, &il->active, sizeof(il->staging)))
2645 il3945_commit_rxon(il);
2651 struct il_priv *il = container_of(data, struct il_priv, restart);
2653 if (test_bit(S_EXIT_PENDING, &il->status))
2656 if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
2657 mutex_lock(&il->mutex);
2658 il->is_open = 0;
2659 mutex_unlock(&il->mutex);
2660 il3945_down(il);
2661 ieee80211_restart_hw(il->hw);
2663 il3945_down(il);
2665 mutex_lock(&il->mutex);
2666 if (test_bit(S_EXIT_PENDING, &il->status)) {
2667 mutex_unlock(&il->mutex);
2671 __il3945_up(il);
2672 mutex_unlock(&il->mutex);
2679 struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
2681 mutex_lock(&il->mutex);
2682 if (test_bit(S_EXIT_PENDING, &il->status))
2685 il3945_rx_replenish(il);
2687 mutex_unlock(&il->mutex);
2691 il3945_post_associate(struct il_priv *il)
2695 if (!il->vif || !il->is_open)
2698 D_ASSOC("Associated as %d to: %pM\n", il->vif->cfg.aid,
2699 il->active.bssid_addr);
2701 if (test_bit(S_EXIT_PENDING, &il->status))
2704 il_scan_cancel_timeout(il, 200);
2706 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2707 il3945_commit_rxon(il);
2709 rc = il_send_rxon_timing(il);
2713 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2715 il->staging.assoc_id = cpu_to_le16(il->vif->cfg.aid);
2717 D_ASSOC("assoc id %d beacon interval %d\n", il->vif->cfg.aid,
2718 il->vif->bss_conf.beacon_int);
2720 if (il->vif->bss_conf.use_short_preamble)
2721 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2723 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2725 if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
2726 if (il->vif->bss_conf.use_short_slot)
2727 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
2729 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2732 il3945_commit_rxon(il);
2734 switch (il->vif->type) {
2736 il3945_rate_scale_init(il->hw, IL_AP_ID);
2739 il3945_send_beacon_cmd(il);
2743 il->vif->type);
2759 struct il_priv *il = hw->priv;
2763 mutex_lock(&il->mutex);
2769 if (!il->ucode_code.len) {
2770 ret = il3945_read_ucode(il);
2773 mutex_unlock(&il->mutex);
2778 ret = __il3945_up(il);
2780 mutex_unlock(&il->mutex);
2789 ret = wait_event_timeout(il->wait_command_queue,
2790 test_bit(S_READY, &il->status),
2793 if (!test_bit(S_READY, &il->status)) {
2803 cancel_delayed_work(&il->_3945.rfkill_poll);
2805 il->is_open = 1;
2810 il->is_open = 0;
2818 struct il_priv *il = hw->priv;
2822 if (!il->is_open) {
2827 il->is_open = 0;
2829 il3945_down(il);
2831 flush_workqueue(il->workqueue);
2834 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
2845 struct il_priv *il = hw->priv;
2852 if (il3945_tx_skb(il, control->sta, skb))
2859 il3945_config_ap(struct il_priv *il)
2861 struct ieee80211_vif *vif = il->vif;
2864 if (test_bit(S_EXIT_PENDING, &il->status))
2868 if (!(il_is_associated(il))) {
2871 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2872 il3945_commit_rxon(il);
2875 rc = il_send_rxon_timing(il);
2880 il->staging.assoc_id = 0;
2883 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2885 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2887 if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
2889 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
2891 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2894 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2895 il3945_commit_rxon(il);
2897 il3945_send_beacon_cmd(il);
2905 struct il_priv *il = hw->priv;
2927 static_key = !il_is_associated(il);
2930 sta_id = il_sta_id_or_broadcast(il, sta);
2937 mutex_lock(&il->mutex);
2938 il_scan_cancel_timeout(il, 100);
2943 ret = il3945_set_static_key(il, key);
2945 ret = il3945_set_dynamic_key(il, key, sta_id);
2950 ret = il3945_remove_static_key(il);
2952 ret = il3945_clear_sta_key_info(il, sta_id);
2960 mutex_unlock(&il->mutex);
2969 struct il_priv *il = hw->priv;
2975 mutex_lock(&il->mutex);
2979 ret = il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
2983 mutex_unlock(&il->mutex);
2991 il3945_rs_rate_init(il, sta, sta_id);
2992 mutex_unlock(&il->mutex);
3001 struct il_priv *il = hw->priv;
3020 mutex_lock(&il->mutex);
3022 il->staging.filter_flags &= ~filter_nand;
3023 il->staging.filter_flags |= filter_or;
3031 mutex_unlock(&il->mutex);
3067 struct il_priv *il = dev_get_drvdata(d);
3068 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
3075 struct il_priv *il = dev_get_drvdata(d);
3083 il->debug_level = val;
3097 struct il_priv *il = dev_get_drvdata(d);
3099 if (!il_is_alive(il))
3102 return sprintf(buf, "%d\n", il3945_hw_get_temperature(il));
3110 struct il_priv *il = dev_get_drvdata(d);
3111 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
3118 struct il_priv *il = dev_get_drvdata(d);
3126 il3945_hw_reg_set_txpower(il, val);
3136 struct il_priv *il = dev_get_drvdata(d);
3138 return sprintf(buf, "0x%04X\n", il->active.flags);
3145 struct il_priv *il = dev_get_drvdata(d);
3148 mutex_lock(&il->mutex);
3149 if (le32_to_cpu(il->staging.flags) != flags) {
3151 if (il_scan_cancel_timeout(il, 100))
3155 il->staging.flags = cpu_to_le32(flags);
3156 il3945_commit_rxon(il);
3159 mutex_unlock(&il->mutex);
3170 struct il_priv *il = dev_get_drvdata(d);
3172 return sprintf(buf, "0x%04X\n", le32_to_cpu(il->active.filter_flags));
3179 struct il_priv *il = dev_get_drvdata(d);
3182 mutex_lock(&il->mutex);
3183 if (le32_to_cpu(il->staging.filter_flags) != filter_flags) {
3185 if (il_scan_cancel_timeout(il, 100))
3190 il->staging.filter_flags = cpu_to_le32(filter_flags);
3191 il3945_commit_rxon(il);
3194 mutex_unlock(&il->mutex);
3206 struct il_priv *il = dev_get_drvdata(d);
3212 spin_lock_irqsave(&il->lock, flags);
3213 if (!(il->measurement_status & MEASUREMENT_READY)) {
3214 spin_unlock_irqrestore(&il->lock, flags);
3217 memcpy(&measure_report, &il->measure_report, size);
3218 il->measurement_status = 0;
3219 spin_unlock_irqrestore(&il->lock, flags);
3239 struct il_priv *il = dev_get_drvdata(d);
3241 .channel = le16_to_cpu(il->active.channel),
3242 .start_time = cpu_to_le64(il->_3945.last_tsf),
3265 il3945_get_measurement(il, ¶ms, type);
3277 struct il_priv *il = dev_get_drvdata(d);
3279 il->retry_rate = simple_strtoul(buf, NULL, 0);
3280 if (il->retry_rate <= 0)
3281 il->retry_rate = 1;
3290 struct il_priv *il = dev_get_drvdata(d);
3291 return sprintf(buf, "%d", il->retry_rate);
3309 struct il_priv *il = dev_get_drvdata(d);
3311 if (!il_is_alive(il))
3321 struct il_priv *il __maybe_unused = dev_get_drvdata(d);
3346 struct il_priv *il = dev_get_drvdata(d);
3347 if (!il_is_alive(il))
3349 return sprintf(buf, "0x%08x\n", (int)il->status);
3358 struct il_priv *il = dev_get_drvdata(d);
3362 il3945_dump_nic_error_log(il);
3376 il3945_setup_deferred_work(struct il_priv *il)
3378 il->workqueue = create_singlethread_workqueue(DRV_NAME);
3379 if (!il->workqueue)
3382 init_waitqueue_head(&il->wait_command_queue);
3384 INIT_WORK(&il->restart, il3945_bg_restart);
3385 INIT_WORK(&il->rx_replenish, il3945_bg_rx_replenish);
3386 INIT_DELAYED_WORK(&il->init_alive_start, il3945_bg_init_alive_start);
3387 INIT_DELAYED_WORK(&il->alive_start, il3945_bg_alive_start);
3388 INIT_DELAYED_WORK(&il->_3945.rfkill_poll, il3945_rfkill_poll);
3390 il_setup_scan_deferred_work(il);
3392 il3945_hw_setup_deferred_work(il);
3394 timer_setup(&il->watchdog, il_bg_watchdog, 0);
3396 tasklet_setup(&il->irq_tasklet, il3945_irq_tasklet);
3402 il3945_cancel_deferred_work(struct il_priv *il)
3404 il3945_hw_cancel_deferred_work(il);
3406 cancel_delayed_work_sync(&il->init_alive_start);
3407 cancel_delayed_work(&il->alive_start);
3409 il_cancel_scan_deferred_work(il);
3460 il3945_init_drv(struct il_priv *il)
3463 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
3465 il->retry_rate = 1;
3466 il->beacon_skb = NULL;
3468 spin_lock_init(&il->sta_lock);
3469 spin_lock_init(&il->hcmd_lock);
3471 INIT_LIST_HEAD(&il->free_frames);
3473 mutex_init(&il->mutex);
3475 il->ieee_channels = NULL;
3476 il->ieee_rates = NULL;
3477 il->band = NL80211_BAND_2GHZ;
3479 il->iw_mode = NL80211_IFTYPE_STATION;
3480 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
3483 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
3491 ret = il_init_channel_map(il);
3498 if (il3945_txpower_set_from_eeprom(il)) {
3503 ret = il_init_geos(il);
3508 il3945_init_hw_rates(il, il->ieee_rates);
3513 il_free_channel_map(il);
3521 il3945_setup_mac(struct il_priv *il)
3524 struct ieee80211_hw *hw = il->hw;
3552 if (il->bands[NL80211_BAND_2GHZ].n_channels)
3553 il->hw->wiphy->bands[NL80211_BAND_2GHZ] =
3554 &il->bands[NL80211_BAND_2GHZ];
3556 if (il->bands[NL80211_BAND_5GHZ].n_channels)
3557 il->hw->wiphy->bands[NL80211_BAND_5GHZ] =
3558 &il->bands[NL80211_BAND_5GHZ];
3560 il_leds_init(il);
3562 wiphy_ext_feature_set(il->hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
3564 ret = ieee80211_register_hw(il->hw);
3569 il->mac80211_registered = 1;
3578 struct il_priv *il;
3593 il = hw->priv;
3594 il->hw = hw;
3597 il->cmd_queue = IL39_CMD_QUEUE_NUM;
3600 il->cfg = cfg;
3601 il->ops = &il3945_ops;
3603 il->debugfs_ops = &il3945_debugfs_ops;
3605 il->pci_dev = pdev;
3606 il->inta_mask = CSR_INI_SET_MASK;
3628 pci_set_drvdata(pdev, il);
3636 il->hw_base = pci_ioremap_bar(pdev, 0);
3637 if (!il->hw_base) {
3644 D_INFO("pci_resource_base = %p\n", il->hw_base);
3653 spin_lock_init(&il->reg_lock);
3654 spin_lock_init(&il->lock);
3661 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3668 err = il_eeprom_init(il);
3674 eeprom = (struct il3945_eeprom *)il->eeprom;
3676 SET_IEEE80211_PERM_ADDR(il->hw, eeprom->mac_address);
3682 err = il3945_hw_set_hw_params(il);
3689 * 6. Setup il
3692 err = il3945_init_drv(il);
3698 IL_INFO("Detected Intel Wireless WiFi Link %s\n", il->cfg->name);
3704 spin_lock_irqsave(&il->lock, flags);
3705 il_disable_interrupts(il);
3706 spin_unlock_irqrestore(&il->lock, flags);
3708 pci_enable_msi(il->pci_dev);
3710 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
3712 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
3722 il_set_rxon_channel(il, &il->bands[NL80211_BAND_2GHZ].channels[5]);
3723 err = il3945_setup_deferred_work(il);
3727 il3945_setup_handlers(il);
3728 il_power_initialize(il);
3734 il_enable_interrupts(il);
3736 err = il3945_setup_mac(il);
3740 il_dbgfs_register(il, DRV_NAME);
3743 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll, 2 * HZ);
3748 destroy_workqueue(il->workqueue);
3749 il->workqueue = NULL;
3753 free_irq(il->pci_dev->irq, il);
3755 pci_disable_msi(il->pci_dev);
3756 il_free_geos(il);
3757 il_free_channel_map(il);
3759 il3945_unset_hw_params(il);
3761 il_eeprom_free(il);
3763 iounmap(il->hw_base);
3769 ieee80211_free_hw(il->hw);
3777 struct il_priv *il = pci_get_drvdata(pdev);
3780 if (!il)
3785 il_dbgfs_unregister(il);
3787 set_bit(S_EXIT_PENDING, &il->status);
3789 il_leds_exit(il);
3791 if (il->mac80211_registered) {
3792 ieee80211_unregister_hw(il->hw);
3793 il->mac80211_registered = 0;
3795 il3945_down(il);
3805 il_apm_stop(il);
3810 spin_lock_irqsave(&il->lock, flags);
3811 il_disable_interrupts(il);
3812 spin_unlock_irqrestore(&il->lock, flags);
3814 il3945_synchronize_irq(il);
3818 cancel_delayed_work_sync(&il->_3945.rfkill_poll);
3820 il3945_dealloc_ucode_pci(il);
3822 if (il->rxq.bd)
3823 il3945_rx_queue_free(il, &il->rxq);
3824 il3945_hw_txq_ctx_free(il);
3826 il3945_unset_hw_params(il);
3831 * il->workqueue... so we can't take down the workqueue
3833 destroy_workqueue(il->workqueue);
3834 il->workqueue = NULL;
3836 free_irq(pdev->irq, il);
3839 iounmap(il->hw_base);
3843 il_free_channel_map(il);
3844 il_free_geos(il);
3845 kfree(il->scan_cmd);
3846 dev_kfree_skb(il->beacon_skb);
3847 ieee80211_free_hw(il->hw);