Lines Matching refs:pi
25 #define READ_RADIO_REG2(pi, radio_type, jspace, core, reg_name) \
26 read_radio_reg(pi, radio_type##_##jspace##_##reg_name | \
31 #define WRITE_RADIO_REG2(pi, radio_type, jspace, core, reg_name, value) \
32 write_radio_reg(pi, radio_type##_##jspace##_##reg_name | \
37 #define WRITE_RADIO_SYN(pi, radio_type, reg_name, value) \
38 write_radio_reg(pi, radio_type##_##SYN##_##reg_name, value)
40 #define READ_RADIO_REG3(pi, radio_type, jspace, core, reg_name) \
41 read_radio_reg(pi, ((core == PHY_CORE_0) ? \
45 #define WRITE_RADIO_REG3(pi, radio_type, jspace, core, reg_name, value) \
46 write_radio_reg(pi, ((core == PHY_CORE_0) ? \
51 #define READ_RADIO_REG4(pi, radio_type, jspace, core, reg_name) \
52 read_radio_reg(pi, ((core == PHY_CORE_0) ? \
56 #define WRITE_RADIO_REG4(pi, radio_type, jspace, core, reg_name, value) \
57 write_radio_reg(pi, ((core == PHY_CORE_0) ? \
97 #define NPHY_IS_SROM_REINTERPRET NREV_GE(pi->pubpi.phy_rev, 5)
256 #define wlc_phy_get_papd_nphy(pi) \
257 (read_phy_reg((pi), 0x1e7) & \
14113 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
14116 if (NREV_GE(pi->pubpi.phy_rev, 16))
14119 phybist0 = read_phy_reg(pi, 0x0e);
14120 phybist1 = read_phy_reg(pi, 0x0f);
14121 phybist2 = read_phy_reg(pi, 0xea);
14122 phybist3 = read_phy_reg(pi, 0xeb);
14123 phybist4 = read_phy_reg(pi, 0x156);
14132 static void wlc_phy_bphy_init_nphy(struct brcms_phy *pi)
14139 write_phy_reg(pi, addr, val);
14146 write_phy_reg(pi, NPHY_TO_BPHY_OFF + BPHY_STEP, 0x668);
14150 wlc_phy_table_write_nphy(struct brcms_phy *pi, u32 id, u32 len, u32 offset,
14160 wlc_phy_write_table_nphy(pi, &tbl);
14164 wlc_phy_table_read_nphy(struct brcms_phy *pi, u32 id, u32 len, u32 offset,
14174 wlc_phy_read_table_nphy(pi, &tbl);
14178 wlc_phy_static_table_download_nphy(struct brcms_phy *pi)
14182 if (NREV_GE(pi->pubpi.phy_rev, 16)) {
14184 wlc_phy_write_table_nphy(pi,
14186 } else if (NREV_GE(pi->pubpi.phy_rev, 7)) {
14188 wlc_phy_write_table_nphy(pi,
14190 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
14192 wlc_phy_write_table_nphy(pi,
14196 wlc_phy_write_table_nphy(pi,
14201 static void wlc_phy_tbl_init_nphy(struct brcms_phy *pi)
14206 if (pi->phy_init_por)
14207 wlc_phy_static_table_download_nphy(pi);
14209 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
14211 antswctrllut = CHSPEC_IS2G(pi->radio_chanspec) ?
14212 pi->srom_fem2g.antswctrllut : pi->srom_fem5g.
14222 if (pi->aa2g == 7)
14224 pi,
14230 pi,
14236 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
14239 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
14247 pi, NPHY_TBL_ID_ANTSWCTRLLUT,
14251 pi, NPHY_TBL_ID_ANTSWCTRLLUT,
14255 pi, NPHY_TBL_ID_ANTSWCTRLLUT,
14260 pi, NPHY_TBL_ID_ANTSWCTRLLUT,
14264 pi, NPHY_TBL_ID_ANTSWCTRLLUT,
14268 pi, NPHY_TBL_ID_ANTSWCTRLLUT,
14277 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
14282 CHSPEC_IS2G(pi->radio_chanspec) ?
14283 pi->srom_fem2g.antswctrllut :
14284 pi->srom_fem5g.antswctrllut;
14288 pi,
14294 pi,
14300 pi,
14306 pi,
14315 pi,
14321 wlc_phy_write_table_nphy(pi,
14328 wlc_phy_write_txmacreg_nphy(struct brcms_phy *pi, u16 holdoff, u16 delay)
14330 write_phy_reg(pi, 0x77, holdoff);
14331 write_phy_reg(pi, 0xb4, delay);
14334 void wlc_phy_nphy_tkip_rifs_war(struct brcms_phy *pi, u8 rifs)
14348 wlc_phy_write_txmacreg_nphy(pi, holdoff, delay);
14350 if (pi->sh && (pi->sh->_rifs_phy != rifs))
14351 pi->sh->_rifs_phy = rifs;
14354 static void wlc_phy_txpwrctrl_config_nphy(struct brcms_phy *pi)
14357 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
14358 pi->nphy_txpwrctrl = PHY_TPC_HW_ON;
14359 pi->phy_5g_pwrgain = true;
14363 pi->nphy_txpwrctrl = PHY_TPC_HW_OFF;
14364 pi->phy_5g_pwrgain = false;
14366 if ((pi->sh->boardflags2 & BFL2_TXPWRCTRL_EN) &&
14367 NREV_GE(pi->pubpi.phy_rev, 2) && (pi->sh->sromrev >= 4))
14368 pi->nphy_txpwrctrl = PHY_TPC_HW_ON;
14369 else if ((pi->sh->sromrev >= 4)
14370 && (pi->sh->boardflags2 & BFL2_5G_PWRGAIN))
14371 pi->phy_5g_pwrgain = true;
14374 static void wlc_phy_txpwr_srom_read_ppr_nphy(struct brcms_phy *pi)
14378 struct ssb_sprom *sprom = &pi->d11core->bus->sprom;
14380 if (pi->sh->sromrev >= 9)
14384 pi->bw402gpo = bw40po & 0xf;
14385 pi->bw405gpo = (bw40po & 0xf0) >> 4;
14386 pi->bw405glpo = (bw40po & 0xf00) >> 8;
14387 pi->bw405ghpo = (bw40po & 0xf000) >> 12;
14390 pi->cdd2gpo = cddpo & 0xf;
14391 pi->cdd5gpo = (cddpo & 0xf0) >> 4;
14392 pi->cdd5glpo = (cddpo & 0xf00) >> 8;
14393 pi->cdd5ghpo = (cddpo & 0xf000) >> 12;
14396 pi->stbc2gpo = stbcpo & 0xf;
14397 pi->stbc5gpo = (stbcpo & 0xf0) >> 4;
14398 pi->stbc5glpo = (stbcpo & 0xf00) >> 8;
14399 pi->stbc5ghpo = (stbcpo & 0xf000) >> 12;
14402 pi->bwdup2gpo = bwduppo & 0xf;
14403 pi->bwdup5gpo = (bwduppo & 0xf0) >> 4;
14404 pi->bwdup5glpo = (bwduppo & 0xf00) >> 8;
14405 pi->bwdup5ghpo = (bwduppo & 0xf000) >> 12;
14411 pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_2g =
14413 pi->nphy_pwrctrl_info[PHY_CORE_1].max_pwr_2g =
14415 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_a1 =
14417 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_a1 =
14419 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_b0 =
14421 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_b0 =
14423 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_b1 =
14425 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_b1 =
14427 pi->nphy_pwrctrl_info[PHY_CORE_0].idle_targ_2g =
14429 pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_2g =
14432 pi->cck2gpo = sprom->cck2gpo;
14434 pi->ofdm2gpo = sprom->ofdm2gpo;
14436 pi->mcs2gpo[0] = sprom->mcs2gpo[0];
14437 pi->mcs2gpo[1] = sprom->mcs2gpo[1];
14438 pi->mcs2gpo[2] = sprom->mcs2gpo[2];
14439 pi->mcs2gpo[3] = sprom->mcs2gpo[3];
14440 pi->mcs2gpo[4] = sprom->mcs2gpo[4];
14441 pi->mcs2gpo[5] = sprom->mcs2gpo[5];
14442 pi->mcs2gpo[6] = sprom->mcs2gpo[6];
14443 pi->mcs2gpo[7] = sprom->mcs2gpo[7];
14447 pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_5gm =
14449 pi->nphy_pwrctrl_info[PHY_CORE_1].max_pwr_5gm =
14451 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_a1 =
14453 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_a1 =
14455 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_b0 =
14457 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_b0 =
14459 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_b1 =
14461 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_b1 =
14463 pi->nphy_pwrctrl_info[PHY_CORE_0].idle_targ_5gm =
14465 pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_5gm =
14468 pi->ofdm5gpo = sprom->ofdm5gpo;
14470 pi->mcs5gpo[0] = sprom->mcs5gpo[0];
14471 pi->mcs5gpo[1] = sprom->mcs5gpo[1];
14472 pi->mcs5gpo[2] = sprom->mcs5gpo[2];
14473 pi->mcs5gpo[3] = sprom->mcs5gpo[3];
14474 pi->mcs5gpo[4] = sprom->mcs5gpo[4];
14475 pi->mcs5gpo[5] = sprom->mcs5gpo[5];
14476 pi->mcs5gpo[6] = sprom->mcs5gpo[6];
14477 pi->mcs5gpo[7] = sprom->mcs5gpo[7];
14481 pi->nphy_pwrctrl_info[0].max_pwr_5gl =
14483 pi->nphy_pwrctrl_info[1].max_pwr_5gl =
14485 pi->nphy_pwrctrl_info[0].pwrdet_5gl_a1 =
14487 pi->nphy_pwrctrl_info[1].pwrdet_5gl_a1 =
14489 pi->nphy_pwrctrl_info[0].pwrdet_5gl_b0 =
14491 pi->nphy_pwrctrl_info[1].pwrdet_5gl_b0 =
14493 pi->nphy_pwrctrl_info[0].pwrdet_5gl_b1 =
14495 pi->nphy_pwrctrl_info[1].pwrdet_5gl_b1 =
14497 pi->nphy_pwrctrl_info[0].idle_targ_5gl = 0;
14498 pi->nphy_pwrctrl_info[1].idle_targ_5gl = 0;
14500 pi->ofdm5glpo = sprom->ofdm5glpo;
14502 pi->mcs5glpo[0] = sprom->mcs5glpo[0];
14503 pi->mcs5glpo[1] = sprom->mcs5glpo[1];
14504 pi->mcs5glpo[2] = sprom->mcs5glpo[2];
14505 pi->mcs5glpo[3] = sprom->mcs5glpo[3];
14506 pi->mcs5glpo[4] = sprom->mcs5glpo[4];
14507 pi->mcs5glpo[5] = sprom->mcs5glpo[5];
14508 pi->mcs5glpo[6] = sprom->mcs5glpo[6];
14509 pi->mcs5glpo[7] = sprom->mcs5glpo[7];
14513 pi->nphy_pwrctrl_info[0].max_pwr_5gh =
14515 pi->nphy_pwrctrl_info[1].max_pwr_5gh =
14517 pi->nphy_pwrctrl_info[0].pwrdet_5gh_a1 =
14519 pi->nphy_pwrctrl_info[1].pwrdet_5gh_a1 =
14521 pi->nphy_pwrctrl_info[0].pwrdet_5gh_b0 =
14523 pi->nphy_pwrctrl_info[1].pwrdet_5gh_b0 =
14525 pi->nphy_pwrctrl_info[0].pwrdet_5gh_b1 =
14527 pi->nphy_pwrctrl_info[1].pwrdet_5gh_b1 =
14529 pi->nphy_pwrctrl_info[0].idle_targ_5gh = 0;
14530 pi->nphy_pwrctrl_info[1].idle_targ_5gh = 0;
14532 pi->ofdm5ghpo = sprom->ofdm5ghpo;
14534 pi->mcs5ghpo[0] = sprom->mcs5ghpo[0];
14535 pi->mcs5ghpo[1] = sprom->mcs5ghpo[1];
14536 pi->mcs5ghpo[2] = sprom->mcs5ghpo[2];
14537 pi->mcs5ghpo[3] = sprom->mcs5ghpo[3];
14538 pi->mcs5ghpo[4] = sprom->mcs5ghpo[4];
14539 pi->mcs5ghpo[5] = sprom->mcs5ghpo[5];
14540 pi->mcs5ghpo[6] = sprom->mcs5ghpo[6];
14541 pi->mcs5ghpo[7] = sprom->mcs5ghpo[7];
14546 wlc_phy_txpwr_apply_nphy(pi);
14549 static void wlc_phy_txpwr_srom_read_nphy(struct brcms_phy *pi)
14551 struct ssb_sprom *sprom = &pi->d11core->bus->sprom;
14553 pi->antswitch = sprom->antswitch;
14554 pi->aa2g = sprom->ant_available_bg;
14555 pi->aa5g = sprom->ant_available_a;
14557 pi->srom_fem2g.tssipos = sprom->fem.ghz2.tssipos;
14558 pi->srom_fem2g.extpagain = sprom->fem.ghz2.extpa_gain;
14559 pi->srom_fem2g.pdetrange = sprom->fem.ghz2.pdet_range;
14560 pi->srom_fem2g.triso = sprom->fem.ghz2.tr_iso;
14561 pi->srom_fem2g.antswctrllut = sprom->fem.ghz2.antswlut;
14563 pi->srom_fem5g.tssipos = sprom->fem.ghz5.tssipos;
14564 pi->srom_fem5g.extpagain = sprom->fem.ghz5.extpa_gain;
14565 pi->srom_fem5g.pdetrange = sprom->fem.ghz5.pdet_range;
14566 pi->srom_fem5g.triso = sprom->fem.ghz5.tr_iso;
14568 pi->srom_fem5g.antswctrllut = sprom->fem.ghz5.antswlut;
14570 pi->srom_fem5g.antswctrllut = sprom->fem.ghz2.antswlut;
14572 wlc_phy_txpower_ipa_upd(pi);
14574 pi->phy_txcore_disable_temp = sprom->tempthresh;
14575 if (pi->phy_txcore_disable_temp == 0)
14576 pi->phy_txcore_disable_temp = PHY_CHAIN_TX_DISABLE_TEMP;
14578 pi->phy_tempsense_offset = sprom->tempoffset;
14579 if (pi->phy_tempsense_offset != 0) {
14580 if (pi->phy_tempsense_offset >
14582 pi->phy_tempsense_offset = NPHY_SROM_MAXTEMPOFFSET;
14583 else if (pi->phy_tempsense_offset < (NPHY_SROM_TEMPSHIFT +
14585 pi->phy_tempsense_offset = NPHY_SROM_MINTEMPOFFSET;
14587 pi->phy_tempsense_offset -= NPHY_SROM_TEMPSHIFT;
14590 pi->phy_txcore_enable_temp =
14591 pi->phy_txcore_disable_temp - PHY_HYSTERESIS_DELTATEMP;
14593 pi->phycal_tempdelta = sprom->phycal_tempdelta;
14594 if (pi->phycal_tempdelta > NPHY_CAL_MAXTEMPDELTA)
14595 pi->phycal_tempdelta = 0;
14597 wlc_phy_txpwr_srom_read_ppr_nphy(pi);
14600 void wlc_phy_attach_nphy(struct brcms_phy *pi)
14604 if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 6))
14605 pi->phyhang_avoid = true;
14607 if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 7)) {
14608 pi->nphy_gband_spurwar_en = true;
14609 if (pi->sh->boardflags2 & BFL2_SPUR_WAR)
14610 pi->nphy_aband_spurwar_en = true;
14612 if (NREV_GE(pi->pubpi.phy_rev, 6) && NREV_LT(pi->pubpi.phy_rev, 7)) {
14613 if (pi->sh->boardflags2 & BFL2_2G_SPUR_WAR)
14614 pi->nphy_gband_spurwar2_en = true;
14617 pi->n_preamble_override = AUTO;
14618 if (NREV_IS(pi->pubpi.phy_rev, 3) || NREV_IS(pi->pubpi.phy_rev, 4))
14619 pi->n_preamble_override = BRCMS_N_PREAMBLE_MIXEDMODE;
14621 pi->nphy_txrx_chain = AUTO;
14622 pi->phy_scraminit = AUTO;
14624 pi->nphy_rxcalparams = 0x010100B5;
14626 pi->nphy_perical = PHY_PERICAL_MPHASE;
14627 pi->mphase_cal_phase_id = MPHASE_CAL_STATE_IDLE;
14628 pi->mphase_txcal_numcmds = MPHASE_TXCAL_NUMCMDS;
14630 pi->nphy_gain_boost = true;
14631 pi->nphy_elna_gain_config = false;
14632 pi->radio_is_on = false;
14634 for (i = 0; i < pi->pubpi.phy_corenum; i++)
14635 pi->nphy_txpwrindex[i].index = AUTO;
14637 wlc_phy_txpwrctrl_config_nphy(pi);
14638 if (pi->nphy_txpwrctrl == PHY_TPC_HW_ON)
14639 pi->hwpwrctrl_capable = true;
14641 pi->pi_fptr.init = wlc_phy_init_nphy;
14642 pi->pi_fptr.calinit = wlc_phy_cal_init_nphy;
14643 pi->pi_fptr.chanset = wlc_phy_chanspec_set_nphy;
14644 pi->pi_fptr.txpwrrecalc = wlc_phy_txpower_recalc_target_nphy;
14646 wlc_phy_txpwr_srom_read_nphy(pi);
14649 static s32 get_rf_pwr_offset(struct brcms_phy *pi, s16 pga_gn, s16 pad_gn)
14653 if (CHSPEC_IS2G(pi->radio_chanspec)) {
14654 if ((pi->pubpi.radiorev == 3) ||
14655 (pi->pubpi.radiorev == 4) ||
14656 (pi->pubpi.radiorev == 6))
14660 else if (pi->pubpi.radiorev == 5)
14664 else if ((pi->pubpi.radiorev == 7)
14665 || (pi->pubpi.radiorev ==
14671 if ((pi->pubpi.radiorev == 3) ||
14672 (pi->pubpi.radiorev == 4) ||
14673 (pi->pubpi.radiorev == 6))
14677 else if ((pi->pubpi.radiorev == 7)
14678 || (pi->pubpi.radiorev ==
14687 static void wlc_phy_update_mimoconfig_nphy(struct brcms_phy *pi, s32 preamble)
14695 val = read_phy_reg(pi, 0xed);
14702 write_phy_reg(pi, 0xed, val);
14705 static void wlc_phy_ipa_set_tx_digi_filts_nphy(struct brcms_phy *pi)
14712 write_phy_reg(pi, addr_offset[type] + j,
14716 if (pi->bw == WL_CHANSPEC_BW_40) {
14718 write_phy_reg(pi, 0x186 + j,
14721 if (CHSPEC_IS5G(pi->radio_chanspec)) {
14723 write_phy_reg(pi, 0x186 + j,
14727 if (CHSPEC_CHANNEL(pi->radio_chanspec) == 14) {
14729 write_phy_reg(pi, 0x2c5 + j,
14735 static void wlc_phy_ipa_restore_tx_digi_filts_nphy(struct brcms_phy *pi)
14739 if (pi->bw == WL_CHANSPEC_BW_40) {
14741 write_phy_reg(pi, 0x195 + j,
14745 write_phy_reg(pi, 0x186 + j,
14751 wlc_phy_set_rfseq_nphy(struct brcms_phy *pi, u8 cmd, const u8 *events,
14757 NREV_GE(pi->pubpi.phy_rev,
14761 if (pi->phyhang_avoid)
14762 wlc_phy_stay_in_carriersearch_nphy(pi, true);
14765 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, len, t1_offset, 8,
14768 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, len, t2_offset, 8,
14772 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
14774 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
14778 if (pi->phyhang_avoid)
14779 wlc_phy_stay_in_carriersearch_nphy(pi, false);
14782 static u16 wlc_phy_read_lpf_bw_ctl_nphy(struct brcms_phy *pi, u16 offset)
14788 if (CHSPEC_IS40(pi->radio_chanspec))
14795 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
14805 wlc_phy_rfctrl_override_nphy_rev7(struct brcms_phy *pi, u16 field, u16 value,
14812 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
15056 and_phy_reg(pi, en_addr, ~en_mask);
15057 and_phy_reg(pi, val_addr, ~val_mask);
15062 or_phy_reg(pi, en_addr, en_mask);
15065 mod_phy_reg(pi, val_addr,
15075 static void wlc_phy_adjust_lnagaintbl_nphy(struct brcms_phy *pi)
15084 if (pi->phyhang_avoid)
15085 wlc_phy_stay_in_carriersearch_nphy(pi, true);
15087 if (pi->nphy_gain_boost) {
15088 if ((CHSPEC_IS2G(pi->radio_chanspec))) {
15094 curr_channel = CHSPEC_CHANNEL(pi->radio_chanspec);
15112 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
15113 if (pi->nphy_elna_gain_config) {
15125 wlc_phy_table_write_nphy(pi, core, 4, 8, 16, regval);
15131 mod_phy_reg(pi, 0x1e, (0xff << 0), (minmax_gain[0] << 0));
15132 mod_phy_reg(pi, 0x34, (0xff << 0), (minmax_gain[1] << 0));
15134 if (pi->phyhang_avoid)
15135 wlc_phy_stay_in_carriersearch_nphy(pi, false);
15139 wlc_phy_war_force_trsw_to_R_cliplo_nphy(struct brcms_phy *pi, u8 core)
15142 write_phy_reg(pi, 0x38, 0x4);
15143 if (CHSPEC_IS2G(pi->radio_chanspec))
15144 write_phy_reg(pi, 0x37, 0x0060);
15146 write_phy_reg(pi, 0x37, 0x1080);
15148 write_phy_reg(pi, 0x2ae, 0x4);
15149 if (CHSPEC_IS2G(pi->radio_chanspec))
15150 write_phy_reg(pi, 0x2ad, 0x0060);
15152 write_phy_reg(pi, 0x2ad, 0x1080);
15156 static void wlc_phy_war_txchain_upd_nphy(struct brcms_phy *pi, u8 txchain)
15163 wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, PHY_CORE_0);
15166 wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, PHY_CORE_1);
15169 static void wlc_phy_workarounds_nphy_gainctrl_2057_rev5(struct brcms_phy *pi)
15177 mod_phy_reg(pi, 0x1c, (0x1 << 13), (1 << 13));
15178 mod_phy_reg(pi, 0x32, (0x1 << 13), (1 << 13));
15180 mod_phy_reg(pi, 0x289, (0xff << 0), (0x46 << 0));
15182 mod_phy_reg(pi, 0x283, (0xff << 0), (0x3c << 0));
15183 mod_phy_reg(pi, 0x280, (0xff << 0), (0x3c << 0));
15185 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 0x8, 8,
15187 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 0x8, 8,
15190 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 0x10, 8,
15192 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 0x10, 8,
15195 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 10, 0x20, 8,
15197 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 10, 0x20, 8,
15200 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS1, 10, 0x20, 8,
15202 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS2, 10, 0x20, 8,
15205 write_phy_reg(pi, 0x37, 0x74);
15206 write_phy_reg(pi, 0x2ad, 0x74);
15207 write_phy_reg(pi, 0x38, 0x18);
15208 write_phy_reg(pi, 0x2ae, 0x18);
15210 write_phy_reg(pi, 0x2b, 0xe8);
15211 write_phy_reg(pi, 0x41, 0xe8);
15213 if (CHSPEC_IS20(pi->radio_chanspec)) {
15215 mod_phy_reg(pi, 0x300, (0x3f << 0), (0x12 << 0));
15216 mod_phy_reg(pi, 0x301, (0x3f << 0), (0x12 << 0));
15219 mod_phy_reg(pi, 0x300, (0x3f << 0), (0x10 << 0));
15220 mod_phy_reg(pi, 0x301, (0x3f << 0), (0x10 << 0));
15224 static void wlc_phy_workarounds_nphy_gainctrl_2057_rev6(struct brcms_phy *pi)
15251 mod_phy_reg(pi, 0x1c, (0x1 << 13), (1 << 13));
15252 mod_phy_reg(pi, 0x32, (0x1 << 13), (1 << 13));
15254 currband = read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand;
15259 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 8, 8,
15261 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 8, 8,
15264 mod_phy_reg(pi, 0x283, (0xff << 0), (0x40 << 0));
15266 if (CHSPEC_IS40(pi->radio_chanspec)) {
15267 mod_phy_reg(pi, 0x280, (0xff << 0), (0x3e << 0));
15268 mod_phy_reg(pi, 0x283, (0xff << 0), (0x3e << 0));
15271 mod_phy_reg(pi, 0x289, (0xff << 0), (0x46 << 0));
15273 if (CHSPEC_IS20(pi->radio_chanspec)) {
15274 mod_phy_reg(pi, 0x300, (0x3f << 0), (13 << 0));
15275 mod_phy_reg(pi, 0x301, (0x3f << 0), (13 << 0));
15289 freq = CHAN5G_FREQ(CHSPEC_CHANNEL(pi->radio_chanspec));
15290 if (CHSPEC_IS20(pi->radio_chanspec)) {
15361 write_phy_reg(pi, 0x20, init_gaincode);
15362 write_phy_reg(pi, 0x2a7, init_gaincode);
15364 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
15365 pi->pubpi.phy_corenum, 0x106, 16,
15368 write_phy_reg(pi, 0x22, clip1hi_gaincode);
15369 write_phy_reg(pi, 0x2a9, clip1hi_gaincode);
15371 write_phy_reg(pi, 0x36, clip1md_gaincode_B);
15372 write_phy_reg(pi, 0x2ac, clip1md_gaincode_B);
15374 write_phy_reg(pi, 0x37, clip1lo_gaincode);
15375 write_phy_reg(pi, 0x2ad, clip1lo_gaincode);
15376 write_phy_reg(pi, 0x38, clip1lo_gaincode_B);
15377 write_phy_reg(pi, 0x2ae, clip1lo_gaincode_B);
15379 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 10, 0x20, 8,
15381 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 10, 0x20, 8,
15384 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS1, 10, 0x20, 8,
15386 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS2, 10, 0x20, 8,
15389 mod_phy_reg(pi, 0x283, (0xff << 0), (crsminu_th << 0));
15392 write_phy_reg(pi, 0x2b, nbclip_th);
15393 write_phy_reg(pi, 0x41, nbclip_th);
15396 mod_phy_reg(pi, 0x300, (0x3f << 0), (w1clip_th << 0));
15397 mod_phy_reg(pi, 0x301, (0x3f << 0), (w1clip_th << 0));
15399 mod_phy_reg(pi, 0x2e4,
15402 mod_phy_reg(pi, 0x2e4,
15405 if (CHSPEC_IS20(pi->radio_chanspec)) {
15407 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 8, 8,
15409 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 8, 8,
15412 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 0x10,
15414 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 0x10,
15417 write_phy_reg(pi, 0x24, clip1md_gaincode);
15418 write_phy_reg(pi, 0x2ab, clip1md_gaincode);
15420 mod_phy_reg(pi, 0x280, (0xff << 0), (crsminl_th << 0));
15425 static void wlc_phy_workarounds_nphy_gainctrl(struct brcms_phy *pi)
15580 triso = (CHSPEC_IS5G(pi->radio_chanspec)) ? pi->srom_fem5g.triso :
15581 pi->srom_fem2g.triso;
15583 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
15584 if (pi->pubpi.radiorev == 5) {
15585 wlc_phy_workarounds_nphy_gainctrl_2057_rev5(pi);
15586 } else if (pi->pubpi.radiorev == 7) {
15587 wlc_phy_workarounds_nphy_gainctrl_2057_rev6(pi);
15589 mod_phy_reg(pi, 0x283, (0xff << 0), (0x44 << 0));
15590 mod_phy_reg(pi, 0x280, (0xff << 0), (0x44 << 0));
15592 } else if ((pi->pubpi.radiorev == 3)
15593 || (pi->pubpi.radiorev == 8)) {
15594 wlc_phy_workarounds_nphy_gainctrl_2057_rev6(pi);
15596 if (pi->pubpi.radiorev == 8) {
15597 mod_phy_reg(pi, 0x283,
15599 mod_phy_reg(pi, 0x280,
15603 wlc_phy_workarounds_nphy_gainctrl_2057_rev6(pi);
15605 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
15607 mod_phy_reg(pi, 0xa0, (0x1 << 6), (1 << 6));
15609 mod_phy_reg(pi, 0x1c, (0x1 << 13), (1 << 13));
15610 mod_phy_reg(pi, 0x32, (0x1 << 13), (1 << 13));
15613 read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand;
15615 if (NREV_GE(pi->pubpi.phy_rev, 6)) {
15616 if (pi->pubpi.radiorev == 11) {
15636 if (pi->sh->boardflags & BFL_EXTLNA) {
15701 } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
15704 if (pi->sh->boardflags & BFL_EXTLNA) {
15760 } else if (NREV_IS(pi->pubpi.phy_rev, 4)) {
15791 if (NREV_GE(pi->pubpi.phy_rev, 6)) {
15803 if ((pi->pubpi.radiorev == 11) &&
15804 (CHSPEC_IS40(pi->radio_chanspec) == 0))
15811 } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
15826 } else if (NREV_IS(pi->pubpi.phy_rev, 4)) {
15831 if (pi->sh->boardflags & BFL_EXTLNA_5GHz) {
15868 write_radio_reg(pi,
15871 write_radio_reg(pi,
15875 write_radio_reg(pi, (RADIO_2056_RX_LNAG2_IDAC | RADIO_2056_RX0),
15877 write_radio_reg(pi, (RADIO_2056_RX_LNAG2_IDAC | RADIO_2056_RX1),
15880 write_radio_reg(pi, (RADIO_2056_RX_RSSI_POLE | RADIO_2056_RX0),
15882 write_radio_reg(pi, (RADIO_2056_RX_RSSI_POLE | RADIO_2056_RX1),
15885 write_radio_reg(pi, (RADIO_2056_RX_RSSI_GAIN | RADIO_2056_RX0),
15887 write_radio_reg(pi, (RADIO_2056_RX_RSSI_GAIN | RADIO_2056_RX1),
15890 write_radio_reg(pi,
15893 write_radio_reg(pi,
15897 write_radio_reg(pi, (RADIO_2056_RX_LNAA2_IDAC | RADIO_2056_RX0),
15899 write_radio_reg(pi, (RADIO_2056_RX_LNAA2_IDAC | RADIO_2056_RX1),
15902 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 8,
15904 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 8,
15907 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 0x10,
15909 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 0x10,
15912 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 10, 0x20,
15914 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 10, 0x20,
15917 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS1, 10, 0x20,
15919 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS2, 10, 0x20,
15922 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 6, 0x40,
15924 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 6, 0x40,
15926 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS1, 6, 0x40,
15928 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS2, 6, 0x40,
15931 write_phy_reg(pi, 0x20, init_gaincode);
15932 write_phy_reg(pi, 0x2a7, init_gaincode);
15934 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
15935 pi->pubpi.phy_corenum, 0x106, 16,
15938 write_phy_reg(pi, 0x22, clip1hi_gaincode);
15939 write_phy_reg(pi, 0x2a9, clip1hi_gaincode);
15941 write_phy_reg(pi, 0x24, clip1md_gaincode);
15942 write_phy_reg(pi, 0x2ab, clip1md_gaincode);
15944 write_phy_reg(pi, 0x37, clip1lo_gaincode);
15945 write_phy_reg(pi, 0x2ad, clip1lo_gaincode);
15947 mod_phy_reg(pi, 0x27d, (0xff << 0), (crsmin_th << 0));
15948 mod_phy_reg(pi, 0x280, (0xff << 0), (crsminl_th << 0));
15949 mod_phy_reg(pi, 0x283, (0xff << 0), (crsminu_th << 0));
15951 write_phy_reg(pi, 0x2b, nbclip_th);
15952 write_phy_reg(pi, 0x41, nbclip_th);
15954 mod_phy_reg(pi, 0x27, (0x3f << 0), (w1clip_th << 0));
15955 mod_phy_reg(pi, 0x3d, (0x3f << 0), (w1clip_th << 0));
15957 write_phy_reg(pi, 0x150, 0x809c);
15961 mod_phy_reg(pi, 0x1c, (0x1 << 13), (1 << 13));
15962 mod_phy_reg(pi, 0x32, (0x1 << 13), (1 << 13));
15964 write_phy_reg(pi, 0x2b, 0x84);
15965 write_phy_reg(pi, 0x41, 0x84);
15967 if (CHSPEC_IS20(pi->radio_chanspec)) {
15968 write_phy_reg(pi, 0x6b, 0x2b);
15969 write_phy_reg(pi, 0x6c, 0x2b);
15970 write_phy_reg(pi, 0x6d, 0x9);
15971 write_phy_reg(pi, 0x6e, 0x9);
15975 mod_phy_reg(pi, 0x27, (0x3f << 0), (w1th << 0));
15976 mod_phy_reg(pi, 0x3d, (0x3f << 0), (w1th << 0));
15978 if (CHSPEC_IS20(pi->radio_chanspec)) {
15979 mod_phy_reg(pi, 0x1c, (0x1f << 0), (0x1 << 0));
15980 mod_phy_reg(pi, 0x32, (0x1f << 0), (0x1 << 0));
15982 mod_phy_reg(pi, 0x1d, (0x1f << 0), (0x1 << 0));
15983 mod_phy_reg(pi, 0x33, (0x1f << 0), (0x1 << 0));
15986 write_phy_reg(pi, 0x150, 0x809c);
15988 if (pi->nphy_gain_boost)
15989 if ((CHSPEC_IS2G(pi->radio_chanspec)) &&
15990 (CHSPEC_IS40(pi->radio_chanspec)))
15994 else if (CHSPEC_IS40(pi->radio_chanspec))
15999 mod_phy_reg(pi, 0x20, (0x1f << 7), (hpf_code << 7));
16000 mod_phy_reg(pi, 0x36, (0x1f << 7), (hpf_code << 7));
16004 wlc_phy_table_write_nphy(pi, 7, 4, 0x106, 16, regval);
16006 wlc_phy_adjust_lnagaintbl_nphy(pi);
16008 if (pi->nphy_elna_gain_config) {
16013 wlc_phy_table_write_nphy(pi, 2, 4, 8, 16, regval);
16014 wlc_phy_table_write_nphy(pi, 3, 4, 8, 16, regval);
16018 wlc_phy_table_write_nphy(pi, 7, 4, 0x106, 16, regval);
16021 if (NREV_IS(pi->pubpi.phy_rev, 2)) {
16024 wlc_phy_table_write_nphy(pi, 0, 21, 32, 16, regval);
16025 wlc_phy_table_write_nphy(pi, 1, 21, 32, 16, regval);
16029 wlc_phy_table_write_nphy(pi, 2, 21, 32, 16, regval);
16030 wlc_phy_table_write_nphy(pi, 3, 21, 32, 16, regval);
16033 wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_UPDATEGAINU,
16038 mod_phy_reg(pi, 0x153, (0xff << 8), (90 << 8));
16040 if (CHSPEC_IS2G(pi->radio_chanspec))
16041 mod_phy_reg(pi,
16047 static void wlc_phy_workarounds_nphy_rev7(struct brcms_phy *pi)
16101 if (NREV_IS(pi->pubpi.phy_rev, 7)) {
16102 mod_phy_reg(pi, 0x221, (0x1 << 4), (1 << 4));
16104 mod_phy_reg(pi, 0x160, (0x7f << 0), (32 << 0));
16105 mod_phy_reg(pi, 0x160, (0x7f << 8), (39 << 8));
16106 mod_phy_reg(pi, 0x161, (0x7f << 0), (46 << 0));
16107 mod_phy_reg(pi, 0x161, (0x7f << 8), (51 << 8));
16108 mod_phy_reg(pi, 0x162, (0x7f << 0), (55 << 0));
16109 mod_phy_reg(pi, 0x162, (0x7f << 8), (58 << 8));
16110 mod_phy_reg(pi, 0x163, (0x7f << 0), (60 << 0));
16111 mod_phy_reg(pi, 0x163, (0x7f << 8), (62 << 8));
16112 mod_phy_reg(pi, 0x164, (0x7f << 0), (62 << 0));
16113 mod_phy_reg(pi, 0x164, (0x7f << 8), (63 << 8));
16114 mod_phy_reg(pi, 0x165, (0x7f << 0), (63 << 0));
16115 mod_phy_reg(pi, 0x165, (0x7f << 8), (64 << 8));
16116 mod_phy_reg(pi, 0x166, (0x7f << 0), (64 << 0));
16117 mod_phy_reg(pi, 0x166, (0x7f << 8), (64 << 8));
16118 mod_phy_reg(pi, 0x167, (0x7f << 0), (64 << 0));
16119 mod_phy_reg(pi, 0x167, (0x7f << 8), (64 << 8));
16122 if (NREV_LE(pi->pubpi.phy_rev, 8)) {
16123 write_phy_reg(pi, 0x23f, 0x1b0);
16124 write_phy_reg(pi, 0x240, 0x1b0);
16127 if (NREV_GE(pi->pubpi.phy_rev, 8))
16128 mod_phy_reg(pi, 0xbd, (0xff << 0), (114 << 0));
16130 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x00, 16,
16132 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x10, 16,
16135 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
16138 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
16141 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
16143 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x16e, 16,
16146 if (PHY_IPA(pi))
16147 wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX,
16153 mod_phy_reg(pi, 0x299, (0x3 << 14), (0x1 << 14));
16154 mod_phy_reg(pi, 0x29d, (0x3 << 14), (0x1 << 14));
16156 tx_lpf_bw_ofdm_20mhz = wlc_phy_read_lpf_bw_ctl_nphy(pi, 0x154);
16157 tx_lpf_bw_ofdm_40mhz = wlc_phy_read_lpf_bw_ctl_nphy(pi, 0x159);
16158 tx_lpf_bw_11b = wlc_phy_read_lpf_bw_ctl_nphy(pi, 0x152);
16160 if (PHY_IPA(pi)) {
16162 if (((pi->pubpi.radiorev == 5)
16163 && (CHSPEC_IS40(pi->radio_chanspec) == 1))
16164 || (pi->pubpi.radiorev == 7)
16165 || (pi->pubpi.radiorev == 8)) {
16168 read_radio_reg(pi, RADIO_2057_RCCAL_BCAP_VAL);
16170 read_radio_reg(pi, RADIO_2057_RCCAL_SCAP_VAL);
16175 if ((pi->pubpi.radiorev == 5) &&
16176 (CHSPEC_IS40(pi->radio_chanspec) == 1)) {
16185 } else if ((pi->pubpi.radiorev == 7)
16186 || (pi->pubpi.radiorev == 8)) {
16191 if (CHSPEC_IS2G(pi->radio_chanspec)) {
16209 if (pi->pubpi.radiorev == 5) {
16215 read_radio_reg(pi, RADIO_2057_RCCAL_BCAP_VAL);
16217 read_radio_reg(pi, RADIO_2057_RCCAL_SCAP_VAL);
16244 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
16247 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
16250 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
16253 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
16256 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
16259 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
16262 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
16265 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
16270 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 4), 1, 0x3, 0,
16274 write_phy_reg(pi, 0x32f, 0x3);
16276 if ((pi->pubpi.radiorev == 4) || (pi->pubpi.radiorev == 6))
16277 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2), 1, 0x3, 0,
16280 if ((pi->pubpi.radiorev == 3) || (pi->pubpi.radiorev == 4) ||
16281 (pi->pubpi.radiorev == 6)) {
16282 if ((pi->sh->sromrev >= 8)
16283 && (pi->sh->boardflags2 & BFL2_IPALVLSHIFT_3P3))
16287 write_radio_reg(pi, RADIO_2057_GPAIO_CONFIG, 0x5);
16288 write_radio_reg(pi, RADIO_2057_GPAIO_SEL1, 0x30);
16289 write_radio_reg(pi, RADIO_2057_GPAIO_SEL0, 0x0);
16290 or_radio_reg(pi, RADIO_2057_RXTXBIAS_CONFIG_CORE0, 0x1);
16291 or_radio_reg(pi, RADIO_2057_RXTXBIAS_CONFIG_CORE1, 0x1);
16307 if (CHSPEC_IS2G(pi->radio_chanspec)) {
16309 WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
16312 WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
16315 WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
16323 if (PHY_IPA(pi)) {
16324 if (CHSPEC_IS2G(pi->radio_chanspec)) {
16325 if ((pi->pubpi.radiorev == 3)
16326 || (pi->pubpi.radiorev == 4)
16327 || (pi->pubpi.radiorev == 6))
16332 WRITE_RADIO_REG4(pi, RADIO_2057,
16338 if (pi->pubpi.radiorev == 5) {
16340 WRITE_RADIO_REG4(pi, RADIO_2057,
16344 WRITE_RADIO_REG4(pi, RADIO_2057,
16348 WRITE_RADIO_REG4(pi, RADIO_2057,
16352 WRITE_RADIO_REG4(pi, RADIO_2057,
16356 WRITE_RADIO_REG4(pi, RADIO_2057,
16361 } else if ((pi->pubpi.radiorev == 7) ||
16362 (pi->pubpi.radiorev == 8)) {
16364 if (CHSPEC_IS40(pi->radio_chanspec) == 0) {
16365 WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
16367 WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
16370 WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
16372 WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
16380 (pi->radio_chanspec));
16383 WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
16385 WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
16391 if (pi->pubpi.radiorev != 5) {
16393 WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
16395 WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
16401 if (pi->pubpi.radiorev == 4) {
16402 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x05, 16,
16404 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x15, 16,
16408 WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
16410 WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
16412 WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
16416 mod_phy_reg(pi, 0xa6, (0x1 << 2), (0x1 << 2));
16417 mod_phy_reg(pi, 0x8f, (0x1 << 2), (0x1 << 2));
16418 mod_phy_reg(pi, 0xa7, (0x1 << 2), (0x1 << 2));
16419 mod_phy_reg(pi, 0xa5, (0x1 << 2), (0x1 << 2));
16421 mod_phy_reg(pi, 0xa6, (0x1 << 0), 0);
16422 mod_phy_reg(pi, 0x8f, (0x1 << 0), (0x1 << 0));
16423 mod_phy_reg(pi, 0xa7, (0x1 << 0), 0);
16424 mod_phy_reg(pi, 0xa5, (0x1 << 0), (0x1 << 0));
16426 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x05, 16,
16428 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x15, 16,
16431 mod_phy_reg(pi, 0xa6, (0x1 << 2), 0);
16432 mod_phy_reg(pi, 0x8f, (0x1 << 2), 0);
16433 mod_phy_reg(pi, 0xa7, (0x1 << 2), 0);
16434 mod_phy_reg(pi, 0xa5, (0x1 << 2), 0);
16437 write_phy_reg(pi, 0x6a, 0x2);
16439 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 256, 32,
16442 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x138, 16,
16445 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1, 0x141, 16,
16448 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 3, 0x133, 16,
16451 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x146, 16,
16454 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1, 0x123, 16,
16457 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1, 0x12A, 16,
16460 if (CHSPEC_IS40(pi->radio_chanspec) == 0) {
16461 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 3,
16463 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
16467 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 3,
16471 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
16475 wlc_phy_workarounds_nphy_gainctrl(pi);
16477 pdetrange = (CHSPEC_IS5G(pi->radio_chanspec)) ?
16478 pi->srom_fem5g.pdetrange : pi->srom_fem2g.pdetrange;
16481 chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0);
16502 if (pi->pubpi.radioid == BCM2057_ID) {
16503 if ((pi->pubpi.radiorev == 5)
16504 || (pi->pubpi.radiorev == 7)
16505 || (pi->pubpi.radiorev == 8)) {
16539 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4, 0x08, 16,
16541 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4, 0x18, 16,
16543 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4, 0x0c, 16,
16545 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4, 0x1c, 16,
16549 static void wlc_phy_workarounds_nphy_rev3(struct brcms_phy *pi)
16605 write_phy_reg(pi, 0x23f, 0x1f8);
16606 write_phy_reg(pi, 0x240, 0x1f8);
16608 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
16611 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
16620 write_phy_reg(pi, 0x145, alpha0);
16621 write_phy_reg(pi, 0x146, alpha1);
16622 write_phy_reg(pi, 0x147, alpha2);
16623 write_phy_reg(pi, 0x148, beta0);
16624 write_phy_reg(pi, 0x149, beta1);
16625 write_phy_reg(pi, 0x14a, beta2);
16627 write_phy_reg(pi, 0x38, 0xC);
16628 write_phy_reg(pi, 0x2ae, 0xC);
16630 wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_TX2RX,
16635 if (PHY_IPA(pi))
16636 wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX,
16641 if ((pi->sh->hw_phyrxchain != 0x3) &&
16642 (pi->sh->hw_phyrxchain != pi->sh->hw_phytxchain)) {
16644 if (PHY_IPA(pi)) {
16650 wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX,
16656 if (CHSPEC_IS2G(pi->radio_chanspec))
16657 write_phy_reg(pi, 0x6a, 0x2);
16659 write_phy_reg(pi, 0x6a, 0x9c40);
16661 mod_phy_reg(pi, 0x294, (0xf << 8), (7 << 8));
16663 if (CHSPEC_IS40(pi->radio_chanspec) == 0) {
16664 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 3,
16666 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
16670 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 3,
16674 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
16678 wlc_phy_workarounds_nphy_gainctrl(pi);
16680 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x00, 16,
16682 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x10, 16,
16685 pdetrange = (CHSPEC_IS5G(pi->radio_chanspec)) ?
16686 pi->srom_fem5g.pdetrange : pi->srom_fem2g.pdetrange;
16689 if (NREV_GE(pi->pubpi.phy_rev, 4)) {
16696 chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0);
16715 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16717 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16719 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16721 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16724 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16726 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16728 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16730 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16737 if (NREV_GE(pi->pubpi.phy_rev, 6)) {
16739 wlc_phy_get_chan_freq_range_nphy(pi, 0);
16747 } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
16752 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16754 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16756 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16758 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16761 chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0);
16762 if ((NREV_GE(pi->pubpi.phy_rev, 4)) &&
16767 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16769 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16771 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16773 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16781 chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0);
16796 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16798 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16803 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16805 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16809 write_radio_reg(pi, (RADIO_2056_RX_MIXA_MAST_BIAS | RADIO_2056_RX0), 0x0);
16810 write_radio_reg(pi, (RADIO_2056_RX_MIXA_MAST_BIAS | RADIO_2056_RX1), 0x0);
16812 write_radio_reg(pi, (RADIO_2056_RX_MIXA_BIAS_MAIN | RADIO_2056_RX0), 0x6);
16813 write_radio_reg(pi, (RADIO_2056_RX_MIXA_BIAS_MAIN | RADIO_2056_RX1), 0x6);
16815 write_radio_reg(pi, (RADIO_2056_RX_MIXA_BIAS_AUX | RADIO_2056_RX0), 0x7);
16816 write_radio_reg(pi, (RADIO_2056_RX_MIXA_BIAS_AUX | RADIO_2056_RX1), 0x7);
16818 write_radio_reg(pi, (RADIO_2056_RX_MIXA_LOB_BIAS | RADIO_2056_RX0), 0x88);
16819 write_radio_reg(pi, (RADIO_2056_RX_MIXA_LOB_BIAS | RADIO_2056_RX1), 0x88);
16821 write_radio_reg(pi, (RADIO_2056_RX_MIXA_CMFB_IDAC | RADIO_2056_RX0), 0x0);
16822 write_radio_reg(pi, (RADIO_2056_RX_MIXA_CMFB_IDAC | RADIO_2056_RX1), 0x0);
16824 write_radio_reg(pi, (RADIO_2056_RX_MIXG_CMFB_IDAC | RADIO_2056_RX0), 0x0);
16825 write_radio_reg(pi, (RADIO_2056_RX_MIXG_CMFB_IDAC | RADIO_2056_RX1), 0x0);
16827 triso = (CHSPEC_IS5G(pi->radio_chanspec)) ?
16828 pi->srom_fem5g.triso : pi->srom_fem2g.triso;
16830 wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, PHY_CORE_0);
16831 wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, PHY_CORE_1);
16834 wlc_phy_war_txchain_upd_nphy(pi, pi->sh->hw_phytxchain);
16836 if (((pi->sh->boardflags2 & BFL2_APLL_WAR) &&
16837 (CHSPEC_IS5G(pi->radio_chanspec))) ||
16838 (((pi->sh->boardflags2 & BFL2_GPLL_WAR) ||
16839 (pi->sh->boardflags2 & BFL2_GPLL_WAR2)) &&
16840 (CHSPEC_IS2G(pi->radio_chanspec)))) {
16849 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
16851 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
16853 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
16856 if (NREV_IS(pi->pubpi.phy_rev, 4)) {
16857 if (CHSPEC_IS5G(pi->radio_chanspec)) {
16858 write_radio_reg(pi,
16861 write_radio_reg(pi,
16867 if (!pi->edcrs_threshold_lock) {
16868 write_phy_reg(pi, 0x224, 0x3eb);
16869 write_phy_reg(pi, 0x225, 0x3eb);
16870 write_phy_reg(pi, 0x226, 0x341);
16871 write_phy_reg(pi, 0x227, 0x341);
16872 write_phy_reg(pi, 0x228, 0x42b);
16873 write_phy_reg(pi, 0x229, 0x42b);
16874 write_phy_reg(pi, 0x22a, 0x381);
16875 write_phy_reg(pi, 0x22b, 0x381);
16876 write_phy_reg(pi, 0x22c, 0x42b);
16877 write_phy_reg(pi, 0x22d, 0x42b);
16878 write_phy_reg(pi, 0x22e, 0x381);
16879 write_phy_reg(pi, 0x22f, 0x381);
16882 if (NREV_GE(pi->pubpi.phy_rev, 6)) {
16884 if (pi->sh->boardflags2 & BFL2_SINGLEANT_CCK)
16885 wlapi_bmac_mhf(pi->sh->physhim, MHF4,
16891 static void wlc_phy_workarounds_nphy_rev1(struct brcms_phy *pi)
16917 if (pi->sh->boardflags2 & BFL2_SKWRKFEM_BRD ||
16918 (pi->sh->boardtype == 0x8b)) {
16925 if (CHSPEC_IS5G(pi->radio_chanspec) && pi->phy_5g_pwrgain) {
16926 and_radio_reg(pi, RADIO_2055_CORE1_TX_RF_SPARE, 0xf7);
16927 and_radio_reg(pi, RADIO_2055_CORE2_TX_RF_SPARE, 0xf7);
16929 or_radio_reg(pi, RADIO_2055_CORE1_TX_RF_SPARE, 0x8);
16930 or_radio_reg(pi, RADIO_2055_CORE2_TX_RF_SPARE, 0x8);
16934 wlc_phy_table_write_nphy(pi, 8, 1, 0, 16, ®val);
16935 wlc_phy_table_write_nphy(pi, 8, 1, 0x10, 16, ®val);
16937 if (NREV_LT(pi->pubpi.phy_rev, 3)) {
16939 wlc_phy_table_write_nphy(pi, 8, 1, 0x02, 16, ®val);
16940 wlc_phy_table_write_nphy(pi, 8, 1, 0x12, 16, ®val);
16943 if (NREV_LT(pi->pubpi.phy_rev, 2)) {
16945 wlc_phy_table_write_nphy(pi, 8, 1, 0x08, 16, ®val);
16946 wlc_phy_table_write_nphy(pi, 8, 1, 0x18, 16, ®val);
16949 wlc_phy_table_write_nphy(pi, 8, 1, 0x07, 16, ®val);
16950 wlc_phy_table_write_nphy(pi, 8, 1, 0x17, 16, ®val);
16953 wlc_phy_table_write_nphy(pi, 8, 1, 0x06, 16, ®val);
16954 wlc_phy_table_write_nphy(pi, 8, 1, 0x16, 16, ®val);
16957 write_phy_reg(pi, 0xf8, 0x02d8);
16958 write_phy_reg(pi, 0xf9, 0x0301);
16959 write_phy_reg(pi, 0xfa, 0x02d8);
16960 write_phy_reg(pi, 0xfb, 0x0301);
16962 wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX, rfseq_rx2tx_events,
16966 wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_TX2RX, rfseq_tx2rx_events,
16970 wlc_phy_workarounds_nphy_gainctrl(pi);
16972 if (NREV_LT(pi->pubpi.phy_rev, 2)) {
16974 if (read_phy_reg(pi, 0xa0) & NPHY_MLenable)
16975 wlapi_bmac_mhf(pi->sh->physhim, MHF3,
16979 } else if (NREV_IS(pi->pubpi.phy_rev, 2)) {
16980 write_phy_reg(pi, 0x1e3, 0x0);
16981 write_phy_reg(pi, 0x1e4, 0x0);
16984 if (NREV_LT(pi->pubpi.phy_rev, 2))
16985 mod_phy_reg(pi, 0x90, (0x1 << 7), 0);
16993 write_phy_reg(pi, 0x145, alpha0);
16994 write_phy_reg(pi, 0x146, alpha1);
16995 write_phy_reg(pi, 0x147, alpha2);
16996 write_phy_reg(pi, 0x148, beta0);
16997 write_phy_reg(pi, 0x149, beta1);
16998 write_phy_reg(pi, 0x14a, beta2);
17000 if (NREV_LT(pi->pubpi.phy_rev, 3)) {
17001 mod_phy_reg(pi, 0x142, (0xf << 12), 0);
17003 write_phy_reg(pi, 0x192, 0xb5);
17004 write_phy_reg(pi, 0x193, 0xa4);
17005 write_phy_reg(pi, 0x194, 0x0);
17008 if (NREV_IS(pi->pubpi.phy_rev, 2))
17009 mod_phy_reg(pi, 0x221,
17014 static void wlc_phy_workarounds_nphy(struct brcms_phy *pi)
17016 if (CHSPEC_IS5G(pi->radio_chanspec))
17017 wlc_phy_classifier_nphy(pi, NPHY_ClassifierCtrl_cck_en, 0);
17019 wlc_phy_classifier_nphy(pi, NPHY_ClassifierCtrl_cck_en, 1);
17021 if (pi->phyhang_avoid)
17022 wlc_phy_stay_in_carriersearch_nphy(pi, true);
17024 or_phy_reg(pi, 0xb1, NPHY_IQFlip_ADC1 | NPHY_IQFlip_ADC2);
17026 if (NREV_GE(pi->pubpi.phy_rev, 7))
17027 wlc_phy_workarounds_nphy_rev7(pi);
17028 else if (NREV_GE(pi->pubpi.phy_rev, 3))
17029 wlc_phy_workarounds_nphy_rev3(pi);
17031 wlc_phy_workarounds_nphy_rev1(pi);
17033 if (pi->phyhang_avoid)
17034 wlc_phy_stay_in_carriersearch_nphy(pi, false);
17037 static void wlc_phy_extpa_set_tx_digi_filts_nphy(struct brcms_phy *pi)
17043 write_phy_reg(pi, addr_offset + j,
17047 static void wlc_phy_clip_det_nphy(struct brcms_phy *pi, u8 write, u16 *vals)
17051 vals[0] = read_phy_reg(pi, 0x2c);
17052 vals[1] = read_phy_reg(pi, 0x42);
17054 write_phy_reg(pi, 0x2c, vals[0]);
17055 write_phy_reg(pi, 0x42, vals[1]);
17059 static void wlc_phy_ipa_internal_tssi_setup_nphy(struct brcms_phy *pi)
17063 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
17064 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
17065 if (CHSPEC_IS2G(pi->radio_chanspec)) {
17066 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
17068 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
17071 if (pi->pubpi.radiorev != 5)
17072 WRITE_RADIO_REG3(pi, RADIO_2057, TX,
17075 if (!NREV_IS(pi->pubpi.phy_rev, 7))
17076 WRITE_RADIO_REG3(pi, RADIO_2057, TX,
17079 WRITE_RADIO_REG3(pi, RADIO_2057, TX,
17082 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
17084 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
17086 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
17089 if (pi->pubpi.radiorev != 5) {
17090 if (!NREV_IS(pi->pubpi.phy_rev, 7))
17091 WRITE_RADIO_REG3(pi, RADIO_2057,
17095 WRITE_RADIO_REG3(pi, RADIO_2057,
17100 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, IQCAL_VCM_HG,
17102 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, IQCAL_IDAC,
17104 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSI_VCM,
17106 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSI_MISC1,
17110 WRITE_RADIO_SYN(pi, RADIO_2056, RESERVED_ADDR31,
17111 (CHSPEC_IS2G(pi->radio_chanspec)) ? 0x128 :
17113 WRITE_RADIO_SYN(pi, RADIO_2056, RESERVED_ADDR30, 0x0);
17114 WRITE_RADIO_SYN(pi, RADIO_2056, GPIO_MASTER1, 0x29);
17116 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
17117 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, IQCAL_VCM_HG,
17119 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, IQCAL_IDAC,
17121 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TSSI_VCM,
17123 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TX_AMP_DET,
17125 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TSSI_MISC1,
17127 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TSSI_MISC2,
17129 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TSSI_MISC3,
17132 if (CHSPEC_IS2G(pi->radio_chanspec)) {
17133 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
17136 if (pi->pubpi.radiorev != 5)
17137 WRITE_RADIO_REG2(pi, RADIO_2056, TX,
17139 if (NREV_GE(pi->pubpi.phy_rev, 5))
17140 WRITE_RADIO_REG2(pi, RADIO_2056, TX,
17143 WRITE_RADIO_REG2(pi, RADIO_2056, TX,
17145 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
17148 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
17150 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
17152 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
17154 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
17162 wlc_phy_rfctrl_override_nphy(struct brcms_phy *pi, u16 field, u16 value,
17170 if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 7)) {
17275 and_phy_reg(pi, en_addr, ~en_mask);
17276 and_phy_reg(pi, val_addr, ~val_mask);
17281 or_phy_reg(pi, en_addr, en_mask);
17284 mod_phy_reg(pi, val_addr,
17294 and_phy_reg(pi, 0xec, ~field);
17297 or_phy_reg(pi, 0xec, field);
17395 mod_phy_reg(pi, addr, mask, (value << shift));
17398 or_phy_reg(pi, 0xec, (0x1 << 0));
17399 or_phy_reg(pi, 0x78, (0x1 << 0));
17401 and_phy_reg(pi, 0xec, ~(0x1 << 0));
17405 static void wlc_phy_txpwrctrl_idle_tssi_nphy(struct brcms_phy *pi)
17410 if (SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi) || PHY_MUTED(pi))
17414 if (PHY_IPA(pi))
17415 wlc_phy_ipa_internal_tssi_setup_nphy(pi);
17417 if (NREV_GE(pi->pubpi.phy_rev, 7))
17418 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 12),
17421 else if (NREV_GE(pi->pubpi.phy_rev, 3))
17422 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 13), 0, 3, 0);
17424 wlc_phy_stopplayback_nphy(pi);
17426 wlc_phy_tx_tone_nphy(pi, 4000, 0, 0, 0, false);
17430 wlc_phy_poll_rssi_nphy(pi, (u8) NPHY_RSSI_SEL_TSSI_2G, rssi_buf,
17432 wlc_phy_stopplayback_nphy(pi);
17433 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_OFF, 0);
17435 if (NREV_GE(pi->pubpi.phy_rev, 7))
17436 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 12),
17439 else if (NREV_GE(pi->pubpi.phy_rev, 3))
17440 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 13), 0, 3, 1);
17442 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
17444 pi->nphy_pwrctrl_info[PHY_CORE_0].idle_tssi_2g =
17446 pi->nphy_pwrctrl_info[PHY_CORE_0].idle_tssi_5g =
17449 pi->nphy_pwrctrl_info[PHY_CORE_1].idle_tssi_2g =
17451 pi->nphy_pwrctrl_info[PHY_CORE_1].idle_tssi_5g =
17454 pi->nphy_pwrctrl_info[PHY_CORE_0].idle_tssi_2g =
17457 pi->nphy_pwrctrl_info[PHY_CORE_1].idle_tssi_2g =
17460 pi->nphy_pwrctrl_info[PHY_CORE_0].idle_tssi_5g =
17462 pi->nphy_pwrctrl_info[PHY_CORE_1].idle_tssi_5g =
17468 static void wlc_phy_txpwr_limit_to_tbl_nphy(struct brcms_phy *pi)
17473 pi->adj_pwr_tbl_nphy[idx] = pi->tx_power_offset[idx];
17483 if (CHSPEC_IS40(pi->radio_chanspec)
17487 idx = (CHSPEC_IS40(pi->radio_chanspec)) ?
17495 idx = (CHSPEC_IS40(pi->radio_chanspec)) ?
17501 idx = (CHSPEC_IS40(pi->radio_chanspec)) ?
17507 idx = (CHSPEC_IS40(pi->radio_chanspec)) ?
17512 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17513 pi->tx_power_offset[idx];
17515 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17516 pi->tx_power_offset[idx];
17517 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17518 pi->tx_power_offset[idx];
17519 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17520 pi->tx_power_offset[idx++];
17522 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17523 pi->tx_power_offset[idx++];
17524 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17525 pi->tx_power_offset[idx];
17526 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17527 pi->tx_power_offset[idx];
17528 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17529 pi->tx_power_offset[idx++];
17531 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17532 pi->tx_power_offset[idx++];
17533 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17534 pi->tx_power_offset[idx];
17535 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17536 pi->tx_power_offset[idx];
17537 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17538 pi->tx_power_offset[idx++];
17540 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17541 pi->tx_power_offset[idx];
17542 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17543 pi->tx_power_offset[idx++];
17544 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17545 pi->tx_power_offset[idx];
17547 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17548 pi->tx_power_offset[idx];
17550 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17551 pi->tx_power_offset[idx];
17552 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17553 pi->tx_power_offset[idx];
17554 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17555 pi->tx_power_offset[idx];
17556 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17557 pi->tx_power_offset[idx];
17561 static void wlc_phy_txpwrctrl_pwr_setup_nphy(struct brcms_phy *pi)
17573 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
17574 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
17575 (void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
17579 if (pi->phyhang_avoid)
17580 wlc_phy_stay_in_carriersearch_nphy(pi, true);
17582 or_phy_reg(pi, 0x122, (0x1 << 0));
17584 if (NREV_GE(pi->pubpi.phy_rev, 3))
17585 and_phy_reg(pi, 0x1e7, 0x7fff);
17587 or_phy_reg(pi, 0x1e7, (0x1 << 15));
17589 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12))
17590 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, 0);
17592 if (pi->sh->sromrev < 4) {
17593 idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_2g;
17594 idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_2g;
17603 chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0);
17606 idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_2g;
17607 idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_2g;
17608 a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_2g_a1;
17609 a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_2g_a1;
17610 b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_2g_b0;
17611 b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_2g_b0;
17612 b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_2g_b1;
17613 b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_2g_b1;
17616 idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_5g;
17617 idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_5g;
17618 a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gl_a1;
17619 a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gl_a1;
17620 b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gl_b0;
17621 b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gl_b0;
17622 b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gl_b1;
17623 b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gl_b1;
17626 idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_5g;
17627 idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_5g;
17628 a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gm_a1;
17629 a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gm_a1;
17630 b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gm_b0;
17631 b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gm_b0;
17632 b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gm_b1;
17633 b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gm_b1;
17636 idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_5g;
17637 idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_5g;
17638 a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gh_a1;
17639 a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gh_a1;
17640 b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gh_b0;
17641 b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gh_b0;
17642 b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gh_b1;
17643 b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gh_b1;
17646 idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_2g;
17647 idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_2g;
17659 target_pwr_qtrdbm[0] = (s8) pi->tx_power_max;
17660 target_pwr_qtrdbm[1] = (s8) pi->tx_power_max;
17662 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
17663 if (pi->srom_fem2g.tssipos)
17664 or_phy_reg(pi, 0x1e9, (0x1 << 14));
17666 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
17668 if (PHY_IPA(pi)) {
17669 if (CHSPEC_IS2G(pi->radio_chanspec))
17670 WRITE_RADIO_REG3(pi, RADIO_2057,
17675 WRITE_RADIO_REG3(pi, RADIO_2057,
17682 if (PHY_IPA(pi)) {
17684 write_radio_reg(pi, RADIO_2056_TX_TX_SSI_MUX |
17687 (pi->radio_chanspec)) ?
17689 write_radio_reg(pi,
17693 (pi->radio_chanspec)) ?
17697 write_radio_reg(pi, RADIO_2056_TX_TX_SSI_MUX |
17699 write_radio_reg(pi, RADIO_2056_TX_TX_SSI_MUX |
17705 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
17706 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
17707 (void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
17711 if (NREV_GE(pi->pubpi.phy_rev, 7))
17712 mod_phy_reg(pi, 0x1e7, (0x7f << 0),
17715 mod_phy_reg(pi, 0x1e7, (0x7f << 0),
17718 if (NREV_GE(pi->pubpi.phy_rev, 7))
17719 mod_phy_reg(pi, 0x222, (0xff << 0),
17721 else if (NREV_GT(pi->pubpi.phy_rev, 1))
17722 mod_phy_reg(pi, 0x222, (0xff << 0),
17725 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12))
17726 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, 0);
17728 write_phy_reg(pi, 0x1e8, (0x3 << 8) | (240 << 0));
17730 write_phy_reg(pi, 0x1e9,
17733 write_phy_reg(pi, 0x1ea,
17747 if (NREV_LT(pi->pubpi.phy_rev, 3)) {
17757 wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32,
17761 wlc_phy_txpwr_limit_to_tbl_nphy(pi);
17762 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 84, 64, 8,
17763 pi->adj_pwr_tbl_nphy);
17764 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 84, 64, 8,
17765 pi->adj_pwr_tbl_nphy);
17767 if (pi->phyhang_avoid)
17768 wlc_phy_stay_in_carriersearch_nphy(pi, false);
17771 static u32 *wlc_phy_get_ipa_gaintbl_nphy(struct brcms_phy *pi)
17775 if (CHSPEC_IS2G(pi->radio_chanspec)) {
17776 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
17777 if ((pi->pubpi.radiorev == 4)
17778 || (pi->pubpi.radiorev == 6))
17781 else if (pi->pubpi.radiorev == 3)
17784 else if (pi->pubpi.radiorev == 5)
17787 else if ((pi->pubpi.radiorev == 7)
17788 || (pi->pubpi.radiorev == 8))
17791 } else if (NREV_IS(pi->pubpi.phy_rev, 6)) {
17793 if (pi->sh->chip == BCMA_CHIP_ID_BCM47162)
17795 } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
17802 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
17803 if ((pi->pubpi.radiorev == 3) ||
17804 (pi->pubpi.radiorev == 4) ||
17805 (pi->pubpi.radiorev == 6))
17807 else if ((pi->pubpi.radiorev == 7)
17808 || (pi->pubpi.radiorev == 8))
17819 static void wlc_phy_restore_rssical_nphy(struct brcms_phy *pi)
17821 if (CHSPEC_IS2G(pi->radio_chanspec)) {
17822 if (pi->nphy_rssical_chanspec_2G == 0)
17825 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
17826 mod_radio_reg(pi, RADIO_2057_NB_MASTER_CORE0,
17828 pi->rssical_cache.
17830 mod_radio_reg(pi, RADIO_2057_NB_MASTER_CORE1,
17832 pi->rssical_cache.
17835 mod_radio_reg(pi,
17838 pi->rssical_cache.
17840 mod_radio_reg(pi,
17843 pi->rssical_cache.
17847 write_phy_reg(pi, 0x1a6,
17848 pi->rssical_cache.rssical_phyregs_2G[0]);
17849 write_phy_reg(pi, 0x1ac,
17850 pi->rssical_cache.rssical_phyregs_2G[1]);
17851 write_phy_reg(pi, 0x1b2,
17852 pi->rssical_cache.rssical_phyregs_2G[2]);
17853 write_phy_reg(pi, 0x1b8,
17854 pi->rssical_cache.rssical_phyregs_2G[3]);
17855 write_phy_reg(pi, 0x1a4,
17856 pi->rssical_cache.rssical_phyregs_2G[4]);
17857 write_phy_reg(pi, 0x1aa,
17858 pi->rssical_cache.rssical_phyregs_2G[5]);
17859 write_phy_reg(pi, 0x1b0,
17860 pi->rssical_cache.rssical_phyregs_2G[6]);
17861 write_phy_reg(pi, 0x1b6,
17862 pi->rssical_cache.rssical_phyregs_2G[7]);
17863 write_phy_reg(pi, 0x1a5,
17864 pi->rssical_cache.rssical_phyregs_2G[8]);
17865 write_phy_reg(pi, 0x1ab,
17866 pi->rssical_cache.rssical_phyregs_2G[9]);
17867 write_phy_reg(pi, 0x1b1,
17868 pi->rssical_cache.rssical_phyregs_2G[10]);
17869 write_phy_reg(pi, 0x1b7,
17870 pi->rssical_cache.rssical_phyregs_2G[11]);
17873 if (pi->nphy_rssical_chanspec_5G == 0)
17876 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
17877 mod_radio_reg(pi, RADIO_2057_NB_MASTER_CORE0,
17879 pi->rssical_cache.
17881 mod_radio_reg(pi, RADIO_2057_NB_MASTER_CORE1,
17883 pi->rssical_cache.
17886 mod_radio_reg(pi,
17889 pi->rssical_cache.
17891 mod_radio_reg(pi,
17894 pi->rssical_cache.
17898 write_phy_reg(pi, 0x1a6,
17899 pi->rssical_cache.rssical_phyregs_5G[0]);
17900 write_phy_reg(pi, 0x1ac,
17901 pi->rssical_cache.rssical_phyregs_5G[1]);
17902 write_phy_reg(pi, 0x1b2,
17903 pi->rssical_cache.rssical_phyregs_5G[2]);
17904 write_phy_reg(pi, 0x1b8,
17905 pi->rssical_cache.rssical_phyregs_5G[3]);
17906 write_phy_reg(pi, 0x1a4,
17907 pi->rssical_cache.rssical_phyregs_5G[4]);
17908 write_phy_reg(pi, 0x1aa,
17909 pi->rssical_cache.rssical_phyregs_5G[5]);
17910 write_phy_reg(pi, 0x1b0,
17911 pi->rssical_cache.rssical_phyregs_5G[6]);
17912 write_phy_reg(pi, 0x1b6,
17913 pi->rssical_cache.rssical_phyregs_5G[7]);
17914 write_phy_reg(pi, 0x1a5,
17915 pi->rssical_cache.rssical_phyregs_5G[8]);
17916 write_phy_reg(pi, 0x1ab,
17917 pi->rssical_cache.rssical_phyregs_5G[9]);
17918 write_phy_reg(pi, 0x1b1,
17919 pi->rssical_cache.rssical_phyregs_5G[10]);
17920 write_phy_reg(pi, 0x1b7,
17921 pi->rssical_cache.rssical_phyregs_5G[11]);
17925 static void wlc_phy_internal_cal_txgain_nphy(struct brcms_phy *pi)
17929 pi->nphy_txcal_pwr_idx[0] = pi->nphy_cal_orig_pwr_idx[0];
17930 pi->nphy_txcal_pwr_idx[1] = pi->nphy_cal_orig_pwr_idx[0];
17931 wlc_phy_txpwr_index_nphy(pi, 1, pi->nphy_cal_orig_pwr_idx[0], true);
17932 wlc_phy_txpwr_index_nphy(pi, 2, pi->nphy_cal_orig_pwr_idx[1], true);
17934 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
17937 if (CHSPEC_IS2G(pi->radio_chanspec)) {
17945 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
17949 static void wlc_phy_precal_txgain_nphy(struct brcms_phy *pi)
17955 if (pi->use_int_tx_iqlo_cal_nphy) {
17956 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
17957 if ((pi->pubpi.radiorev == 3) ||
17958 (pi->pubpi.radiorev == 4) ||
17959 (pi->pubpi.radiorev == 6)) {
17961 pi->nphy_txcal_pwr_idx[0] =
17963 pi->nphy_txcal_pwr_idx[1] =
17966 pi, 3,
17971 pi->nphy_txcal_pwr_idx[0] =
17973 pi->nphy_txcal_pwr_idx[1] =
17976 pi, 3,
17982 } else if (NREV_LT(pi->pubpi.phy_rev, 5)) {
17983 wlc_phy_cal_txgainctrl_nphy(pi, 11, false);
17984 if (pi->sh->hw_phytxchain != 3) {
17985 pi->nphy_txcal_pwr_idx[1] =
17986 pi->nphy_txcal_pwr_idx[0];
17987 wlc_phy_txpwr_index_nphy(pi, 3,
17988 pi->
17994 } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
17995 if (PHY_IPA(pi)) {
17996 if (CHSPEC_IS2G(pi->radio_chanspec)) {
17997 wlc_phy_cal_txgainctrl_nphy(pi, 12,
18000 pi->nphy_txcal_pwr_idx[0] = 80;
18001 pi->nphy_txcal_pwr_idx[1] = 80;
18002 wlc_phy_txpwr_index_nphy(pi, 3, 80,
18007 wlc_phy_internal_cal_txgain_nphy(pi);
18011 } else if (NREV_IS(pi->pubpi.phy_rev, 6)) {
18012 if (PHY_IPA(pi)) {
18013 if (CHSPEC_IS2G(pi->radio_chanspec))
18014 wlc_phy_cal_txgainctrl_nphy(pi, 12,
18017 wlc_phy_cal_txgainctrl_nphy(pi, 14,
18020 wlc_phy_internal_cal_txgain_nphy(pi);
18026 wlc_phy_cal_txgainctrl_nphy(pi, 10, false);
18030 wlc_phy_table_read_nphy(pi, 15, 1, 87, 16,
18031 &pi->nphy_txcal_bbmult);
18035 wlc_phy_rfctrlintc_override_nphy(struct brcms_phy *pi, u8 field, u16 value,
18042 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
18043 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
18051 if (NREV_LT(pi->pubpi.phy_rev, 7)) {
18055 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x91 :
18061 write_phy_reg(pi, (core == PHY_CORE_0) ? 0x91 :
18064 wlc_phy_force_rfseq_nphy(pi,
18068 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18073 mod_phy_reg(pi,
18078 or_phy_reg(pi,
18083 and_phy_reg(pi, 0x2ff, (u16)
18085 or_phy_reg(pi, 0x2ff, (0x1 << 13));
18086 or_phy_reg(pi, 0x2ff, (0x1 << 0));
18093 mod_phy_reg(pi,
18100 mod_phy_reg(pi,
18109 mod_phy_reg(pi, 0x78, mask, val);
18111 SPINWAIT(((read_phy_reg(pi, 0x78) & val)
18113 if (WARN(read_phy_reg(pi, 0x78) & val,
18119 mod_phy_reg(pi,
18125 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18129 if (CHSPEC_IS5G(pi->radio_chanspec))
18134 mod_phy_reg(pi,
18139 or_phy_reg(pi,
18145 if (CHSPEC_IS5G(pi->radio_chanspec)) {
18152 mod_phy_reg(pi,
18159 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18160 if (CHSPEC_IS5G(pi->radio_chanspec)) {
18164 mod_phy_reg(pi,
18170 mod_phy_reg(pi,
18178 mod_phy_reg(pi,
18184 mod_phy_reg(pi,
18192 mod_phy_reg(pi,
18198 if (CHSPEC_IS5G(pi->radio_chanspec)) {
18205 mod_phy_reg(pi,
18212 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18213 if (CHSPEC_IS5G(pi->radio_chanspec)) {
18217 mod_phy_reg(pi,
18223 mod_phy_reg(pi,
18231 mod_phy_reg(pi,
18237 mod_phy_reg(pi,
18245 mod_phy_reg(pi,
18251 if (CHSPEC_IS5G(pi->radio_chanspec)) {
18258 mod_phy_reg(pi,
18269 wlc_phy_cal_txgainctrl_nphy(struct brcms_phy *pi, s32 dBm_targetpower,
18285 if (NREV_GE(pi->pubpi.phy_rev, 7))
18290 if (CHSPEC_IS40(pi->radio_chanspec))
18295 wlc_phy_txpwr_index_nphy(pi, 1, pi->nphy_cal_orig_pwr_idx[0], true);
18296 wlc_phy_txpwr_index_nphy(pi, 2, pi->nphy_cal_orig_pwr_idx[1], true);
18298 if (pi->phyhang_avoid)
18299 wlc_phy_stay_in_carriersearch_nphy(pi, true);
18301 phyhang_avoid_state = pi->phyhang_avoid;
18302 pi->phyhang_avoid = false;
18304 phy_saveregs[0] = read_phy_reg(pi, 0x91);
18305 phy_saveregs[1] = read_phy_reg(pi, 0x92);
18306 phy_saveregs[2] = read_phy_reg(pi, 0xe7);
18307 phy_saveregs[3] = read_phy_reg(pi, 0xec);
18308 wlc_phy_rfctrlintc_override_nphy(pi, NPHY_RfctrlIntc_override_PA, 1,
18313 wlc_phy_rfctrlintc_override_nphy(pi,
18316 wlc_phy_rfctrlintc_override_nphy(pi,
18320 wlc_phy_rfctrlintc_override_nphy(pi,
18323 wlc_phy_rfctrlintc_override_nphy(pi,
18328 orig_BBConfig = read_phy_reg(pi, 0x01);
18329 mod_phy_reg(pi, 0x01, (0x1 << 15), 0);
18331 wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m0m1);
18333 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
18334 txpwrindex = (s32) pi->nphy_cal_orig_pwr_idx[core];
18338 wlc_phy_tx_tone_nphy(pi, freq_test, ampl_test, 0, 0,
18346 wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &curr_m0m1);
18347 wlc_phy_table_write_nphy(pi, 15, 1, 95, 16, &curr_m0m1);
18351 wlc_phy_est_tonepwr_nphy(pi, qdBm_power,
18354 pi->nphy_bb_mult_save = 0;
18355 wlc_phy_stopplayback_nphy(pi);
18365 if (CHSPEC_IS5G(pi->radio_chanspec)) {
18366 if (NREV_IS(pi->pubpi.phy_rev, 4) &&
18367 (pi->srom_fem5g.extpagain == 3)) {
18372 if (NREV_GE(pi->pubpi.phy_rev, 5) &&
18373 (pi->srom_fem2g.extpagain == 3)) {
18379 wlc_phy_txpwr_index_nphy(pi, (1 << core),
18383 pi->nphy_txcal_pwr_idx[core] = (u8) txpwrindex;
18389 wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &dbg_m0m1);
18391 wlc_phy_tx_tone_nphy(pi, freq_test, ampl_test, 0, 0,
18394 wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &dbg_m0m1);
18395 wlc_phy_table_write_nphy(pi, 15, 1, 95, 16, &dbg_m0m1);
18399 wlc_phy_est_tonepwr_nphy(pi, qdBm_power,
18402 wlc_phy_table_read_nphy(pi, 7, 1, (0x110 + core), 16,
18406 pi->nphy_bb_mult_save = 0;
18407 wlc_phy_stopplayback_nphy(pi);
18411 wlc_phy_txpwr_index_nphy(pi, 1, pi->nphy_txcal_pwr_idx[0], true);
18412 wlc_phy_txpwr_index_nphy(pi, 2, pi->nphy_txcal_pwr_idx[1], true);
18414 wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &pi->nphy_txcal_bbmult);
18416 write_phy_reg(pi, 0x01, orig_BBConfig);
18418 write_phy_reg(pi, 0x91, phy_saveregs[0]);
18419 write_phy_reg(pi, 0x92, phy_saveregs[1]);
18420 write_phy_reg(pi, 0xe7, phy_saveregs[2]);
18421 write_phy_reg(pi, 0xec, phy_saveregs[3]);
18423 pi->phyhang_avoid = phyhang_avoid_state;
18425 if (pi->phyhang_avoid)
18426 wlc_phy_stay_in_carriersearch_nphy(pi, false);
18429 static void wlc_phy_savecal_nphy(struct brcms_phy *pi)
18435 if (pi->phyhang_avoid)
18436 wlc_phy_stay_in_carriersearch_nphy(pi, true);
18438 if (CHSPEC_IS2G(pi->radio_chanspec)) {
18440 wlc_phy_rx_iq_coeffs_nphy(pi, 0,
18441 &pi->calibration_cache.
18444 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18446 pi->calibration_cache.txcal_radio_regs_2G;
18447 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
18449 pi->calibration_cache.txcal_radio_regs_2G[0] =
18450 read_radio_reg(pi,
18453 pi->calibration_cache.txcal_radio_regs_2G[1] =
18454 read_radio_reg(pi,
18457 pi->calibration_cache.txcal_radio_regs_2G[2] =
18458 read_radio_reg(pi,
18461 pi->calibration_cache.txcal_radio_regs_2G[3] =
18462 read_radio_reg(pi,
18466 pi->calibration_cache.txcal_radio_regs_2G[4] =
18467 read_radio_reg(pi,
18470 pi->calibration_cache.txcal_radio_regs_2G[5] =
18471 read_radio_reg(pi,
18474 pi->calibration_cache.txcal_radio_regs_2G[6] =
18475 read_radio_reg(pi,
18478 pi->calibration_cache.txcal_radio_regs_2G[7] =
18479 read_radio_reg(pi,
18483 pi->calibration_cache.txcal_radio_regs_2G[0] =
18484 read_radio_reg(pi, RADIO_2055_CORE1_TX_VOS_CNCL);
18485 pi->calibration_cache.txcal_radio_regs_2G[1] =
18486 read_radio_reg(pi, RADIO_2055_CORE2_TX_VOS_CNCL);
18487 pi->calibration_cache.txcal_radio_regs_2G[2] =
18488 read_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM);
18489 pi->calibration_cache.txcal_radio_regs_2G[3] =
18490 read_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM);
18493 pi->nphy_iqcal_chanspec_2G = pi->radio_chanspec;
18494 tbl_ptr = pi->calibration_cache.txcal_coeffs_2G;
18497 wlc_phy_rx_iq_coeffs_nphy(pi, 0,
18498 &pi->calibration_cache.
18501 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18503 pi->calibration_cache.txcal_radio_regs_5G;
18504 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
18506 pi->calibration_cache.txcal_radio_regs_5G[0] =
18507 read_radio_reg(pi,
18510 pi->calibration_cache.txcal_radio_regs_5G[1] =
18511 read_radio_reg(pi,
18514 pi->calibration_cache.txcal_radio_regs_5G[2] =
18515 read_radio_reg(pi,
18518 pi->calibration_cache.txcal_radio_regs_5G[3] =
18519 read_radio_reg(pi,
18523 pi->calibration_cache.txcal_radio_regs_5G[4] =
18524 read_radio_reg(pi,
18527 pi->calibration_cache.txcal_radio_regs_5G[5] =
18528 read_radio_reg(pi,
18531 pi->calibration_cache.txcal_radio_regs_5G[6] =
18532 read_radio_reg(pi,
18535 pi->calibration_cache.txcal_radio_regs_5G[7] =
18536 read_radio_reg(pi,
18540 pi->calibration_cache.txcal_radio_regs_5G[0] =
18541 read_radio_reg(pi, RADIO_2055_CORE1_TX_VOS_CNCL);
18542 pi->calibration_cache.txcal_radio_regs_5G[1] =
18543 read_radio_reg(pi, RADIO_2055_CORE2_TX_VOS_CNCL);
18544 pi->calibration_cache.txcal_radio_regs_5G[2] =
18545 read_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM);
18546 pi->calibration_cache.txcal_radio_regs_5G[3] =
18547 read_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM);
18550 pi->nphy_iqcal_chanspec_5G = pi->radio_chanspec;
18551 tbl_ptr = pi->calibration_cache.txcal_coeffs_5G;
18553 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18557 READ_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
18560 READ_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
18564 READ_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
18567 READ_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
18572 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL, 8, 80, 16, tbl_ptr);
18574 if (pi->phyhang_avoid)
18575 wlc_phy_stay_in_carriersearch_nphy(pi, false);
18578 static void wlc_phy_tx_iq_war_nphy(struct brcms_phy *pi)
18582 wlc_phy_table_read_nphy(pi, 15, 4, 0x50, 16, &tx_comp);
18584 wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ, tx_comp.a0);
18585 wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ + 2, tx_comp.b0);
18586 wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ + 4, tx_comp.a1);
18587 wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ + 6, tx_comp.b1);
18590 static void wlc_phy_restorecal_nphy(struct brcms_phy *pi)
18598 if (CHSPEC_IS2G(pi->radio_chanspec)) {
18599 if (pi->nphy_iqcal_chanspec_2G == 0)
18602 tbl_ptr = pi->calibration_cache.txcal_coeffs_2G;
18603 loft_comp = &pi->calibration_cache.txcal_coeffs_2G[5];
18605 if (pi->nphy_iqcal_chanspec_5G == 0)
18608 tbl_ptr = pi->calibration_cache.txcal_coeffs_5G;
18609 loft_comp = &pi->calibration_cache.txcal_coeffs_5G[5];
18612 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 80, 16, tbl_ptr);
18614 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
18626 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 88, 16,
18629 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 85, 16, loft_comp);
18631 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 93, 16, loft_comp);
18633 if (NREV_LT(pi->pubpi.phy_rev, 2))
18634 wlc_phy_tx_iq_war_nphy(pi);
18636 if (CHSPEC_IS2G(pi->radio_chanspec)) {
18637 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18639 pi->calibration_cache.txcal_radio_regs_2G;
18640 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
18642 write_radio_reg(pi,
18645 pi->calibration_cache.
18647 write_radio_reg(pi,
18650 pi->calibration_cache.
18652 write_radio_reg(pi,
18655 pi->calibration_cache.
18657 write_radio_reg(pi,
18660 pi->calibration_cache.
18663 write_radio_reg(pi,
18666 pi->calibration_cache.
18668 write_radio_reg(pi,
18671 pi->calibration_cache.
18673 write_radio_reg(pi,
18676 pi->calibration_cache.
18678 write_radio_reg(pi,
18681 pi->calibration_cache.
18684 write_radio_reg(pi, RADIO_2055_CORE1_TX_VOS_CNCL,
18685 pi->calibration_cache.
18687 write_radio_reg(pi, RADIO_2055_CORE2_TX_VOS_CNCL,
18688 pi->calibration_cache.
18690 write_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM,
18691 pi->calibration_cache.
18693 write_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM,
18694 pi->calibration_cache.
18698 wlc_phy_rx_iq_coeffs_nphy(pi, 1,
18699 &pi->calibration_cache.
18702 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18704 pi->calibration_cache.txcal_radio_regs_5G;
18705 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
18707 write_radio_reg(pi,
18710 pi->calibration_cache.
18712 write_radio_reg(pi,
18715 pi->calibration_cache.
18717 write_radio_reg(pi,
18720 pi->calibration_cache.
18722 write_radio_reg(pi,
18725 pi->calibration_cache.
18728 write_radio_reg(pi,
18731 pi->calibration_cache.
18733 write_radio_reg(pi,
18736 pi->calibration_cache.
18738 write_radio_reg(pi,
18741 pi->calibration_cache.
18743 write_radio_reg(pi,
18746 pi->calibration_cache.
18749 write_radio_reg(pi, RADIO_2055_CORE1_TX_VOS_CNCL,
18750 pi->calibration_cache.
18752 write_radio_reg(pi, RADIO_2055_CORE2_TX_VOS_CNCL,
18753 pi->calibration_cache.
18755 write_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM,
18756 pi->calibration_cache.
18758 write_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM,
18759 pi->calibration_cache.
18763 wlc_phy_rx_iq_coeffs_nphy(pi, 1,
18764 &pi->calibration_cache.
18768 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18771 WRITE_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
18774 WRITE_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
18778 WRITE_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
18781 WRITE_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
18788 static void wlc_phy_txpwrctrl_coeff_setup_nphy(struct brcms_phy *pi)
18798 if (pi->phyhang_avoid)
18799 wlc_phy_stay_in_carriersearch_nphy(pi, true);
18801 wlc_phy_table_read_nphy(pi, 15, 7, 80, 16, iqloCalbuf);
18816 wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32,
18829 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
18845 wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32,
18849 if (NREV_LT(pi->pubpi.phy_rev, 2)) {
18851 wlapi_bmac_write_shm(pi->sh->physhim, M_CURR_IDX1, 0xFFFF);
18852 wlapi_bmac_write_shm(pi->sh->physhim, M_CURR_IDX2, 0xFFFF);
18855 if (pi->phyhang_avoid)
18856 wlc_phy_stay_in_carriersearch_nphy(pi, false);
18859 static void wlc_phy_txlpfbw_nphy(struct brcms_phy *pi)
18863 if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 7)) {
18864 if (CHSPEC_IS40(pi->radio_chanspec))
18869 if (PHY_IPA(pi)) {
18870 if (CHSPEC_IS40(pi->radio_chanspec))
18876 write_phy_reg(pi, 0xe8,
18881 if (PHY_IPA(pi)) {
18883 if (CHSPEC_IS40(pi->radio_chanspec))
18888 write_phy_reg(pi, 0xe9,
18897 wlc_phy_adjust_rx_analpfbw_nphy(struct brcms_phy *pi, u16 reduction_factr)
18899 if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 7)) {
18900 if ((CHSPEC_CHANNEL(pi->radio_chanspec) == 11) &&
18901 CHSPEC_IS40(pi->radio_chanspec)) {
18902 if (!pi->nphy_anarxlpf_adjusted) {
18903 write_radio_reg(pi,
18906 ((pi->nphy_rccal_value +
18909 pi->nphy_anarxlpf_adjusted = true;
18912 if (pi->nphy_anarxlpf_adjusted) {
18913 write_radio_reg(pi,
18916 (pi->nphy_rccal_value | 0x80));
18918 pi->nphy_anarxlpf_adjusted = false;
18925 wlc_phy_adjust_min_noisevar_nphy(struct brcms_phy *pi, int ntones,
18932 CHSPEC_IS40(pi->radio_chanspec) ?
18935 if (pi->nphy_noisevars_adjusted) {
18936 for (i = 0; i < pi->nphy_saved_noisevars.bufcount; i++) {
18937 tone_id = pi->nphy_saved_noisevars.tone_id[i];
18942 pi, NPHY_TBL_ID_NOISEVAR, 1,
18944 &pi->nphy_saved_noisevars.min_noise_vars[i]);
18947 pi->nphy_saved_noisevars.bufcount = 0;
18948 pi->nphy_noisevars_adjusted = false;
18952 pi->nphy_saved_noisevars.bufcount = 0;
18959 pi->nphy_saved_noisevars.tone_id[i] = tone_id;
18960 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
18962 &pi->nphy_saved_noisevars.
18964 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
18966 pi->nphy_saved_noisevars.bufcount++;
18969 pi->nphy_noisevars_adjusted = true;
18973 static void wlc_phy_adjust_crsminpwr_nphy(struct brcms_phy *pi, u8 minpwr)
18977 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
18978 if ((CHSPEC_CHANNEL(pi->radio_chanspec) == 11) &&
18979 CHSPEC_IS40(pi->radio_chanspec)) {
18980 if (!pi->nphy_crsminpwr_adjusted) {
18981 regval = read_phy_reg(pi, 0x27d);
18982 pi->nphy_crsminpwr[0] = regval & 0xff;
18985 write_phy_reg(pi, 0x27d, regval);
18987 regval = read_phy_reg(pi, 0x280);
18988 pi->nphy_crsminpwr[1] = regval & 0xff;
18991 write_phy_reg(pi, 0x280, regval);
18993 regval = read_phy_reg(pi, 0x283);
18994 pi->nphy_crsminpwr[2] = regval & 0xff;
18997 write_phy_reg(pi, 0x283, regval);
18999 pi->nphy_crsminpwr_adjusted = true;
19002 if (pi->nphy_crsminpwr_adjusted) {
19003 regval = read_phy_reg(pi, 0x27d);
19005 regval |= pi->nphy_crsminpwr[0];
19006 write_phy_reg(pi, 0x27d, regval);
19008 regval = read_phy_reg(pi, 0x280);
19010 regval |= pi->nphy_crsminpwr[1];
19011 write_phy_reg(pi, 0x280, regval);
19013 regval = read_phy_reg(pi, 0x283);
19015 regval |= pi->nphy_crsminpwr[2];
19016 write_phy_reg(pi, 0x283, regval);
19018 pi->nphy_crsminpwr_adjusted = false;
19024 static void wlc_phy_spurwar_nphy(struct brcms_phy *pi)
19032 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
19033 if (pi->phyhang_avoid)
19034 wlc_phy_stay_in_carriersearch_nphy(pi, true);
19036 cur_channel = CHSPEC_CHANNEL(pi->radio_chanspec);
19038 if (pi->nphy_gband_spurwar_en) {
19041 pi,
19044 if (CHSPEC_IS2G(pi->radio_chanspec)) {
19046 && CHSPEC_IS40(pi->radio_chanspec))
19048 pi, 2,
19052 wlc_phy_adjust_min_noisevar_nphy(pi, 0,
19057 wlc_phy_adjust_crsminpwr_nphy(pi,
19061 if ((pi->nphy_gband_spurwar2_en)
19062 && CHSPEC_IS2G(pi->radio_chanspec)) {
19064 if (CHSPEC_IS40(pi->radio_chanspec)) {
19132 pi,
19137 wlc_phy_adjust_min_noisevar_nphy(pi, 0, NULL,
19142 if ((pi->nphy_aband_spurwar_en) &&
19143 (CHSPEC_IS5G(pi->radio_chanspec))) {
19152 if ((pi->sh->chip == BCMA_CHIP_ID_BCM4716) &&
19153 (pi->sh->chippkg == BCMA_PKG_ID_BCM4717)) {
19183 pi, 1,
19187 wlc_phy_adjust_min_noisevar_nphy(pi, 0, NULL,
19191 if (pi->phyhang_avoid)
19192 wlc_phy_stay_in_carriersearch_nphy(pi, false);
19196 void wlc_phy_init_nphy(struct brcms_phy *pi)
19209 if (!(pi->measure_hold & PHY_HOLD_FOR_SCAN))
19210 pi->measure_hold |= PHY_HOLD_FOR_NOT_ASSOC;
19212 if ((ISNPHY(pi)) && (NREV_GE(pi->pubpi.phy_rev, 5)) &&
19213 ((pi->sh->chippkg == BCMA_PKG_ID_BCM4717) ||
19214 (pi->sh->chippkg == BCMA_PKG_ID_BCM4718))) {
19215 if ((pi->sh->boardflags & BFL_EXTLNA) &&
19216 (CHSPEC_IS2G(pi->radio_chanspec)))
19217 bcma_cc_set32(&pi->d11core->bus->drv_cc,
19221 if ((!PHY_IPA(pi)) && (pi->sh->chip == BCMA_CHIP_ID_BCM5357))
19222 bcma_chipco_chipctl_maskset(&pi->d11core->bus->drv_cc, 1,
19225 if ((pi->nphy_gband_spurwar2_en) && CHSPEC_IS2G(pi->radio_chanspec) &&
19226 CHSPEC_IS40(pi->radio_chanspec)) {
19228 d11_clk_ctl_st = bcma_read32(pi->d11core,
19230 bcma_mask32(pi->d11core, D11REGOFFS(clk_ctl_st),
19233 bcma_write32(pi->d11core, D11REGOFFS(clk_ctl_st),
19237 pi->use_int_tx_iqlo_cal_nphy =
19238 (PHY_IPA(pi) ||
19239 (NREV_GE(pi->pubpi.phy_rev, 7) ||
19240 (NREV_GE(pi->pubpi.phy_rev, 5)
19241 && pi->sh->boardflags2 & BFL2_INTERNDET_TXIQCAL)));
19243 pi->internal_tx_iqlo_cal_tapoff_intpa_nphy = false;
19245 pi->nphy_deaf_count = 0;
19247 wlc_phy_tbl_init_nphy(pi);
19249 pi->nphy_crsminpwr_adjusted = false;
19250 pi->nphy_noisevars_adjusted = false;
19252 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
19253 write_phy_reg(pi, 0xe7, 0);
19254 write_phy_reg(pi, 0xec, 0);
19255 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
19256 write_phy_reg(pi, 0x342, 0);
19257 write_phy_reg(pi, 0x343, 0);
19258 write_phy_reg(pi, 0x346, 0);
19259 write_phy_reg(pi, 0x347, 0);
19261 write_phy_reg(pi, 0xe5, 0);
19262 write_phy_reg(pi, 0xe6, 0);
19264 write_phy_reg(pi, 0xec, 0);
19267 write_phy_reg(pi, 0x91, 0);
19268 write_phy_reg(pi, 0x92, 0);
19269 if (NREV_LT(pi->pubpi.phy_rev, 6)) {
19270 write_phy_reg(pi, 0x93, 0);
19271 write_phy_reg(pi, 0x94, 0);
19274 and_phy_reg(pi, 0xa1, ~3);
19276 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
19277 write_phy_reg(pi, 0x8f, 0);
19278 write_phy_reg(pi, 0xa5, 0);
19280 write_phy_reg(pi, 0xa5, 0);
19283 if (NREV_IS(pi->pubpi.phy_rev, 2))
19284 mod_phy_reg(pi, 0xdc, 0x00ff, 0x3b);
19285 else if (NREV_LT(pi->pubpi.phy_rev, 2))
19286 mod_phy_reg(pi, 0xdc, 0x00ff, 0x40);
19288 write_phy_reg(pi, 0x203, 32);
19289 write_phy_reg(pi, 0x201, 32);
19291 if (pi->sh->boardflags2 & BFL2_SKWRKFEM_BRD)
19292 write_phy_reg(pi, 0x20d, 160);
19294 write_phy_reg(pi, 0x20d, 184);
19296 write_phy_reg(pi, 0x13a, 200);
19298 write_phy_reg(pi, 0x70, 80);
19300 write_phy_reg(pi, 0x1ff, 48);
19302 if (NREV_LT(pi->pubpi.phy_rev, 8))
19303 wlc_phy_update_mimoconfig_nphy(pi, pi->n_preamble_override);
19305 wlc_phy_stf_chain_upd_nphy(pi);
19307 if (NREV_LT(pi->pubpi.phy_rev, 2)) {
19308 write_phy_reg(pi, 0x180, 0xaa8);
19309 write_phy_reg(pi, 0x181, 0x9a4);
19312 if (PHY_IPA(pi)) {
19313 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
19315 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
19318 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x298 :
19320 (pi->nphy_papd_epsilon_offset[core]) << 7);
19324 wlc_phy_ipa_set_tx_digi_filts_nphy(pi);
19325 } else if (NREV_GE(pi->pubpi.phy_rev, 5)) {
19326 wlc_phy_extpa_set_tx_digi_filts_nphy(pi);
19329 wlc_phy_workarounds_nphy(pi);
19331 wlapi_bmac_phyclk_fgc(pi->sh->physhim, ON);
19333 val = read_phy_reg(pi, 0x01);
19334 write_phy_reg(pi, 0x01, val | BBCFG_RESETCCA);
19335 write_phy_reg(pi, 0x01, val & (~BBCFG_RESETCCA));
19336 wlapi_bmac_phyclk_fgc(pi->sh->physhim, OFF);
19338 wlapi_bmac_macphyclk_set(pi->sh->physhim, ON);
19340 wlc_phy_pa_override_nphy(pi, OFF);
19341 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX);
19342 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
19343 wlc_phy_pa_override_nphy(pi, ON);
19345 wlc_phy_classifier_nphy(pi, 0, 0);
19346 wlc_phy_clip_det_nphy(pi, 0, clip1_ths);
19348 if (CHSPEC_IS2G(pi->radio_chanspec))
19349 wlc_phy_bphy_init_nphy(pi);
19351 tx_pwr_ctrl_state = pi->nphy_txpwrctrl;
19352 wlc_phy_txpwrctrl_enable_nphy(pi, PHY_TPC_HW_OFF);
19354 wlc_phy_txpwr_fixpower_nphy(pi);
19356 wlc_phy_txpwrctrl_idle_tssi_nphy(pi);
19358 wlc_phy_txpwrctrl_pwr_setup_nphy(pi);
19360 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
19367 if (PHY_IPA(pi)) {
19368 tx_pwrctrl_tbl = wlc_phy_get_ipa_gaintbl_nphy(pi);
19370 if (CHSPEC_IS5G(pi->radio_chanspec)) {
19371 if (NREV_IS(pi->pubpi.phy_rev, 3))
19374 else if (NREV_IS(pi->pubpi.phy_rev, 4))
19376 (pi->srom_fem5g.extpagain ==
19384 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
19385 if (pi->pubpi.radiorev == 5)
19388 else if (pi->pubpi.radiorev == 3)
19392 if (NREV_GE(pi->pubpi.phy_rev, 5) &&
19393 (pi->srom_fem2g.extpagain == 3))
19403 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 128,
19405 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 128,
19408 pi->nphy_gmval = (u16) ((*tx_pwrctrl_tbl >> 16) & 0x7000);
19410 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
19415 rfpwr_offset = get_rf_pwr_offset(pi, pga_gn,
19418 pi,
19423 pi,
19432 if (CHSPEC_IS2G(pi->radio_chanspec))
19442 pi,
19447 pi,
19456 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 128,
19458 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 128,
19462 if (pi->sh->phyrxchain != 0x3)
19463 wlc_phy_rxcore_setstate_nphy((struct brcms_phy_pub *) pi,
19464 pi->sh->phyrxchain);
19466 if (PHY_PERICAL_MPHASE_PENDING(pi))
19467 wlc_phy_cal_perical_mphase_restart(pi);
19469 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
19470 do_rssi_cal = (CHSPEC_IS2G(pi->radio_chanspec)) ?
19471 (pi->nphy_rssical_chanspec_2G == 0) :
19472 (pi->nphy_rssical_chanspec_5G == 0);
19475 wlc_phy_rssi_cal_nphy(pi);
19477 wlc_phy_restore_rssical_nphy(pi);
19479 wlc_phy_rssi_cal_nphy(pi);
19482 if (!SCAN_RM_IN_PROGRESS(pi))
19483 do_nphy_cal = (CHSPEC_IS2G(pi->radio_chanspec)) ?
19484 (pi->nphy_iqcal_chanspec_2G == 0) :
19485 (pi->nphy_iqcal_chanspec_5G == 0);
19487 if (!pi->do_initcal)
19492 target_gain = wlc_phy_get_tx_gain_nphy(pi);
19494 if (pi->antsel_type == ANTSEL_2x3)
19495 wlc_phy_antsel_init((struct brcms_phy_pub *) pi,
19498 if (pi->nphy_perical != PHY_PERICAL_MPHASE) {
19499 wlc_phy_rssi_cal_nphy(pi);
19501 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
19502 pi->nphy_cal_orig_pwr_idx[0] =
19503 pi->nphy_txpwrindex[PHY_CORE_0]
19506 pi->nphy_cal_orig_pwr_idx[1] =
19507 pi->nphy_txpwrindex[PHY_CORE_1]
19511 wlc_phy_precal_txgain_nphy(pi);
19513 wlc_phy_get_tx_gain_nphy(pi);
19517 (pi, target_gain, true,
19520 (pi, target_gain, 2,
19522 wlc_phy_savecal_nphy(pi);
19525 } else if (pi->mphase_cal_phase_id ==
19527 wlc_phy_cal_perical((struct brcms_phy_pub *) pi,
19531 wlc_phy_restorecal_nphy(pi);
19534 wlc_phy_txpwrctrl_coeff_setup_nphy(pi);
19536 wlc_phy_txpwrctrl_enable_nphy(pi, tx_pwr_ctrl_state);
19538 wlc_phy_nphy_tkip_rifs_war(pi, pi->sh->_rifs_phy);
19540 if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LE(pi->pubpi.phy_rev, 6))
19542 write_phy_reg(pi, 0x70, 50);
19544 wlc_phy_txlpfbw_nphy(pi);
19546 wlc_phy_spurwar_nphy(pi);
19550 static void wlc_phy_resetcca_nphy(struct brcms_phy *pi)
19554 wlapi_bmac_phyclk_fgc(pi->sh->physhim, ON);
19556 val = read_phy_reg(pi, 0x01);
19557 write_phy_reg(pi, 0x01, val | BBCFG_RESETCCA);
19559 write_phy_reg(pi, 0x01, val & (~BBCFG_RESETCCA));
19561 wlapi_bmac_phyclk_fgc(pi->sh->physhim, OFF);
19563 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
19566 void wlc_phy_pa_override_nphy(struct brcms_phy *pi, bool en)
19572 pi->rfctrlIntc1_save = read_phy_reg(pi, 0x91);
19573 pi->rfctrlIntc2_save = read_phy_reg(pi, 0x92);
19575 if (NREV_GE(pi->pubpi.phy_rev, 7))
19577 else if (NREV_GE(pi->pubpi.phy_rev, 3))
19579 CHSPEC_IS5G(pi->radio_chanspec) ? 0x600 : 0x480;
19582 CHSPEC_IS5G(pi->radio_chanspec) ? 0x180 : 0x120;
19584 write_phy_reg(pi, 0x91, rfctrlintc_override_val);
19585 write_phy_reg(pi, 0x92, rfctrlintc_override_val);
19587 write_phy_reg(pi, 0x91, pi->rfctrlIntc1_save);
19588 write_phy_reg(pi, 0x92, pi->rfctrlIntc2_save);
19593 void wlc_phy_stf_chain_upd_nphy(struct brcms_phy *pi)
19600 if (pi->nphy_txrx_chain == BRCMS_N_TXRX_CHAIN0) {
19604 if (NREV_LE(pi->pubpi.phy_rev, 2))
19605 and_phy_reg(pi, 0xa0, ~0x20);
19606 } else if (pi->nphy_txrx_chain == BRCMS_N_TXRX_CHAIN1) {
19610 if (NREV_LE(pi->pubpi.phy_rev, 2))
19611 or_phy_reg(pi, 0xa0, 0x20);
19614 mod_phy_reg(pi, 0xa2, ((0xf << 0) | (0xf << 4)), txrx_chain);
19617 pi->nphy_perical = PHY_PERICAL_DISABLE;
19618 or_phy_reg(pi, 0xa1, NPHY_RfseqMode_CoreActv_override);
19620 pi->nphy_perical = PHY_PERICAL_MPHASE;
19621 and_phy_reg(pi, 0xa1, ~NPHY_RfseqMode_CoreActv_override);
19630 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
19634 pi->sh->phyrxchain = rxcore_bitmask;
19636 if (!pi->sh->clk)
19639 suspend = (0 == (bcma_read32(pi->d11core, D11REGOFFS(maccontrol)) &
19642 wlapi_suspend_mac_and_wait(pi->sh->physhim);
19644 if (pi->phyhang_avoid)
19645 wlc_phy_stay_in_carriersearch_nphy(pi, true);
19647 regval = read_phy_reg(pi, 0xa2);
19650 write_phy_reg(pi, 0xa2, regval);
19654 write_phy_reg(pi, 0x20e, 1);
19656 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
19657 if (pi->rx2tx_biasentry == -1) {
19658 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ,
19665 pi->rx2tx_biasentry = (u8) i;
19669 pi,
19683 write_phy_reg(pi, 0x20e, 30);
19685 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
19686 if (pi->rx2tx_biasentry != -1) {
19688 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
19689 1, pi->rx2tx_biasentry,
19691 pi->rx2tx_biasentry = -1;
19696 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
19698 if (pi->phyhang_avoid)
19699 wlc_phy_stay_in_carriersearch_nphy(pi, false);
19702 wlapi_enable_mac(pi->sh->physhim);
19708 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
19710 regval = read_phy_reg(pi, 0xa2);
19716 bool wlc_phy_n_txpower_ipa_ison(struct brcms_phy *pi)
19718 return PHY_IPA(pi);
19721 void wlc_phy_cal_init_nphy(struct brcms_phy *pi)
19725 static void wlc_phy_radio_preinit_205x(struct brcms_phy *pi)
19728 and_phy_reg(pi, 0x78, ~RFCC_CHIP0_PU);
19729 and_phy_reg(pi, 0x78, RFCC_OE_POR_FORCE);
19731 or_phy_reg(pi, 0x78, ~RFCC_OE_POR_FORCE);
19732 or_phy_reg(pi, 0x78, RFCC_CHIP0_PU);
19736 static void wlc_phy_radio_init_2057(struct brcms_phy *pi)
19740 if (NREV_IS(pi->pubpi.phy_rev, 7)) {
19742 } else if (NREV_IS(pi->pubpi.phy_rev, 8)
19743 || NREV_IS(pi->pubpi.phy_rev, 9)) {
19744 switch (pi->pubpi.radiorev) {
19747 if (NREV_IS(pi->pubpi.phy_rev, 8))
19749 else if (NREV_IS(pi->pubpi.phy_rev, 9))
19768 wlc_phy_init_radio_regs_allbands(pi, regs_2057_ptr);
19771 static u16 wlc_phy_radio205x_rcal(struct brcms_phy *pi)
19776 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
19778 if (pi->pubpi.radiorev == 5) {
19780 and_phy_reg(pi, 0x342, ~(0x1 << 1));
19784 mod_radio_reg(pi, RADIO_2057_IQTEST_SEL_PU, 0x1, 0x1);
19785 mod_radio_reg(pi, RADIO_2057v7_IQTEST_SEL_PU2, 0x2,
19788 mod_radio_reg(pi, RADIO_2057_RCAL_CONFIG, 0x1, 0x1);
19792 mod_radio_reg(pi, RADIO_2057_RCAL_CONFIG, 0x3, 0x3);
19795 rcal_reg = read_radio_reg(pi, RADIO_2057_RCAL_STATUS);
19806 mod_radio_reg(pi, RADIO_2057_RCAL_CONFIG, 0x2, 0x0);
19808 rcal_reg = read_radio_reg(pi, RADIO_2057_RCAL_STATUS) & 0x3e;
19810 mod_radio_reg(pi, RADIO_2057_RCAL_CONFIG, 0x1, 0x0);
19811 if (pi->pubpi.radiorev == 5) {
19813 mod_radio_reg(pi, RADIO_2057_IQTEST_SEL_PU, 0x1, 0x0);
19814 mod_radio_reg(pi, RADIO_2057v7_IQTEST_SEL_PU2, 0x2,
19818 if ((pi->pubpi.radiorev <= 4) || (pi->pubpi.radiorev == 6)) {
19820 mod_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG, 0x3c,
19822 mod_radio_reg(pi, RADIO_2057_BANDGAP_RCAL_TRIM, 0xf0,
19826 } else if (NREV_IS(pi->pubpi.phy_rev, 3)) {
19831 pi,
19834 write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST2 | RADIO_2056_SYN,
19838 write_radio_reg(pi, RADIO_2056_SYN_RCAL_MASTER | RADIO_2056_SYN,
19842 write_radio_reg(pi, RADIO_2056_SYN_RCAL_MASTER | RADIO_2056_SYN,
19847 pi,
19860 write_radio_reg(pi, RADIO_2056_SYN_RCAL_MASTER | RADIO_2056_SYN,
19864 read_radio_reg(pi,
19868 write_radio_reg(pi, RADIO_2056_SYN_RCAL_MASTER | RADIO_2056_SYN,
19871 write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST2 | RADIO_2056_SYN,
19879 static u16 wlc_phy_radio2057_rccal(struct brcms_phy *pi)
19885 chip43226_6362A0 = ((pi->pubpi.radiorev == 3)
19886 || (pi->pubpi.radiorev == 4)
19887 || (pi->pubpi.radiorev == 6));
19891 write_radio_reg(pi, RADIO_2057_RCCAL_MASTER, 0x61);
19892 write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xc0);
19894 write_radio_reg(pi, RADIO_2057v7_RCCAL_MASTER, 0x61);
19896 write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xe9);
19898 write_radio_reg(pi, RADIO_2057_RCCAL_X1, 0x6e);
19899 write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x55);
19902 rccal_valid = read_radio_reg(pi, RADIO_2057_RCCAL_DONE_OSCCAP);
19909 write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x15);
19913 write_radio_reg(pi, RADIO_2057_RCCAL_MASTER, 0x69);
19914 write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xb0);
19916 write_radio_reg(pi, RADIO_2057v7_RCCAL_MASTER, 0x69);
19918 write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xd5);
19920 write_radio_reg(pi, RADIO_2057_RCCAL_X1, 0x6e);
19921 write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x55);
19924 rccal_valid = read_radio_reg(pi, RADIO_2057_RCCAL_DONE_OSCCAP);
19931 write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x15);
19935 write_radio_reg(pi, RADIO_2057_RCCAL_MASTER, 0x73);
19937 write_radio_reg(pi, RADIO_2057_RCCAL_X1, 0x28);
19938 write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xb0);
19940 write_radio_reg(pi, RADIO_2057v7_RCCAL_MASTER, 0x73);
19941 write_radio_reg(pi, RADIO_2057_RCCAL_X1, 0x6e);
19942 write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0x99);
19944 write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x55);
19947 rccal_valid = read_radio_reg(pi, RADIO_2057_RCCAL_DONE_OSCCAP);
19957 write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x15);
19962 static void wlc_phy_radio_postinit_2057(struct brcms_phy *pi)
19965 mod_radio_reg(pi, RADIO_2057_XTALPUOVR_PINCTRL, 0x1, 0x1);
19967 mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_CAL_RESETN, 0x78, 0x78);
19968 mod_radio_reg(pi, RADIO_2057_XTAL_CONFIG2, 0x80, 0x80);
19970 mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_CAL_RESETN, 0x78, 0x0);
19971 mod_radio_reg(pi, RADIO_2057_XTAL_CONFIG2, 0x80, 0x0);
19973 if (pi->phy_init_por) {
19974 wlc_phy_radio205x_rcal(pi);
19975 wlc_phy_radio2057_rccal(pi);
19978 mod_radio_reg(pi, RADIO_2057_RFPLL_MASTER, 0x8, 0x0);
19981 static void wlc_phy_radio_init_2056(struct brcms_phy *pi)
19987 if (NREV_IS(pi->pubpi.phy_rev, 3)) {
19991 } else if (NREV_IS(pi->pubpi.phy_rev, 4)) {
19996 switch (pi->pubpi.radiorev) {
20033 wlc_phy_init_radio_regs(pi, regs_SYN_2056_ptr, (u16) RADIO_2056_SYN);
20035 wlc_phy_init_radio_regs(pi, regs_TX_2056_ptr, (u16) RADIO_2056_TX0);
20037 wlc_phy_init_radio_regs(pi, regs_TX_2056_ptr, (u16) RADIO_2056_TX1);
20039 wlc_phy_init_radio_regs(pi, regs_RX_2056_ptr, (u16) RADIO_2056_RX0);
20041 wlc_phy_init_radio_regs(pi, regs_RX_2056_ptr, (u16) RADIO_2056_RX1);
20044 static void wlc_phy_radio_postinit_2056(struct brcms_phy *pi)
20046 mod_radio_reg(pi, RADIO_2056_SYN_COM_CTRL, 0xb, 0xb);
20048 mod_radio_reg(pi, RADIO_2056_SYN_COM_PU, 0x2, 0x2);
20049 mod_radio_reg(pi, RADIO_2056_SYN_COM_RESET, 0x2, 0x2);
20051 mod_radio_reg(pi, RADIO_2056_SYN_COM_RESET, 0x2, 0x0);
20053 if ((pi->sh->boardflags2 & BFL2_LEGACY)
20054 || (pi->sh->boardflags2 & BFL2_XTALBUFOUTEN))
20055 mod_radio_reg(pi, RADIO_2056_SYN_PLL_MAST2, 0xf4, 0x0);
20057 mod_radio_reg(pi, RADIO_2056_SYN_PLL_MAST2, 0xfc, 0x0);
20059 mod_radio_reg(pi, RADIO_2056_SYN_RCCAL_CTRL0, 0x1, 0x0);
20061 if (pi->phy_init_por)
20062 wlc_phy_radio205x_rcal(pi);
20065 static void wlc_phy_radio_preinit_2055(struct brcms_phy *pi)
20068 and_phy_reg(pi, 0x78, ~RFCC_POR_FORCE);
20069 or_phy_reg(pi, 0x78, RFCC_CHIP0_PU | RFCC_OE_POR_FORCE);
20071 or_phy_reg(pi, 0x78, RFCC_POR_FORCE);
20074 static void wlc_phy_radio_init_2055(struct brcms_phy *pi)
20076 wlc_phy_init_radio_regs(pi, regs_2055, RADIO_DEFAULT_CORE);
20079 static void wlc_phy_radio_postinit_2055(struct brcms_phy *pi)
20082 and_radio_reg(pi, RADIO_2055_MASTER_CNTRL1,
20085 if (((pi->sh->sromrev >= 4)
20086 && !(pi->sh->boardflags2 & BFL2_RXBB_INT_REG_DIS))
20087 || ((pi->sh->sromrev < 4))) {
20088 and_radio_reg(pi, RADIO_2055_CORE1_RXBB_REGULATOR, 0x7F);
20089 and_radio_reg(pi, RADIO_2055_CORE2_RXBB_REGULATOR, 0x7F);
20092 mod_radio_reg(pi, RADIO_2055_RRCCAL_N_OPT_SEL, 0x3F, 0x2C);
20093 write_radio_reg(pi, RADIO_2055_CAL_MISC, 0x3C);
20095 and_radio_reg(pi, RADIO_2055_CAL_MISC,
20098 or_radio_reg(pi, RADIO_2055_CAL_LPO_CNTRL, RADIO_2055_CAL_LPO_ENABLE);
20100 or_radio_reg(pi, RADIO_2055_CAL_MISC, RADIO_2055_RRCAL_RST_N);
20104 or_radio_reg(pi, RADIO_2055_CAL_MISC, RADIO_2055_RRCAL_START);
20106 SPINWAIT(((read_radio_reg(pi, RADIO_2055_CAL_COUNTER_OUT2) &
20109 if (WARN((read_radio_reg(pi, RADIO_2055_CAL_COUNTER_OUT2) &
20114 and_radio_reg(pi, RADIO_2055_CAL_LPO_CNTRL,
20117 wlc_phy_chanspec_set((struct brcms_phy_pub *) pi, pi->radio_chanspec);
20119 write_radio_reg(pi, RADIO_2055_CORE1_RXBB_LPF, 9);
20120 write_radio_reg(pi, RADIO_2055_CORE2_RXBB_LPF, 9);
20122 write_radio_reg(pi, RADIO_2055_CORE1_RXBB_MIDAC_HIPAS, 0x83);
20123 write_radio_reg(pi, RADIO_2055_CORE2_RXBB_MIDAC_HIPAS, 0x83);
20125 mod_radio_reg(pi, RADIO_2055_CORE1_LNA_GAINBST,
20127 mod_radio_reg(pi, RADIO_2055_CORE2_LNA_GAINBST,
20129 if (pi->nphy_gain_boost) {
20130 and_radio_reg(pi, RADIO_2055_CORE1_RXRF_SPC1,
20132 and_radio_reg(pi, RADIO_2055_CORE2_RXRF_SPC1,
20135 or_radio_reg(pi, RADIO_2055_CORE1_RXRF_SPC1,
20137 or_radio_reg(pi, RADIO_2055_CORE2_RXRF_SPC1,
20144 void wlc_phy_switch_radio_nphy(struct brcms_phy *pi, bool on)
20147 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
20148 if (!pi->radio_is_on) {
20149 wlc_phy_radio_preinit_205x(pi);
20150 wlc_phy_radio_init_2057(pi);
20151 wlc_phy_radio_postinit_2057(pi);
20154 wlc_phy_chanspec_set((struct brcms_phy_pub *) pi,
20155 pi->radio_chanspec);
20156 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
20157 wlc_phy_radio_preinit_205x(pi);
20158 wlc_phy_radio_init_2056(pi);
20159 wlc_phy_radio_postinit_2056(pi);
20161 wlc_phy_chanspec_set((struct brcms_phy_pub *) pi,
20162 pi->radio_chanspec);
20164 wlc_phy_radio_preinit_2055(pi);
20165 wlc_phy_radio_init_2055(pi);
20166 wlc_phy_radio_postinit_2055(pi);
20169 pi->radio_is_on = true;
20173 if (NREV_GE(pi->pubpi.phy_rev, 3)
20174 && NREV_LT(pi->pubpi.phy_rev, 7)) {
20175 and_phy_reg(pi, 0x78, ~RFCC_CHIP0_PU);
20176 mod_radio_reg(pi, RADIO_2056_SYN_COM_PU, 0x2, 0x0);
20178 write_radio_reg(pi,
20181 write_radio_reg(pi,
20184 write_radio_reg(pi,
20187 write_radio_reg(pi,
20190 mod_radio_reg(pi,
20193 write_radio_reg(pi,
20197 write_radio_reg(pi,
20200 write_radio_reg(pi,
20203 write_radio_reg(pi,
20206 write_radio_reg(pi,
20209 mod_radio_reg(pi,
20212 write_radio_reg(pi,
20216 pi->radio_is_on = false;
20219 if (NREV_GE(pi->pubpi.phy_rev, 8)) {
20220 and_phy_reg(pi, 0x78, ~RFCC_CHIP0_PU);
20221 pi->radio_is_on = false;
20228 wlc_phy_chan2freq_nphy(struct brcms_phy *pi, uint channel, int *f,
20242 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
20244 if (NREV_IS(pi->pubpi.phy_rev, 7)) {
20249 } else if (NREV_IS(pi->pubpi.phy_rev, 8)
20250 || NREV_IS(pi->pubpi.phy_rev, 9)) {
20251 switch (pi->pubpi.radiorev) {
20255 if (pi->pubpi.radiover == 0x0) {
20262 } else if (pi->pubpi.radiover == 0x1) {
20289 } else if (NREV_IS(pi->pubpi.phy_rev, 16)) {
20298 if (pi->pubpi.radiorev == 5) {
20312 if (pi->pubpi.radiorev == 5) {
20320 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
20321 if (NREV_IS(pi->pubpi.phy_rev, 3)) {
20324 } else if (NREV_IS(pi->pubpi.phy_rev, 4)) {
20327 } else if (NREV_IS(pi->pubpi.phy_rev, 5)
20328 || NREV_IS(pi->pubpi.phy_rev, 6)) {
20329 switch (pi->pubpi.radiorev) {
20389 u8 wlc_phy_get_chan_freq_range_nphy(struct brcms_phy *pi, uint channel)
20398 channel = CHSPEC_CHANNEL(pi->radio_chanspec);
20400 wlc_phy_chan2freq_nphy(pi, channel, &freq, &t0, &t1, &t2, &t3);
20402 if (CHSPEC_IS2G(pi->radio_chanspec))
20414 wlc_phy_chanspec_radio2055_setup(struct brcms_phy *pi,
20418 write_radio_reg(pi, RADIO_2055_PLL_REF, ci->RF_pll_ref);
20419 write_radio_reg(pi, RADIO_2055_RF_PLL_MOD0, ci->RF_rf_pll_mod0);
20420 write_radio_reg(pi, RADIO_2055_RF_PLL_MOD1, ci->RF_rf_pll_mod1);
20421 write_radio_reg(pi, RADIO_2055_VCO_CAP_TAIL, ci->RF_vco_cap_tail);
20423 BRCMS_PHY_WAR_PR51571(pi);
20425 write_radio_reg(pi, RADIO_2055_VCO_CAL1, ci->RF_vco_cal1);
20426 write_radio_reg(pi, RADIO_2055_VCO_CAL2, ci->RF_vco_cal2);
20427 write_radio_reg(pi, RADIO_2055_PLL_LF_C1, ci->RF_pll_lf_c1);
20428 write_radio_reg(pi, RADIO_2055_PLL_LF_R1, ci->RF_pll_lf_r1);
20430 BRCMS_PHY_WAR_PR51571(pi);
20432 write_radio_reg(pi, RADIO_2055_PLL_LF_C2, ci->RF_pll_lf_c2);
20433 write_radio_reg(pi, RADIO_2055_LGBUF_CEN_BUF, ci->RF_lgbuf_cen_buf);
20434 write_radio_reg(pi, RADIO_2055_LGEN_TUNE1, ci->RF_lgen_tune1);
20435 write_radio_reg(pi, RADIO_2055_LGEN_TUNE2, ci->RF_lgen_tune2);
20437 BRCMS_PHY_WAR_PR51571(pi);
20439 write_radio_reg(pi, RADIO_2055_CORE1_LGBUF_A_TUNE,
20441 write_radio_reg(pi, RADIO_2055_CORE1_LGBUF_G_TUNE,
20443 write_radio_reg(pi, RADIO_2055_CORE1_RXRF_REG1, ci->RF_core1_rxrf_reg1);
20444 write_radio_reg(pi, RADIO_2055_CORE1_TX_PGA_PAD_TN,
20447 BRCMS_PHY_WAR_PR51571(pi);
20449 write_radio_reg(pi, RADIO_2055_CORE1_TX_MX_BGTRIM,
20451 write_radio_reg(pi, RADIO_2055_CORE2_LGBUF_A_TUNE,
20453 write_radio_reg(pi, RADIO_2055_CORE2_LGBUF_G_TUNE,
20455 write_radio_reg(pi, RADIO_2055_CORE2_RXRF_REG1, ci->RF_core2_rxrf_reg1);
20457 BRCMS_PHY_WAR_PR51571(pi);
20459 write_radio_reg(pi, RADIO_2055_CORE2_TX_PGA_PAD_TN,
20461 write_radio_reg(pi, RADIO_2055_CORE2_TX_MX_BGTRIM,
20466 write_radio_reg(pi, RADIO_2055_VCO_CAL10, 0x05);
20467 write_radio_reg(pi, RADIO_2055_VCO_CAL10, 0x45);
20469 BRCMS_PHY_WAR_PR51571(pi);
20471 write_radio_reg(pi, RADIO_2055_VCO_CAL10, 0x65);
20477 wlc_phy_chanspec_radio2056_setup(struct brcms_phy *pi,
20482 write_radio_reg(pi,
20485 write_radio_reg(pi, RADIO_2056_SYN_PLL_VCOCAL2 | RADIO_2056_SYN,
20487 write_radio_reg(pi, RADIO_2056_SYN_PLL_REFDIV | RADIO_2056_SYN,
20489 write_radio_reg(pi, RADIO_2056_SYN_PLL_MMD2 | RADIO_2056_SYN,
20491 write_radio_reg(pi, RADIO_2056_SYN_PLL_MMD1 | RADIO_2056_SYN,
20493 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER1 | RADIO_2056_SYN,
20495 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER2 | RADIO_2056_SYN,
20497 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER3 | RADIO_2056_SYN,
20499 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER4 | RADIO_2056_SYN,
20501 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER5 | RADIO_2056_SYN,
20503 write_radio_reg(pi, RADIO_2056_SYN_RESERVED_ADDR27 | RADIO_2056_SYN,
20505 write_radio_reg(pi, RADIO_2056_SYN_RESERVED_ADDR28 | RADIO_2056_SYN,
20507 write_radio_reg(pi, RADIO_2056_SYN_RESERVED_ADDR29 | RADIO_2056_SYN,
20509 write_radio_reg(pi, RADIO_2056_SYN_LOGEN_VCOBUF1 | RADIO_2056_SYN,
20511 write_radio_reg(pi, RADIO_2056_SYN_LOGEN_MIXER2 | RADIO_2056_SYN,
20513 write_radio_reg(pi, RADIO_2056_SYN_LOGEN_BUF3 | RADIO_2056_SYN,
20515 write_radio_reg(pi, RADIO_2056_SYN_LOGEN_BUF4 | RADIO_2056_SYN,
20518 write_radio_reg(pi,
20521 write_radio_reg(pi, RADIO_2056_RX_LNAG_TUNE | RADIO_2056_RX0,
20523 write_radio_reg(pi, RADIO_2056_TX_INTPAA_BOOST_TUNE | RADIO_2056_TX0,
20525 write_radio_reg(pi, RADIO_2056_TX_INTPAG_BOOST_TUNE | RADIO_2056_TX0,
20527 write_radio_reg(pi, RADIO_2056_TX_PADA_BOOST_TUNE | RADIO_2056_TX0,
20529 write_radio_reg(pi, RADIO_2056_TX_PADG_BOOST_TUNE | RADIO_2056_TX0,
20531 write_radio_reg(pi, RADIO_2056_TX_PGAA_BOOST_TUNE | RADIO_2056_TX0,
20533 write_radio_reg(pi, RADIO_2056_TX_PGAG_BOOST_TUNE | RADIO_2056_TX0,
20535 write_radio_reg(pi, RADIO_2056_TX_MIXA_BOOST_TUNE | RADIO_2056_TX0,
20537 write_radio_reg(pi, RADIO_2056_TX_MIXG_BOOST_TUNE | RADIO_2056_TX0,
20540 write_radio_reg(pi,
20543 write_radio_reg(pi, RADIO_2056_RX_LNAG_TUNE | RADIO_2056_RX1,
20545 write_radio_reg(pi, RADIO_2056_TX_INTPAA_BOOST_TUNE | RADIO_2056_TX1,
20547 write_radio_reg(pi, RADIO_2056_TX_INTPAG_BOOST_TUNE | RADIO_2056_TX1,
20549 write_radio_reg(pi, RADIO_2056_TX_PADA_BOOST_TUNE | RADIO_2056_TX1,
20551 write_radio_reg(pi, RADIO_2056_TX_PADG_BOOST_TUNE | RADIO_2056_TX1,
20553 write_radio_reg(pi, RADIO_2056_TX_PGAA_BOOST_TUNE | RADIO_2056_TX1,
20555 write_radio_reg(pi, RADIO_2056_TX_PGAG_BOOST_TUNE | RADIO_2056_TX1,
20557 write_radio_reg(pi, RADIO_2056_TX_MIXA_BOOST_TUNE | RADIO_2056_TX1,
20559 write_radio_reg(pi, RADIO_2056_TX_MIXG_BOOST_TUNE | RADIO_2056_TX1,
20562 if (NREV_IS(pi->pubpi.phy_rev, 3))
20564 else if (NREV_IS(pi->pubpi.phy_rev, 4))
20567 switch (pi->pubpi.radiorev) {
20586 if (CHSPEC_IS2G(pi->radio_chanspec))
20587 write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 |
20591 write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 |
20595 if (pi->sh->boardflags2 & BFL2_GPLL_WAR) {
20596 if (CHSPEC_IS2G(pi->radio_chanspec)) {
20597 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER1 |
20599 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER2 |
20602 if ((pi->sh->chip == BCMA_CHIP_ID_BCM4716) ||
20603 (pi->sh->chip == BCMA_CHIP_ID_BCM47162)) {
20604 write_radio_reg(pi,
20607 write_radio_reg(pi,
20611 write_radio_reg(pi,
20614 write_radio_reg(pi,
20621 if ((pi->sh->boardflags2 & BFL2_GPLL_WAR2) &&
20622 (CHSPEC_IS2G(pi->radio_chanspec))) {
20623 write_radio_reg(pi,
20626 write_radio_reg(pi,
20629 write_radio_reg(pi,
20632 write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 | RADIO_2056_SYN,
20636 if (pi->sh->boardflags2 & BFL2_APLL_WAR) {
20637 if (CHSPEC_IS5G(pi->radio_chanspec)) {
20638 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER1 |
20640 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER2 |
20642 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER4 |
20644 write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 |
20649 if (PHY_IPA(pi) && CHSPEC_IS2G(pi->radio_chanspec)) {
20657 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
20659 if (NREV_GE(pi->pubpi.phy_rev, 5)) {
20661 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20664 if ((pi->sh->chip == BCMA_CHIP_ID_BCM4716) ||
20665 (pi->sh->chip == BCMA_CHIP_ID_BCM47162)) {
20676 if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224 ||
20677 pi->sh->chip == BCMA_CHIP_ID_BCM43225) &&
20678 pi->sh->chippkg == BCMA_PKG_ID_BCM43224_FAB_SMIC) {
20689 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20691 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20693 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20696 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20699 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20702 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20705 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20710 bias = (pi->bw == WL_CHANSPEC_BW_40) ?
20713 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20715 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20717 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20720 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, PA_SPARE1,
20725 if (PHY_IPA(pi) && NREV_IS(pi->pubpi.phy_rev, 6)
20726 && CHSPEC_IS5G(pi->radio_chanspec)) {
20734 freq = CHAN5G_FREQ(CHSPEC_CHANNEL(pi->radio_chanspec));
20766 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
20767 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20769 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20771 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20773 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20776 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20778 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20781 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20786 if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224 ||
20787 pi->sh->chip == BCMA_CHIP_ID_BCM43225) &&
20788 pi->sh->chippkg == BCMA_PKG_ID_BCM43224_FAB_SMIC)
20791 pabias = (pi->phy_pabias == 0) ? 0x30 : pi->phy_pabias;
20793 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20795 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20797 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20804 wlc_phy_radio205x_vcocal_nphy(pi);
20807 void wlc_phy_radio205x_vcocal_nphy(struct brcms_phy *pi)
20809 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
20810 mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_EN, 0x01, 0x0);
20811 mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_CAL_RESETN, 0x04, 0x0);
20812 mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_CAL_RESETN, 0x04,
20814 mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_EN, 0x01, 0x01);
20815 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
20816 write_radio_reg(pi, RADIO_2056_SYN_PLL_VCOCAL12, 0x0);
20817 write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST3, 0x38);
20818 write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST3, 0x18);
20819 write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST3, 0x38);
20820 write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST3, 0x39);
20828 struct brcms_phy *pi,
20837 if (pi->pubpi.radiorev == 5) {
20839 write_radio_reg(pi,
20842 write_radio_reg(pi, RADIO_2057_VCOCAL_COUNTVAL1,
20844 write_radio_reg(pi, RADIO_2057_RFPLL_REFMASTER_SPAREXTALSIZE,
20846 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
20848 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
20850 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
20852 write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC,
20854 write_radio_reg(pi, RADIO_2057_RFPLL_MMD0, ci2->RF_rfpll_mmd0);
20855 write_radio_reg(pi, RADIO_2057_RFPLL_MMD1, ci2->RF_rfpll_mmd1);
20856 write_radio_reg(pi,
20858 write_radio_reg(pi,
20861 write_radio_reg(pi, RADIO_2057_LOGEN_INDBUF2G_TUNE,
20864 write_radio_reg(pi,
20867 write_radio_reg(pi,
20870 write_radio_reg(pi, RADIO_2057_LNA2G_TUNE_CORE0,
20873 write_radio_reg(pi,
20876 write_radio_reg(pi,
20879 write_radio_reg(pi, RADIO_2057_LNA2G_TUNE_CORE1,
20884 write_radio_reg(pi,
20887 write_radio_reg(pi, RADIO_2057_VCOCAL_COUNTVAL1,
20889 write_radio_reg(pi, RADIO_2057_RFPLL_REFMASTER_SPAREXTALSIZE,
20891 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
20893 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
20895 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
20897 write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, ci->RF_cp_kpd_idac);
20898 write_radio_reg(pi, RADIO_2057_RFPLL_MMD0, ci->RF_rfpll_mmd0);
20899 write_radio_reg(pi, RADIO_2057_RFPLL_MMD1, ci->RF_rfpll_mmd1);
20900 write_radio_reg(pi, RADIO_2057_VCOBUF_TUNE, ci->RF_vcobuf_tune);
20901 write_radio_reg(pi,
20904 write_radio_reg(pi, RADIO_2057_LOGEN_MX5G_TUNE,
20906 write_radio_reg(pi, RADIO_2057_LOGEN_INDBUF2G_TUNE,
20908 write_radio_reg(pi, RADIO_2057_LOGEN_INDBUF5G_TUNE,
20911 write_radio_reg(pi,
20914 write_radio_reg(pi,
20917 write_radio_reg(pi, RADIO_2057_PGA_BOOST_TUNE_CORE0,
20919 write_radio_reg(pi, RADIO_2057_TXMIX5G_BOOST_TUNE_CORE0,
20921 write_radio_reg(pi, RADIO_2057_PAD5G_TUNE_MISC_PUS_CORE0,
20923 write_radio_reg(pi, RADIO_2057_LNA2G_TUNE_CORE0,
20925 write_radio_reg(pi, RADIO_2057_LNA5G_TUNE_CORE0,
20928 write_radio_reg(pi,
20931 write_radio_reg(pi,
20934 write_radio_reg(pi, RADIO_2057_PGA_BOOST_TUNE_CORE1,
20936 write_radio_reg(pi, RADIO_2057_TXMIX5G_BOOST_TUNE_CORE1,
20938 write_radio_reg(pi, RADIO_2057_PAD5G_TUNE_MISC_PUS_CORE1,
20940 write_radio_reg(pi, RADIO_2057_LNA2G_TUNE_CORE1,
20942 write_radio_reg(pi, RADIO_2057_LNA5G_TUNE_CORE1,
20946 if ((pi->pubpi.radiorev <= 4) || (pi->pubpi.radiorev == 6)) {
20948 if (CHSPEC_IS2G(pi->radio_chanspec)) {
20949 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
20951 write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, 0x3f);
20952 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
20954 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
20957 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
20959 write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, 0x3f);
20960 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
20962 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
20965 } else if ((pi->pubpi.radiorev == 5) || (pi->pubpi.radiorev == 7) ||
20966 (pi->pubpi.radiorev == 8)) {
20968 if (CHSPEC_IS2G(pi->radio_chanspec)) {
20969 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
20971 write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, 0x30);
20972 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
20974 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
20977 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
20979 write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, 0x3f);
20980 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
20982 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
20988 if (CHSPEC_IS2G(pi->radio_chanspec)) {
20989 if (PHY_IPA(pi)) {
20990 if (pi->pubpi.radiorev == 3)
20993 if (pi->pubpi.radiorev == 5)
20997 if (pi->pubpi.radiorev != 5) {
21007 WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
21012 WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
21020 wlc_phy_radio205x_vcocal_nphy(pi);
21024 wlc_phy_chanspec_nphy_setup(struct brcms_phy *pi, u16 chanspec,
21029 val = read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand;
21032 val = bcma_read16(pi->d11core, D11REGOFFS(psm_phy_hdr_param));
21033 bcma_write16(pi->d11core, D11REGOFFS(psm_phy_hdr_param),
21036 or_phy_reg(pi, (NPHY_TO_BPHY_OFF + BPHY_BB_CONFIG),
21039 bcma_write16(pi->d11core, D11REGOFFS(psm_phy_hdr_param), val);
21041 or_phy_reg(pi, 0x09, NPHY_BandControl_currentBand);
21044 and_phy_reg(pi, 0x09, ~NPHY_BandControl_currentBand);
21046 val = bcma_read16(pi->d11core, D11REGOFFS(psm_phy_hdr_param));
21047 bcma_write16(pi->d11core, D11REGOFFS(psm_phy_hdr_param),
21050 and_phy_reg(pi, (NPHY_TO_BPHY_OFF + BPHY_BB_CONFIG),
21053 bcma_write16(pi->d11core, D11REGOFFS(psm_phy_hdr_param), val);
21056 write_phy_reg(pi, 0x1ce, ci->PHY_BW1a);
21057 write_phy_reg(pi, 0x1cf, ci->PHY_BW2);
21058 write_phy_reg(pi, 0x1d0, ci->PHY_BW3);
21060 write_phy_reg(pi, 0x1d1, ci->PHY_BW4);
21061 write_phy_reg(pi, 0x1d2, ci->PHY_BW5);
21062 write_phy_reg(pi, 0x1d3, ci->PHY_BW6);
21064 if (CHSPEC_CHANNEL(pi->radio_chanspec) == 14) {
21065 wlc_phy_classifier_nphy(pi, NPHY_ClassifierCtrl_ofdm_en, 0);
21067 or_phy_reg(pi, NPHY_TO_BPHY_OFF + BPHY_TEST, 0x800);
21069 wlc_phy_classifier_nphy(pi, NPHY_ClassifierCtrl_ofdm_en,
21073 and_phy_reg(pi, NPHY_TO_BPHY_OFF + BPHY_TEST, ~0x840);
21076 if (pi->nphy_txpwrctrl == PHY_TPC_HW_OFF)
21077 wlc_phy_txpwr_fixpower_nphy(pi);
21079 if (NREV_LT(pi->pubpi.phy_rev, 3))
21080 wlc_phy_adjust_lnagaintbl_nphy(pi);
21082 wlc_phy_txlpfbw_nphy(pi);
21084 if (NREV_GE(pi->pubpi.phy_rev, 3)
21085 && (pi->phy_spuravoid != SPURAVOID_DISABLE)) {
21089 if (!CHSPEC_IS40(pi->radio_chanspec)) {
21090 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
21097 } else if (NREV_GE(pi->pubpi.phy_rev, 7)) {
21100 } else if (pi->nphy_aband_spurwar_en &&
21102 if ((pi->sh->chip == BCMA_CHIP_ID_BCM4716)
21103 && (pi->sh->chippkg == BCMA_PKG_ID_BCM4717)) {
21110 if (pi->phy_spuravoid == SPURAVOID_FORCEON)
21113 if ((pi->sh->chip == BCMA_CHIP_ID_BCM4716) ||
21114 (pi->sh->chip == BCMA_CHIP_ID_BCM43225)) {
21115 bcma_pmu_spuravoid_pllupdate(&pi->d11core->bus->drv_cc,
21118 wlapi_bmac_core_phypll_ctl(pi->sh->physhim, false);
21119 bcma_pmu_spuravoid_pllupdate(&pi->d11core->bus->drv_cc,
21121 wlapi_bmac_core_phypll_ctl(pi->sh->physhim, true);
21124 if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224) ||
21125 (pi->sh->chip == BCMA_CHIP_ID_BCM43225)) {
21127 bcma_write16(pi->d11core,
21130 bcma_write16(pi->d11core,
21133 bcma_write16(pi->d11core,
21136 bcma_write16(pi->d11core,
21141 if (!((pi->sh->chip == BCMA_CHIP_ID_BCM4716) ||
21142 (pi->sh->chip == BCMA_CHIP_ID_BCM47162)))
21143 wlapi_bmac_core_phypll_reset(pi->sh->physhim);
21145 mod_phy_reg(pi, 0x01, (0x1 << 15),
21148 wlc_phy_resetcca_nphy(pi);
21150 pi->phy_isspuravoid = (spuravoid > 0);
21153 if (NREV_LT(pi->pubpi.phy_rev, 7))
21154 write_phy_reg(pi, 0x17e, 0x3830);
21156 wlc_phy_spurwar_nphy(pi);
21159 void wlc_phy_chanspec_set_nphy(struct brcms_phy *pi, u16 chanspec)
21168 (pi, CHSPEC_CHANNEL(chanspec), &freq, &t0, &t1, &t2, &t3))
21171 wlc_phy_chanspec_radio_set((struct brcms_phy_pub *) pi, chanspec);
21173 if (CHSPEC_BW(chanspec) != pi->bw)
21174 wlapi_bmac_bw_set(pi->sh->physhim, CHSPEC_BW(chanspec));
21178 or_phy_reg(pi, 0xa0, BPHY_BAND_SEL_UP20);
21179 if (NREV_GE(pi->pubpi.phy_rev, 7))
21180 or_phy_reg(pi, 0x310, PRIM_SEL_UP20);
21182 and_phy_reg(pi, 0xa0, ~BPHY_BAND_SEL_UP20);
21183 if (NREV_GE(pi->pubpi.phy_rev, 7))
21184 and_phy_reg(pi, 0x310,
21189 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
21190 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
21192 if ((pi->pubpi.radiorev <= 4)
21193 || (pi->pubpi.radiorev == 6)) {
21194 mod_radio_reg(pi, RADIO_2057_TIA_CONFIG_CORE0,
21198 mod_radio_reg(pi, RADIO_2057_TIA_CONFIG_CORE1,
21204 wlc_phy_chanspec_radio2057_setup(pi, t0, t2);
21205 wlc_phy_chanspec_nphy_setup(pi, chanspec,
21206 (pi->pubpi.radiorev == 5) ?
21212 mod_radio_reg(pi,
21216 wlc_phy_chanspec_radio2056_setup(pi, t1);
21218 wlc_phy_chanspec_nphy_setup(pi, chanspec,
21224 mod_radio_reg(pi, RADIO_2055_MASTER_CNTRL1, 0x70,
21228 wlc_phy_chanspec_radio2055_setup(pi, t3);
21229 wlc_phy_chanspec_nphy_setup(pi, chanspec,
21238 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
21242 if (NREV_GE(pi->pubpi.phy_rev, 7))
21245 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
21251 if (pi->srom_fem2g.antswctrllut == 0) {
21252 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
21254 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
21256 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
21258 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
21262 if (pi->srom_fem5g.antswctrllut == 0) {
21263 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
21265 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
21267 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
21269 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
21274 write_phy_reg(pi, 0xc8, 0x0);
21275 write_phy_reg(pi, 0xc9, 0x0);
21277 bcma_chipco_gpio_control(&pi->d11core->bus->drv_cc, mask, mask);
21279 mc = bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
21281 bcma_write32(pi->d11core, D11REGOFFS(maccontrol), mc);
21283 bcma_set16(pi->d11core, D11REGOFFS(psm_gpio_oe), mask);
21285 bcma_mask16(pi->d11core, D11REGOFFS(psm_gpio_out),
21289 write_phy_reg(pi, 0xf8, 0x02d8);
21290 write_phy_reg(pi, 0xf9, 0x0301);
21291 write_phy_reg(pi, 0xfa, 0x02d8);
21292 write_phy_reg(pi, 0xfb, 0x0301);
21297 u16 wlc_phy_classifier_nphy(struct brcms_phy *pi, u16 mask, u16 val)
21302 if (D11REV_IS(pi->sh->corerev, 16)) {
21303 suspended = (bcma_read32(pi->d11core, D11REGOFFS(maccontrol)) &
21306 wlapi_suspend_mac_and_wait(pi->sh->physhim);
21309 curr_ctl = read_phy_reg(pi, 0xb0) & (0x7 << 0);
21313 mod_phy_reg(pi, 0xb0, (0x7 << 0), new_ctl);
21315 if (D11REV_IS(pi->sh->corerev, 16) && !suspended)
21316 wlapi_enable_mac(pi->sh->physhim);
21321 void wlc_phy_force_rfseq_nphy(struct brcms_phy *pi, u8 cmd)
21355 orig_RfseqCoreActv = read_phy_reg(pi, 0xa1);
21356 or_phy_reg(pi, 0xa1,
21359 or_phy_reg(pi, 0xa3, trigger_mask);
21360 SPINWAIT((read_phy_reg(pi, 0xa4) & status_mask), 200000);
21361 write_phy_reg(pi, 0xa1, orig_RfseqCoreActv);
21362 WARN(read_phy_reg(pi, 0xa4) & status_mask, "HW error in rf");
21366 wlc_phy_rfctrl_override_1tomany_nphy(struct brcms_phy *pi, u16 cmd, u16 value,
21372 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
21377 pi, (0x1 << 5),
21381 pi, (0x1 << 4), value,
21385 pi, (0x1 << 3), value,
21391 pi, (0x1 << 2),
21395 pi, (0x1 << 1), value,
21399 pi, (0x1 << 0), value,
21403 pi, (0x1 << 1), value,
21407 pi, (0x1 << 11), 0,
21413 pi, (0x1 << 2),
21417 pi, (0x1 << 1), value,
21421 pi, (0x1 << 0), value,
21425 pi, (0x1 << 2), value,
21429 pi, (0x1 << 11), 1,
21439 pi, (0x1 << 11),
21444 pi, (0x3 << 13),
21455 pi, (0x1 << 12),
21459 pi, (0x1 << 13),
21469 wlc_phy_scale_offset_rssi_nphy(struct brcms_phy *pi, u16 scale, s8 offset,
21484 write_phy_reg(pi, 0x1a6, valuetostuff);
21489 write_phy_reg(pi, 0x1ac, valuetostuff);
21494 write_phy_reg(pi, 0x1b2, valuetostuff);
21499 write_phy_reg(pi, 0x1b8, valuetostuff);
21504 write_phy_reg(pi, 0x1a4, valuetostuff);
21509 write_phy_reg(pi, 0x1aa, valuetostuff);
21514 write_phy_reg(pi, 0x1b0, valuetostuff);
21519 write_phy_reg(pi, 0x1b6, valuetostuff);
21524 write_phy_reg(pi, 0x1a5, valuetostuff);
21528 write_phy_reg(pi, 0x1ab, valuetostuff);
21533 write_phy_reg(pi, 0x1b1, valuetostuff);
21538 write_phy_reg(pi, 0x1b7, valuetostuff);
21543 write_phy_reg(pi, 0x1a7, valuetostuff);
21547 write_phy_reg(pi, 0x1ad, valuetostuff);
21551 write_phy_reg(pi, 0x1b3, valuetostuff);
21555 write_phy_reg(pi, 0x1b9, valuetostuff);
21560 write_phy_reg(pi, 0x1a8, valuetostuff);
21565 write_phy_reg(pi, 0x1ae, valuetostuff);
21570 write_phy_reg(pi, 0x1b4, valuetostuff);
21575 write_phy_reg(pi, 0x1ba, valuetostuff);
21580 write_phy_reg(pi, 0x1a9, valuetostuff);
21584 write_phy_reg(pi, 0x1b5, valuetostuff);
21589 write_phy_reg(pi, 0x1af, valuetostuff);
21594 write_phy_reg(pi, 0x1bb, valuetostuff);
21597 static void brcms_phy_wr_tx_mux(struct brcms_phy *pi, u8 core)
21599 if (PHY_IPA(pi)) {
21600 if (NREV_GE(pi->pubpi.phy_rev, 7))
21601 write_radio_reg(pi,
21605 (CHSPEC_IS5G(pi->radio_chanspec) ?
21608 write_radio_reg(pi,
21612 (CHSPEC_IS5G(pi->radio_chanspec) ?
21615 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
21616 write_radio_reg(pi,
21622 if (pi->pubpi.radioid == BCM2057_ID)
21623 write_radio_reg(pi,
21627 write_radio_reg(pi,
21636 void wlc_phy_rssisel_nphy(struct brcms_phy *pi, u8 core_code, u8 rssi_type)
21647 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
21649 mod_phy_reg(pi, 0x8f, (0x1 << 9), 0);
21650 mod_phy_reg(pi, 0xa5, (0x1 << 9), 0);
21652 mod_phy_reg(pi, 0xa6, (0x3 << 8), 0);
21653 mod_phy_reg(pi, 0xa7, (0x3 << 8), 0);
21655 mod_phy_reg(pi, 0xe5, (0x1 << 5), 0);
21656 mod_phy_reg(pi, 0xe6, (0x1 << 5), 0);
21660 mod_phy_reg(pi, 0xf9, mask, 0);
21661 mod_phy_reg(pi, 0xfb, mask, 0);
21664 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
21672 mod_phy_reg(pi, (core == PHY_CORE_0) ?
21678 mod_phy_reg(pi,
21686 mod_phy_reg(pi,
21693 pi->radio_chanspec)) {
21708 mod_phy_reg(pi,
21715 mod_phy_reg(pi, (core == PHY_CORE_0) ?
21721 mod_phy_reg(pi,
21727 mod_phy_reg(pi,
21735 mod_phy_reg(pi,
21741 mod_phy_reg(pi,
21748 mod_phy_reg(pi,
21754 mod_phy_reg(pi,
21758 brcms_phy_wr_tx_mux(pi, core);
21760 mod_phy_reg(pi,
21784 mod_phy_reg(pi, 0xa6, mask, val);
21785 mod_phy_reg(pi, 0xa7, mask, val);
21799 mod_phy_reg(pi, 0x7a, mask, val);
21800 mod_phy_reg(pi, 0x7d, mask, val);
21826 mod_phy_reg(pi, 0xa5, afectrlovr_rssi_mask,
21845 mod_phy_reg(pi, 0x78, rfctrlcmd_mask, rfctrlcmd_val);
21846 mod_phy_reg(pi, 0xec, rfctrlovr_mask, rfctrlovr_val);
21848 mod_phy_reg(pi, 0x78, (0x1 << 0), (startseq << 0));
21851 mod_phy_reg(pi, 0xec, (0x1 << 0), 0);
21857 wlc_phy_poll_rssi_nphy(struct brcms_phy *pi, u8 rssi_type, s32 *rssi_buf,
21878 afectrlCore1_save = read_phy_reg(pi, 0xa6);
21879 afectrlCore2_save = read_phy_reg(pi, 0xa7);
21880 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
21881 rfctrlMiscReg1_save = read_phy_reg(pi, 0xf9);
21882 rfctrlMiscReg2_save = read_phy_reg(pi, 0xfb);
21883 afectrlOverride1_save = read_phy_reg(pi, 0x8f);
21884 afectrlOverride2_save = read_phy_reg(pi, 0xa5);
21885 rfctrlOverrideAux0_save = read_phy_reg(pi, 0xe5);
21886 rfctrlOverrideAux1_save = read_phy_reg(pi, 0xe6);
21888 afectrlOverride1_save = read_phy_reg(pi, 0xa5);
21889 rfctrlcmd_save = read_phy_reg(pi, 0x78);
21890 rfctrloverride_save = read_phy_reg(pi, 0xec);
21891 rfctrlrssiothers1_save = read_phy_reg(pi, 0x7a);
21892 rfctrlrssiothers2_save = read_phy_reg(pi, 0x7d);
21895 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_ALLRX, rssi_type);
21897 gpiosel_orig = read_phy_reg(pi, 0xca);
21898 if (NREV_LT(pi->pubpi.phy_rev, 2))
21899 write_phy_reg(pi, 0xca, 5);
21905 if (NREV_LT(pi->pubpi.phy_rev, 2)) {
21906 rssi0 = read_phy_reg(pi, 0x1c9);
21907 rssi1 = read_phy_reg(pi, 0x1ca);
21909 rssi0 = read_phy_reg(pi, 0x219);
21910 rssi1 = read_phy_reg(pi, 0x21a);
21929 if (NREV_LT(pi->pubpi.phy_rev, 2))
21930 write_phy_reg(pi, 0xca, gpiosel_orig);
21932 write_phy_reg(pi, 0xa6, afectrlCore1_save);
21933 write_phy_reg(pi, 0xa7, afectrlCore2_save);
21934 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
21935 write_phy_reg(pi, 0xf9, rfctrlMiscReg1_save);
21936 write_phy_reg(pi, 0xfb, rfctrlMiscReg2_save);
21937 write_phy_reg(pi, 0x8f, afectrlOverride1_save);
21938 write_phy_reg(pi, 0xa5, afectrlOverride2_save);
21939 write_phy_reg(pi, 0xe5, rfctrlOverrideAux0_save);
21940 write_phy_reg(pi, 0xe6, rfctrlOverrideAux1_save);
21942 write_phy_reg(pi, 0xa5, afectrlOverride1_save);
21943 write_phy_reg(pi, 0x78, rfctrlcmd_save);
21944 write_phy_reg(pi, 0xec, rfctrloverride_save);
21945 write_phy_reg(pi, 0x7a, rfctrlrssiothers1_save);
21946 write_phy_reg(pi, 0x7d, rfctrlrssiothers2_save);
21952 s16 wlc_phy_tempsense_nphy(struct brcms_phy *pi)
21969 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
21980 read_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG);
21982 afectrlCore1_save = read_phy_reg(pi, 0xa6);
21983 afectrlCore2_save = read_phy_reg(pi, 0xa7);
21984 afectrlOverride_save = read_phy_reg(pi, 0x8f);
21985 afectrlOverride2_save = read_phy_reg(pi, 0xa5);
21986 RSSIMultCoef0QPowerDet_save = read_phy_reg(pi, 0x1ae);
21987 RfctrlOverride5_save = read_phy_reg(pi, 0x346);
21988 RfctrlOverride6_save = read_phy_reg(pi, 0x347);
21989 RfctrlMiscReg5_save = read_phy_reg(pi, 0x344);
21990 read_phy_reg(pi, 0x345); /* RfctrlMiscReg6_save */
21992 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0A, 16,
21994 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0E, 16,
21996 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x02, 16,
21998 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x03, 16,
22001 write_phy_reg(pi, 0x1ae, 0x0);
22005 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x02, 16,
22007 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x03, 16,
22012 write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG,
22015 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1),
22018 mod_phy_reg(pi, 0xa6, (0x1 << 7), 0);
22019 mod_phy_reg(pi, 0xa7, (0x1 << 7), 0);
22020 mod_phy_reg(pi, 0x8f, (0x1 << 7), (0x1 << 7));
22021 mod_phy_reg(pi, 0xa5, (0x1 << 7), (0x1 << 7));
22023 mod_phy_reg(pi, 0xa6, (0x1 << 2), (0x1 << 2));
22024 mod_phy_reg(pi, 0xa7, (0x1 << 2), (0x1 << 2));
22025 mod_phy_reg(pi, 0x8f, (0x1 << 2), (0x1 << 2));
22026 mod_phy_reg(pi, 0xa5, (0x1 << 2), (0x1 << 2));
22028 mod_phy_reg(pi, 0xa6, (0x1 << 2), 0);
22029 mod_phy_reg(pi, 0xa7, (0x1 << 2), 0);
22030 mod_phy_reg(pi, 0xa6, (0x1 << 3), 0);
22031 mod_phy_reg(pi, 0xa7, (0x1 << 3), 0);
22032 mod_phy_reg(pi, 0x8f, (0x1 << 3), (0x1 << 3));
22033 mod_phy_reg(pi, 0xa5, (0x1 << 3), (0x1 << 3));
22034 mod_phy_reg(pi, 0xa6, (0x1 << 6), 0);
22035 mod_phy_reg(pi, 0xa7, (0x1 << 6), 0);
22036 mod_phy_reg(pi, 0x8f, (0x1 << 6), (0x1 << 6));
22037 mod_phy_reg(pi, 0xa5, (0x1 << 6), (0x1 << 6));
22041 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0A, 16,
22043 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0E, 16,
22048 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
22049 write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG,
22053 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp2, 1);
22070 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0A, 16,
22072 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0E, 16,
22077 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp2, 1);
22078 write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG,
22082 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
22084 write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG,
22087 write_phy_reg(pi, 0xa6, afectrlCore1_save);
22088 write_phy_reg(pi, 0xa7, afectrlCore2_save);
22089 write_phy_reg(pi, 0x8f, afectrlOverride_save);
22090 write_phy_reg(pi, 0xa5, afectrlOverride2_save);
22091 write_phy_reg(pi, 0x1ae, RSSIMultCoef0QPowerDet_save);
22092 write_phy_reg(pi, 0x346, RfctrlOverride5_save);
22093 write_phy_reg(pi, 0x347, RfctrlOverride6_save);
22094 write_phy_reg(pi, 0x344, RfctrlMiscReg5_save);
22095 write_phy_reg(pi, 0x345, RfctrlMiscReg5_save);
22097 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0A, 16,
22099 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0E, 16,
22101 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x02, 16,
22103 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x03, 16,
22106 if (pi->sh->chip == BCMA_CHIP_ID_BCM5357) {
22116 offset = (s16) pi->phy_tempsense_offset;
22118 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
22120 read_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE);
22122 afectrlCore1_save = read_phy_reg(pi, 0xa6);
22123 afectrlCore2_save = read_phy_reg(pi, 0xa7);
22124 afectrlOverride_save = read_phy_reg(pi, 0x8f);
22125 afectrlOverride2_save = read_phy_reg(pi, 0xa5);
22126 gpioSel_save = read_phy_reg(pi, 0xca);
22128 write_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE, 0x01);
22130 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
22131 if (NREV_LT(pi->pubpi.phy_rev, 7))
22132 write_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE, 0x05);
22134 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp2, 1);
22135 if (NREV_GE(pi->pubpi.phy_rev, 7))
22136 write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG, 0x01);
22138 write_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE, 0x01);
22143 write_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE,
22146 write_phy_reg(pi, 0xca, gpioSel_save);
22147 write_phy_reg(pi, 0xa6, afectrlCore1_save);
22148 write_phy_reg(pi, 0xa7, afectrlCore2_save);
22149 write_phy_reg(pi, 0x8f, afectrlOverride_save);
22150 write_phy_reg(pi, 0xa5, afectrlOverride2_save);
22152 offset = (s16) pi->phy_tempsense_offset;
22156 read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1);
22158 read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2);
22160 read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1);
22162 read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2);
22164 read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1);
22166 read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2);
22167 pd_pll_ts_save = read_radio_reg(pi, RADIO_2055_PD_PLL_TS);
22169 afectrlCore1_save = read_phy_reg(pi, 0xa6);
22170 afectrlCore2_save = read_phy_reg(pi, 0xa7);
22171 afectrlOverride_save = read_phy_reg(pi, 0xa5);
22172 gpioSel_save = read_phy_reg(pi, 0xca);
22174 write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1, 0x01);
22175 write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1, 0x01);
22176 write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2, 0x08);
22177 write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2, 0x08);
22178 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1, 0x04);
22179 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2, 0x04);
22180 write_radio_reg(pi, RADIO_2055_PD_PLL_TS, 0x00);
22182 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
22183 xor_radio_reg(pi, RADIO_2055_CAL_TS, 0x80);
22185 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
22186 xor_radio_reg(pi, RADIO_2055_CAL_TS, 0x80);
22188 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp2, 1);
22189 xor_radio_reg(pi, RADIO_2055_CAL_TS, 0x80);
22206 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1,
22208 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2,
22210 write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1,
22212 write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1,
22214 write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2,
22216 write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2,
22218 write_radio_reg(pi, RADIO_2055_PD_PLL_TS, pd_pll_ts_save);
22220 write_phy_reg(pi, 0xca, gpioSel_save);
22221 write_phy_reg(pi, 0xa6, afectrlCore1_save);
22222 write_phy_reg(pi, 0xa7, afectrlCore2_save);
22223 write_phy_reg(pi, 0xa5, afectrlOverride_save);
22230 wlc_phy_set_rssi_2055_vcm(struct brcms_phy *pi, u8 rssi_type, u8 *vcm_buf)
22234 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
22237 mod_radio_reg(pi,
22243 mod_radio_reg(pi,
22250 mod_radio_reg(pi,
22256 mod_radio_reg(pi,
22265 mod_radio_reg(pi,
22272 mod_radio_reg(pi,
22282 static void wlc_phy_rssi_cal_nphy_rev3(struct brcms_phy *pi)
22333 classif_state = wlc_phy_classifier_nphy(pi, 0, 0);
22334 wlc_phy_classifier_nphy(pi, (0x7 << 0), 4);
22335 wlc_phy_clip_det_nphy(pi, 0, clip_state);
22336 wlc_phy_clip_det_nphy(pi, 1, clip_off);
22338 NPHY_Rfctrlintc1_save = read_phy_reg(pi, 0x91);
22339 NPHY_Rfctrlintc2_save = read_phy_reg(pi, 0x92);
22340 NPHY_AfectrlOverride1_save = read_phy_reg(pi, 0x8f);
22341 NPHY_AfectrlOverride2_save = read_phy_reg(pi, 0xa5);
22342 NPHY_AfectrlCore1_save = read_phy_reg(pi, 0xa6);
22343 NPHY_AfectrlCore2_save = read_phy_reg(pi, 0xa7);
22344 NPHY_RfctrlOverride0_save = read_phy_reg(pi, 0xe7);
22345 NPHY_RfctrlOverride1_save = read_phy_reg(pi, 0xec);
22346 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
22347 NPHY_REV7_RfctrlOverride3_save = read_phy_reg(pi, 0x342);
22348 NPHY_REV7_RfctrlOverride4_save = read_phy_reg(pi, 0x343);
22349 NPHY_REV7_RfctrlOverride5_save = read_phy_reg(pi, 0x346);
22350 NPHY_REV7_RfctrlOverride6_save = read_phy_reg(pi, 0x347);
22352 NPHY_RfctrlOverrideAux0_save = read_phy_reg(pi, 0xe5);
22353 NPHY_RfctrlOverrideAux1_save = read_phy_reg(pi, 0xe6);
22354 NPHY_RfctrlCmd_save = read_phy_reg(pi, 0x78);
22355 NPHY_RfctrlMiscReg1_save = read_phy_reg(pi, 0xf9);
22356 NPHY_RfctrlMiscReg2_save = read_phy_reg(pi, 0xfb);
22357 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
22358 NPHY_REV7_RfctrlMiscReg3_save = read_phy_reg(pi, 0x340);
22359 NPHY_REV7_RfctrlMiscReg4_save = read_phy_reg(pi, 0x341);
22360 NPHY_REV7_RfctrlMiscReg5_save = read_phy_reg(pi, 0x344);
22361 NPHY_REV7_RfctrlMiscReg6_save = read_phy_reg(pi, 0x345);
22363 NPHY_RfctrlRSSIOTHERS1_save = read_phy_reg(pi, 0x7a);
22364 NPHY_RfctrlRSSIOTHERS2_save = read_phy_reg(pi, 0x7d);
22366 wlc_phy_rfctrlintc_override_nphy(pi, NPHY_RfctrlIntc_override_OFF, 0,
22368 wlc_phy_rfctrlintc_override_nphy(pi, NPHY_RfctrlIntc_override_TRSW, 1,
22371 if (NREV_GE(pi->pubpi.phy_rev, 7))
22373 pi,
22377 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 0), 0, 0, 0);
22379 if (NREV_GE(pi->pubpi.phy_rev, 7))
22381 pi,
22385 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 1), 1, 0, 0);
22387 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
22388 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 7),
22391 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 6), 1, 0, 0,
22394 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 7), 1, 0, 0);
22395 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 6), 1, 0, 0);
22398 if (CHSPEC_IS5G(pi->radio_chanspec)) {
22399 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
22401 pi, (0x1 << 5),
22405 pi, (0x1 << 4), 1, 0,
22409 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 5), 0, 0, 0);
22410 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 4), 1, 0, 0);
22414 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
22416 pi, (0x1 << 4),
22420 pi, (0x1 << 5), 1, 0,
22424 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 4), 0, 0, 0);
22425 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 5), 1, 0, 0);
22430 (struct brcms_phy_pub *) pi);
22434 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
22439 wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0,
22445 wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0,
22453 if (NREV_GE(pi->pubpi.phy_rev, 7))
22454 mod_radio_reg(pi, (core == PHY_CORE_0) ?
22459 mod_radio_reg(pi, RADIO_2056_RX_RSSI_MISC |
22466 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_NB,
22503 if (NREV_GE(pi->pubpi.phy_rev, 7))
22504 mod_radio_reg(pi, (core == PHY_CORE_0) ?
22509 mod_radio_reg(pi, RADIO_2056_RX_RSSI_MISC |
22546 pi, 0x0,
22561 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
22575 wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0,
22582 wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0,
22590 wlc_phy_poll_rssi_nphy(pi, rssi_type, poll_result_core,
22622 pi, 0x0,
22640 write_phy_reg(pi, 0x91, NPHY_Rfctrlintc1_save);
22641 write_phy_reg(pi, 0x92, NPHY_Rfctrlintc2_save);
22643 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
22645 mod_phy_reg(pi, 0xe7, (0x1 << 0), 1 << 0);
22646 mod_phy_reg(pi, 0x78, (0x1 << 0), 1 << 0);
22647 mod_phy_reg(pi, 0xe7, (0x1 << 0), 0);
22649 mod_phy_reg(pi, 0xec, (0x1 << 0), 1 << 0);
22650 mod_phy_reg(pi, 0x78, (0x1 << 1), 1 << 1);
22651 mod_phy_reg(pi, 0xec, (0x1 << 0), 0);
22653 write_phy_reg(pi, 0x8f, NPHY_AfectrlOverride1_save);
22654 write_phy_reg(pi, 0xa5, NPHY_AfectrlOverride2_save);
22655 write_phy_reg(pi, 0xa6, NPHY_AfectrlCore1_save);
22656 write_phy_reg(pi, 0xa7, NPHY_AfectrlCore2_save);
22657 write_phy_reg(pi, 0xe7, NPHY_RfctrlOverride0_save);
22658 write_phy_reg(pi, 0xec, NPHY_RfctrlOverride1_save);
22659 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
22660 write_phy_reg(pi, 0x342, NPHY_REV7_RfctrlOverride3_save);
22661 write_phy_reg(pi, 0x343, NPHY_REV7_RfctrlOverride4_save);
22662 write_phy_reg(pi, 0x346, NPHY_REV7_RfctrlOverride5_save);
22663 write_phy_reg(pi, 0x347, NPHY_REV7_RfctrlOverride6_save);
22665 write_phy_reg(pi, 0xe5, NPHY_RfctrlOverrideAux0_save);
22666 write_phy_reg(pi, 0xe6, NPHY_RfctrlOverrideAux1_save);
22667 write_phy_reg(pi, 0x78, NPHY_RfctrlCmd_save);
22668 write_phy_reg(pi, 0xf9, NPHY_RfctrlMiscReg1_save);
22669 write_phy_reg(pi, 0xfb, NPHY_RfctrlMiscReg2_save);
22670 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
22671 write_phy_reg(pi, 0x340, NPHY_REV7_RfctrlMiscReg3_save);
22672 write_phy_reg(pi, 0x341, NPHY_REV7_RfctrlMiscReg4_save);
22673 write_phy_reg(pi, 0x344, NPHY_REV7_RfctrlMiscReg5_save);
22674 write_phy_reg(pi, 0x345, NPHY_REV7_RfctrlMiscReg6_save);
22676 write_phy_reg(pi, 0x7a, NPHY_RfctrlRSSIOTHERS1_save);
22677 write_phy_reg(pi, 0x7d, NPHY_RfctrlRSSIOTHERS2_save);
22679 if (CHSPEC_IS2G(pi->radio_chanspec)) {
22680 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
22681 pi->rssical_cache.rssical_radio_regs_2G[0] =
22682 read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE0);
22683 pi->rssical_cache.rssical_radio_regs_2G[1] =
22684 read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE1);
22686 pi->rssical_cache.rssical_radio_regs_2G[0] =
22687 read_radio_reg(pi,
22690 pi->rssical_cache.rssical_radio_regs_2G[1] =
22691 read_radio_reg(pi,
22696 pi->rssical_cache.rssical_phyregs_2G[0] =
22697 read_phy_reg(pi, 0x1a6);
22698 pi->rssical_cache.rssical_phyregs_2G[1] =
22699 read_phy_reg(pi, 0x1ac);
22700 pi->rssical_cache.rssical_phyregs_2G[2] =
22701 read_phy_reg(pi, 0x1b2);
22702 pi->rssical_cache.rssical_phyregs_2G[3] =
22703 read_phy_reg(pi, 0x1b8);
22704 pi->rssical_cache.rssical_phyregs_2G[4] =
22705 read_phy_reg(pi, 0x1a4);
22706 pi->rssical_cache.rssical_phyregs_2G[5] =
22707 read_phy_reg(pi, 0x1aa);
22708 pi->rssical_cache.rssical_phyregs_2G[6] =
22709 read_phy_reg(pi, 0x1b0);
22710 pi->rssical_cache.rssical_phyregs_2G[7] =
22711 read_phy_reg(pi, 0x1b6);
22712 pi->rssical_cache.rssical_phyregs_2G[8] =
22713 read_phy_reg(pi, 0x1a5);
22714 pi->rssical_cache.rssical_phyregs_2G[9] =
22715 read_phy_reg(pi, 0x1ab);
22716 pi->rssical_cache.rssical_phyregs_2G[10] =
22717 read_phy_reg(pi, 0x1b1);
22718 pi->rssical_cache.rssical_phyregs_2G[11] =
22719 read_phy_reg(pi, 0x1b7);
22721 pi->nphy_rssical_chanspec_2G = pi->radio_chanspec;
22723 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
22724 pi->rssical_cache.rssical_radio_regs_5G[0] =
22725 read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE0);
22726 pi->rssical_cache.rssical_radio_regs_5G[1] =
22727 read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE1);
22729 pi->rssical_cache.rssical_radio_regs_5G[0] =
22730 read_radio_reg(pi,
22733 pi->rssical_cache.rssical_radio_regs_5G[1] =
22734 read_radio_reg(pi,
22739 pi->rssical_cache.rssical_phyregs_5G[0] =
22740 read_phy_reg(pi, 0x1a6);
22741 pi->rssical_cache.rssical_phyregs_5G[1] =
22742 read_phy_reg(pi, 0x1ac);
22743 pi->rssical_cache.rssical_phyregs_5G[2] =
22744 read_phy_reg(pi, 0x1b2);
22745 pi->rssical_cache.rssical_phyregs_5G[3] =
22746 read_phy_reg(pi, 0x1b8);
22747 pi->rssical_cache.rssical_phyregs_5G[4] =
22748 read_phy_reg(pi, 0x1a4);
22749 pi->rssical_cache.rssical_phyregs_5G[5] =
22750 read_phy_reg(pi, 0x1aa);
22751 pi->rssical_cache.rssical_phyregs_5G[6] =
22752 read_phy_reg(pi, 0x1b0);
22753 pi->rssical_cache.rssical_phyregs_5G[7] =
22754 read_phy_reg(pi, 0x1b6);
22755 pi->rssical_cache.rssical_phyregs_5G[8] =
22756 read_phy_reg(pi, 0x1a5);
22757 pi->rssical_cache.rssical_phyregs_5G[9] =
22758 read_phy_reg(pi, 0x1ab);
22759 pi->rssical_cache.rssical_phyregs_5G[10] =
22760 read_phy_reg(pi, 0x1b1);
22761 pi->rssical_cache.rssical_phyregs_5G[11] =
22762 read_phy_reg(pi, 0x1b7);
22764 pi->nphy_rssical_chanspec_5G = pi->radio_chanspec;
22767 wlc_phy_classifier_nphy(pi, (0x7 << 0), classif_state);
22768 wlc_phy_clip_det_nphy(pi, 1, clip_state);
22771 static void wlc_phy_rssi_cal_nphy_rev2(struct brcms_phy *pi, u8 rssi_type)
22815 classif_state = wlc_phy_classifier_nphy(pi, 0, 0);
22816 wlc_phy_classifier_nphy(pi, (0x7 << 0), 4);
22817 wlc_phy_clip_det_nphy(pi, 0, clip_state);
22818 wlc_phy_clip_det_nphy(pi, 1, clip_off);
22822 CHSPEC_IS5G(pi->radio_chanspec) ? 0x140 : 0x110;
22824 rfctrlintc_state[0] = read_phy_reg(pi, 0x91);
22825 rfpdcorerxtx_state[0] = read_radio_reg(pi, RADIO_2055_PD_CORE1_RXTX);
22826 write_phy_reg(pi, 0x91, rfctrlintc_override_val);
22827 write_radio_reg(pi, RADIO_2055_PD_CORE1_RXTX, rf_pd_val);
22829 rfctrlintc_state[1] = read_phy_reg(pi, 0x92);
22830 rfpdcorerxtx_state[1] = read_radio_reg(pi, RADIO_2055_PD_CORE2_RXTX);
22831 write_phy_reg(pi, 0x92, rfctrlintc_override_val);
22832 write_radio_reg(pi, RADIO_2055_PD_CORE2_RXTX, rf_pd_val);
22837 read_radio_reg(pi, RADIO_2055_PD_CORE1_RSSI_MISC) & pd_mask;
22839 read_radio_reg(pi, RADIO_2055_PD_CORE2_RSSI_MISC) & pd_mask;
22840 mod_radio_reg(pi, RADIO_2055_PD_CORE1_RSSI_MISC, pd_mask, 0);
22841 mod_radio_reg(pi, RADIO_2055_PD_CORE2_RSSI_MISC, pd_mask, 0);
22845 read_radio_reg(pi, RADIO_2055_SP_RSSI_CORE1) & rssi_ctrl_mask;
22847 read_radio_reg(pi, RADIO_2055_SP_RSSI_CORE2) & rssi_ctrl_mask;
22848 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_ALLRX, rssi_type);
22850 wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0, RADIO_MIMO_CORESEL_ALLRX,
22852 wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0, RADIO_MIMO_CORESEL_ALLRX,
22859 wlc_phy_set_rssi_2055_vcm(pi, rssi_type, vcm_tmp);
22861 wlc_phy_poll_rssi_nphy(pi, rssi_type, &poll_results[vcm][0],
22894 wlc_phy_set_rssi_2055_vcm(pi, rssi_type, vcm_final);
22919 wlc_phy_scale_offset_rssi_nphy(pi, 0x0,
22930 mod_radio_reg(pi, RADIO_2055_PD_CORE1_RSSI_MISC, pd_mask, pd_state[0]);
22931 mod_radio_reg(pi, RADIO_2055_PD_CORE2_RSSI_MISC, pd_mask, pd_state[1]);
22933 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE1,
22936 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE1,
22939 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE1,
22942 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE2,
22945 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE2,
22948 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE2,
22950 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_OFF, rssi_type);
22952 write_phy_reg(pi, 0x91, rfctrlintc_state[0]);
22953 write_radio_reg(pi, RADIO_2055_PD_CORE1_RXTX, rfpdcorerxtx_state[0]);
22954 write_phy_reg(pi, 0x92, rfctrlintc_state[1]);
22955 write_radio_reg(pi, RADIO_2055_PD_CORE2_RXTX, rfpdcorerxtx_state[1]);
22957 wlc_phy_classifier_nphy(pi, (0x7 << 0), classif_state);
22958 wlc_phy_clip_det_nphy(pi, 1, clip_state);
22960 wlc_phy_resetcca_nphy(pi);
22963 void wlc_phy_rssi_cal_nphy(struct brcms_phy *pi)
22965 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
22966 wlc_phy_rssi_cal_nphy_rev3(pi);
22968 wlc_phy_rssi_cal_nphy_rev2(pi, NPHY_RSSI_SEL_NB);
22969 wlc_phy_rssi_cal_nphy_rev2(pi, NPHY_RSSI_SEL_W1);
22970 wlc_phy_rssi_cal_nphy_rev2(pi, NPHY_RSSI_SEL_W2);
22975 wlc_phy_rssi_compute_nphy(struct brcms_phy *pi, struct d11rxhdr *rxh)
22998 if (pi->sh->rssi_mode == RSSI_ANT_MERGE_MAX)
23000 else if (pi->sh->rssi_mode == RSSI_ANT_MERGE_MIN)
23002 else if (pi->sh->rssi_mode == RSSI_ANT_MERGE_AVG)
23009 wlc_phy_loadsampletable_nphy(struct brcms_phy *pi, struct cordic_iq *tone_buf,
23019 if (pi->phyhang_avoid)
23020 wlc_phy_stay_in_carriersearch_nphy(pi, true);
23025 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_SAMPLEPLAY, num_samps, 0, 32,
23030 if (pi->phyhang_avoid)
23031 wlc_phy_stay_in_carriersearch_nphy(pi, false);
23035 wlc_phy_gen_load_samples_nphy(struct brcms_phy *pi, u32 f_kHz, u16 max_val,
23044 is_phybw40 = CHSPEC_IS40(pi->radio_chanspec);
23049 spur = read_phy_reg(pi, 0x01);
23076 wlc_phy_loadsampletable_nphy(pi, tone_buf, num_samps);
23084 wlc_phy_runsamples_nphy(struct brcms_phy *pi, u16 num_samps, u16 loops,
23093 if (pi->phyhang_avoid)
23094 wlc_phy_stay_in_carriersearch_nphy(pi, true);
23097 if (CHSPEC_IS40(pi->radio_chanspec))
23100 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
23102 lpf_bw_ctl_override3 = read_phy_reg(pi, 0x342) & (0x1 << 7);
23103 lpf_bw_ctl_override4 = read_phy_reg(pi, 0x343) & (0x1 << 7);
23106 pi,
23109 (pi,
23113 pi->nphy_sample_play_lpf_bw_ctl_ovr = true;
23115 read_phy_reg(pi, 0x340); /* lpf_bw_ctl_miscreg3 */
23116 read_phy_reg(pi, 0x341); /* lpf_bw_ctl_miscreg4 */
23119 if ((pi->nphy_bb_mult_save & BB_MULT_VALID_MASK) == 0) {
23121 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, 87, 16,
23123 pi->nphy_bb_mult_save =
23130 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, 87, 16,
23134 if (pi->phyhang_avoid)
23135 wlc_phy_stay_in_carriersearch_nphy(pi, false);
23137 write_phy_reg(pi, 0xc6, num_samps - 1);
23140 write_phy_reg(pi, 0xc4, loops - 1);
23142 write_phy_reg(pi, 0xc4, loops);
23144 write_phy_reg(pi, 0xc5, wait);
23146 orig_RfseqCoreActv = read_phy_reg(pi, 0xa1);
23147 or_phy_reg(pi, 0xa1, NPHY_RfseqMode_CoreActv_override);
23150 and_phy_reg(pi, 0xc2, 0x7FFF);
23152 or_phy_reg(pi, 0xc2, 0x8000);
23156 write_phy_reg(pi, 0xc3, sample_cmd);
23159 SPINWAIT(((read_phy_reg(pi, 0xa4) & 0x1) == 1), 1000);
23161 write_phy_reg(pi, 0xa1, orig_RfseqCoreActv);
23165 wlc_phy_tx_tone_nphy(struct brcms_phy *pi, u32 f_kHz, u16 max_val,
23172 num_samps = wlc_phy_gen_load_samples_nphy(pi, f_kHz, max_val,
23177 wlc_phy_runsamples_nphy(pi, num_samps, loops, wait, iqmode,
23183 void wlc_phy_stopplayback_nphy(struct brcms_phy *pi)
23188 if (pi->phyhang_avoid)
23189 wlc_phy_stay_in_carriersearch_nphy(pi, true);
23191 playback_status = read_phy_reg(pi, 0xc7);
23193 or_phy_reg(pi, 0xc3, NPHY_sampleCmd_STOP);
23195 and_phy_reg(pi, 0xc2,
23198 and_phy_reg(pi, 0xc3, (u16) ~(0x1 << 2));
23200 if ((pi->nphy_bb_mult_save & BB_MULT_VALID_MASK) != 0) {
23202 bb_mult = pi->nphy_bb_mult_save & BB_MULT_MASK;
23203 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, 87, 16,
23206 pi->nphy_bb_mult_save = 0;
23209 if (NREV_IS(pi->pubpi.phy_rev, 7) || NREV_GE(pi->pubpi.phy_rev, 8)) {
23210 if (pi->nphy_sample_play_lpf_bw_ctl_ovr) {
23212 pi,
23216 pi->nphy_sample_play_lpf_bw_ctl_ovr = false;
23220 if (pi->phyhang_avoid)
23221 wlc_phy_stay_in_carriersearch_nphy(pi, false);
23224 static u32 *brcms_phy_get_tx_pwrctrl_tbl(struct brcms_phy *pi)
23227 uint phyrev = pi->pubpi.phy_rev;
23229 if (PHY_IPA(pi)) {
23231 wlc_phy_get_ipa_gaintbl_nphy(pi);
23233 if (CHSPEC_IS5G(pi->radio_chanspec)) {
23238 (pi->srom_fem5g.extpagain == 3) ?
23245 if (pi->pubpi.radiorev == 3)
23248 else if (pi->pubpi.radiorev == 5)
23253 (pi->srom_fem2g.extpagain == 3))
23265 struct nphy_txgains wlc_phy_get_tx_gain_nphy(struct brcms_phy *pi)
23272 if (pi->nphy_txpwrctrl == PHY_TPC_HW_OFF) {
23273 if (pi->phyhang_avoid)
23274 wlc_phy_stay_in_carriersearch_nphy(pi, true);
23276 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
23279 if (pi->phyhang_avoid)
23280 wlc_phy_stay_in_carriersearch_nphy(pi, false);
23283 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
23294 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
23315 uint phyrev = pi->pubpi.phy_rev;
23317 base_idx[0] = (read_phy_reg(pi, 0x1ed) >> 8) & 0x7f;
23318 base_idx[1] = (read_phy_reg(pi, 0x1ee) >> 8) & 0x7f;
23322 brcms_phy_get_tx_pwrctrl_tbl(pi);
23383 wlc_phy_iqcal_gainparams_nphy(struct brcms_phy *pi, u16 core_no,
23389 u8 band_idx = (CHSPEC_IS5G(pi->radio_chanspec) ? 1 : 0);
23391 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
23392 if (NREV_GE(pi->pubpi.phy_rev, 7))
23399 if (NREV_GE(pi->pubpi.phy_rev, 7))
23438 static void wlc_phy_txcal_radio_setup_nphy(struct brcms_phy *pi)
23442 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
23446 pi->tx_rx_cal_radio_saveregs[(core * 11) + 0] =
23447 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
23450 pi->tx_rx_cal_radio_saveregs[(core * 11) + 1] =
23451 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
23454 pi->tx_rx_cal_radio_saveregs[(core * 11) + 2] =
23455 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
23458 pi->tx_rx_cal_radio_saveregs[(core * 11) + 3] =
23459 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
23462 pi->tx_rx_cal_radio_saveregs[(core * 11) + 4] = 0;
23464 pi->tx_rx_cal_radio_saveregs[(core * 11) + 5] =
23465 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
23468 if (pi->pubpi.radiorev != 5)
23469 pi->tx_rx_cal_radio_saveregs[(core * 11) + 6] =
23470 READ_RADIO_REG3(pi, RADIO_2057, TX,
23474 pi->tx_rx_cal_radio_saveregs[(core * 11) + 7] =
23475 READ_RADIO_REG3(pi, RADIO_2057, TX, core, TSSIG);
23477 pi->tx_rx_cal_radio_saveregs[(core * 11) + 8] =
23478 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
23481 if (CHSPEC_IS5G(pi->radio_chanspec)) {
23482 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23484 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23486 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23488 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23490 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23492 if (pi->use_int_tx_iqlo_cal_nphy) {
23493 WRITE_RADIO_REG3(pi, RADIO_2057, TX,
23495 if (!(pi->
23497 WRITE_RADIO_REG3(pi, RADIO_2057,
23501 WRITE_RADIO_REG3(pi, RADIO_2057,
23505 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23508 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23510 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23512 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23514 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23517 if (pi->pubpi.radiorev != 5)
23518 WRITE_RADIO_REG3(pi, RADIO_2057, TX,
23520 if (pi->use_int_tx_iqlo_cal_nphy) {
23521 WRITE_RADIO_REG3(pi, RADIO_2057, TX,
23524 if (!(pi->
23526 WRITE_RADIO_REG3(pi, RADIO_2057,
23530 WRITE_RADIO_REG3(pi, RADIO_2057,
23534 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23538 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
23545 pi->tx_rx_cal_radio_saveregs[(core * 11) + 0] =
23546 read_radio_reg(pi,
23550 pi->tx_rx_cal_radio_saveregs[(core * 11) + 1] =
23551 read_radio_reg(pi,
23555 pi->tx_rx_cal_radio_saveregs[(core * 11) + 2] =
23556 read_radio_reg(pi,
23560 pi->tx_rx_cal_radio_saveregs[(core * 11) + 3] =
23562 pi,
23566 pi->tx_rx_cal_radio_saveregs[(core * 11) + 4] =
23567 read_radio_reg(pi,
23571 pi->tx_rx_cal_radio_saveregs[(core * 11) + 5] =
23572 read_radio_reg(pi,
23576 pi->tx_rx_cal_radio_saveregs[(core * 11) + 6] =
23577 read_radio_reg(pi,
23580 pi->tx_rx_cal_radio_saveregs[(core * 11) + 7] =
23581 read_radio_reg(pi,
23584 pi->tx_rx_cal_radio_saveregs[(core * 11) + 8] =
23585 read_radio_reg(pi,
23589 pi->tx_rx_cal_radio_saveregs[(core * 11) + 9] =
23590 read_radio_reg(pi,
23594 pi->tx_rx_cal_radio_saveregs[(core * 11) + 10] =
23595 read_radio_reg(pi,
23599 if (CHSPEC_IS5G(pi->radio_chanspec)) {
23600 write_radio_reg(pi,
23603 write_radio_reg(pi,
23606 write_radio_reg(pi,
23609 write_radio_reg(pi,
23612 write_radio_reg(pi,
23616 if (PHY_IPA(pi)) {
23618 pi,
23621 write_radio_reg(pi,
23626 pi,
23629 write_radio_reg(pi,
23633 write_radio_reg(pi,
23636 write_radio_reg(pi,
23640 write_radio_reg(pi,
23643 write_radio_reg(pi,
23647 write_radio_reg(pi,
23650 write_radio_reg(pi,
23653 write_radio_reg(pi,
23656 write_radio_reg(pi,
23659 write_radio_reg(pi,
23662 write_radio_reg(pi,
23666 if (PHY_IPA(pi)) {
23669 pi,
23672 if (NREV_LT(pi->pubpi.phy_rev, 5))
23674 pi,
23680 pi,
23686 pi,
23689 write_radio_reg(pi,
23694 write_radio_reg(pi,
23697 write_radio_reg(pi,
23700 write_radio_reg(pi,
23707 pi->tx_rx_cal_radio_saveregs[0] =
23708 read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1);
23709 write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1, 0x29);
23710 pi->tx_rx_cal_radio_saveregs[1] =
23711 read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2);
23712 write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2, 0x54);
23714 pi->tx_rx_cal_radio_saveregs[2] =
23715 read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1);
23716 write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1, 0x29);
23717 pi->tx_rx_cal_radio_saveregs[3] =
23718 read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2);
23719 write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2, 0x54);
23721 pi->tx_rx_cal_radio_saveregs[4] =
23722 read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1);
23723 pi->tx_rx_cal_radio_saveregs[5] =
23724 read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2);
23726 if ((read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand) ==
23729 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1, 0x04);
23730 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2, 0x04);
23733 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1, 0x20);
23734 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2, 0x20);
23737 if (NREV_LT(pi->pubpi.phy_rev, 2)) {
23739 or_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM, 0x20);
23740 or_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM, 0x20);
23743 and_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM, 0xdf);
23744 and_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM, 0xdf);
23749 static void wlc_phy_txcal_radio_cleanup_nphy(struct brcms_phy *pi)
23753 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
23756 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23758 pi->
23762 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, IQCAL_VCM_HG,
23763 pi->
23767 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, IQCAL_IDAC,
23768 pi->
23772 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSI_VCM,
23773 pi->
23777 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TX_SSI_MUX,
23778 pi->
23782 if (pi->pubpi.radiorev != 5)
23783 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23785 pi->tx_rx_cal_radio_saveregs
23788 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSIG,
23789 pi->
23793 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSI_MISC1,
23794 pi->
23798 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
23803 write_radio_reg(pi,
23805 pi->
23809 write_radio_reg(pi,
23811 pi->
23815 write_radio_reg(pi,
23817 pi->
23821 write_radio_reg(pi, RADIO_2056_TX_TSSI_VCM | jtag_core,
23822 pi->
23826 write_radio_reg(pi,
23828 pi->
23832 write_radio_reg(pi,
23834 pi->
23838 write_radio_reg(pi, RADIO_2056_TX_TSSIA | jtag_core,
23839 pi->
23843 write_radio_reg(pi, RADIO_2056_TX_TSSIG | jtag_core,
23844 pi->
23848 write_radio_reg(pi,
23850 pi->
23854 write_radio_reg(pi,
23856 pi->
23860 write_radio_reg(pi,
23862 pi->
23868 write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1,
23869 pi->tx_rx_cal_radio_saveregs[0]);
23870 write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2,
23871 pi->tx_rx_cal_radio_saveregs[1]);
23872 write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1,
23873 pi->tx_rx_cal_radio_saveregs[2]);
23874 write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2,
23875 pi->tx_rx_cal_radio_saveregs[3]);
23876 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1,
23877 pi->tx_rx_cal_radio_saveregs[4]);
23878 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2,
23879 pi->tx_rx_cal_radio_saveregs[5]);
23883 static void wlc_phy_txcal_physetup_nphy(struct brcms_phy *pi)
23887 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
23888 pi->tx_rx_cal_phy_saveregs[0] = read_phy_reg(pi, 0xa6);
23889 pi->tx_rx_cal_phy_saveregs[1] = read_phy_reg(pi, 0xa7);
23894 mod_phy_reg(pi, 0xa6, mask, val);
23895 mod_phy_reg(pi, 0xa7, mask, val);
23897 val = read_phy_reg(pi, 0x8f);
23898 pi->tx_rx_cal_phy_saveregs[2] = val;
23900 write_phy_reg(pi, 0x8f, val);
23902 val = read_phy_reg(pi, 0xa5);
23903 pi->tx_rx_cal_phy_saveregs[3] = val;
23905 write_phy_reg(pi, 0xa5, val);
23907 pi->tx_rx_cal_phy_saveregs[4] = read_phy_reg(pi, 0x01);
23908 mod_phy_reg(pi, 0x01, (0x1 << 15), 0);
23910 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 3, 16,
23912 pi->tx_rx_cal_phy_saveregs[5] = val;
23914 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 3, 16,
23917 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 19, 16,
23919 pi->tx_rx_cal_phy_saveregs[6] = val;
23921 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 19, 16,
23924 pi->tx_rx_cal_phy_saveregs[7] = read_phy_reg(pi, 0x91);
23925 pi->tx_rx_cal_phy_saveregs[8] = read_phy_reg(pi, 0x92);
23927 if (!(pi->use_int_tx_iqlo_cal_nphy))
23929 pi,
23937 pi,
23944 wlc_phy_rfctrlintc_override_nphy(pi,
23947 wlc_phy_rfctrlintc_override_nphy(pi,
23951 pi->tx_rx_cal_phy_saveregs[9] = read_phy_reg(pi, 0x297);
23952 pi->tx_rx_cal_phy_saveregs[10] = read_phy_reg(pi, 0x29b);
23953 mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x297 :
23956 mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x297 :
23959 if (NREV_IS(pi->pubpi.phy_rev, 7)
23960 || NREV_GE(pi->pubpi.phy_rev, 8))
23962 pi, (0x1 << 7),
23964 (pi,
23968 if (pi->use_int_tx_iqlo_cal_nphy
23969 && !(pi->internal_tx_iqlo_cal_tapoff_intpa_nphy)) {
23971 if (NREV_IS(pi->pubpi.phy_rev, 7)) {
23973 mod_radio_reg(pi, RADIO_2057_OVR_REG0, 1 << 4,
23976 if (CHSPEC_IS2G(pi->radio_chanspec)) {
23978 pi,
23982 pi,
23987 pi,
23991 pi,
23995 } else if (NREV_GE(pi->pubpi.phy_rev, 8)) {
23997 pi,
24004 pi->tx_rx_cal_phy_saveregs[0] = read_phy_reg(pi, 0xa6);
24005 pi->tx_rx_cal_phy_saveregs[1] = read_phy_reg(pi, 0xa7);
24010 mod_phy_reg(pi, 0xa6, mask, val);
24011 mod_phy_reg(pi, 0xa7, mask, val);
24013 val = read_phy_reg(pi, 0xa5);
24014 pi->tx_rx_cal_phy_saveregs[2] = val;
24016 write_phy_reg(pi, 0xa5, val);
24018 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 2, 16,
24020 pi->tx_rx_cal_phy_saveregs[3] = val;
24022 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 2, 16,
24025 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 18, 16,
24027 pi->tx_rx_cal_phy_saveregs[4] = val;
24029 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 18, 16,
24032 pi->tx_rx_cal_phy_saveregs[5] = read_phy_reg(pi, 0x91);
24033 pi->tx_rx_cal_phy_saveregs[6] = read_phy_reg(pi, 0x92);
24034 val = CHSPEC_IS5G(pi->radio_chanspec) ? 0x180 : 0x120;
24035 write_phy_reg(pi, 0x91, val);
24036 write_phy_reg(pi, 0x92, val);
24040 static void wlc_phy_txcal_phycleanup_nphy(struct brcms_phy *pi)
24044 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
24045 write_phy_reg(pi, 0xa6, pi->tx_rx_cal_phy_saveregs[0]);
24046 write_phy_reg(pi, 0xa7, pi->tx_rx_cal_phy_saveregs[1]);
24047 write_phy_reg(pi, 0x8f, pi->tx_rx_cal_phy_saveregs[2]);
24048 write_phy_reg(pi, 0xa5, pi->tx_rx_cal_phy_saveregs[3]);
24049 write_phy_reg(pi, 0x01, pi->tx_rx_cal_phy_saveregs[4]);
24051 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 3, 16,
24052 &pi->tx_rx_cal_phy_saveregs[5]);
24053 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 19, 16,
24054 &pi->tx_rx_cal_phy_saveregs[6]);
24056 write_phy_reg(pi, 0x91, pi->tx_rx_cal_phy_saveregs[7]);
24057 write_phy_reg(pi, 0x92, pi->tx_rx_cal_phy_saveregs[8]);
24059 write_phy_reg(pi, 0x297, pi->tx_rx_cal_phy_saveregs[9]);
24060 write_phy_reg(pi, 0x29b, pi->tx_rx_cal_phy_saveregs[10]);
24062 if (NREV_IS(pi->pubpi.phy_rev, 7)
24063 || NREV_GE(pi->pubpi.phy_rev, 8))
24065 pi, (0x1 << 7), 0, 0,
24069 wlc_phy_resetcca_nphy(pi);
24071 if (pi->use_int_tx_iqlo_cal_nphy
24072 && !(pi->internal_tx_iqlo_cal_tapoff_intpa_nphy)) {
24074 if (NREV_IS(pi->pubpi.phy_rev, 7)) {
24075 if (CHSPEC_IS2G(pi->radio_chanspec)) {
24077 pi,
24081 pi,
24086 pi,
24090 pi,
24095 mod_radio_reg(pi, RADIO_2057_OVR_REG0, 1 << 4,
24097 } else if (NREV_GE(pi->pubpi.phy_rev, 8)) {
24099 pi,
24107 mod_phy_reg(pi, 0xa6, mask, pi->tx_rx_cal_phy_saveregs[0]);
24108 mod_phy_reg(pi, 0xa7, mask, pi->tx_rx_cal_phy_saveregs[1]);
24109 write_phy_reg(pi, 0xa5, pi->tx_rx_cal_phy_saveregs[2]);
24111 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 2, 16,
24112 &pi->tx_rx_cal_phy_saveregs[3]);
24114 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 18, 16,
24115 &pi->tx_rx_cal_phy_saveregs[4]);
24117 write_phy_reg(pi, 0x91, pi->tx_rx_cal_phy_saveregs[5]);
24118 write_phy_reg(pi, 0x92, pi->tx_rx_cal_phy_saveregs[6]);
24123 wlc_phy_est_tonepwr_nphy(struct brcms_phy *pi, s32 *qdBm_pwrbuf, u8 num_samps)
24132 tssi_reg = read_phy_reg(pi, 0x1e9);
24141 CHSPEC_IS5G(pi->radio_chanspec) ?
24144 wlc_phy_poll_rssi_nphy(pi, tssi_type, rssi_buf, num_samps);
24162 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 1,
24164 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 1,
24168 static void wlc_phy_update_txcal_ladder_nphy(struct brcms_phy *pi, u16 core)
24188 ((pi->nphy_txcal_bbmult >> 8) & 0xff) :
24189 (pi->nphy_txcal_bbmult & 0xff);
24197 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, index, 16,
24205 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, index + 32,
24210 static u8 wlc_phy_txpwr_idx_cur_get_nphy(struct brcms_phy *pi, u8 core)
24213 tmp = read_phy_reg(pi, ((core == PHY_CORE_0) ? 0x1ed : 0x1ee));
24220 wlc_phy_txpwr_idx_cur_set_nphy(struct brcms_phy *pi, u8 idx0, u8 idx1)
24222 mod_phy_reg(pi, 0x1e7, (0x7f << 0), idx0);
24224 if (NREV_GT(pi->pubpi.phy_rev, 1))
24225 mod_phy_reg(pi, 0x222, (0xff << 0), idx1);
24228 static u16 wlc_phy_ipa_get_bbmult_nphy(struct brcms_phy *pi)
24232 wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m0m1);
24237 static void wlc_phy_ipa_set_bbmult_nphy(struct brcms_phy *pi, u8 m0, u8 m1)
24241 wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &m0m1);
24242 wlc_phy_table_write_nphy(pi, 15, 1, 95, 16, &m0m1);
24246 wlc_phy_papd_cal_setup_nphy(struct brcms_phy *pi,
24254 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
24256 if (NREV_IS(pi->pubpi.phy_rev, 7)
24257 || NREV_GE(pi->pubpi.phy_rev, 8))
24259 pi, (0x1 << 7),
24261 (pi,
24265 if (CHSPEC_IS2G(pi->radio_chanspec)) {
24266 if (pi->pubpi.radiorev == 5)
24268 else if ((pi->pubpi.radiorev == 7)
24269 || (pi->pubpi.radiorev == 8))
24271 else if ((pi->pubpi.radiorev <= 4)
24272 || (pi->pubpi.radiorev == 6))
24275 if ((pi->pubpi.radiorev == 4) ||
24276 (pi->pubpi.radiorev == 6))
24278 else if ((pi->pubpi.radiorev == 3)
24279 || (pi->pubpi.radiorev == 7)
24280 || (pi->pubpi.radiorev == 8))
24284 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11),
24289 pi,
24293 pi,
24297 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
24300 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2), 1,
24303 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), 0,
24306 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1), 1,
24309 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 8), 0,
24312 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 9), 1,
24315 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 10), 0,
24318 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3), 1,
24322 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 5),
24325 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 4), 0,
24329 state->afectrl[core] = read_phy_reg(pi, (core == PHY_CORE_0) ?
24332 read_phy_reg(pi, (core == PHY_CORE_0) ? 0x8f : 0xa5);
24334 read_phy_reg(pi, (core == PHY_CORE_0) ? 0xa7 : 0xa6);
24336 read_phy_reg(pi, (core == PHY_CORE_0) ? 0xa5 : 0x8f);
24338 mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0xa6 : 0xa7),
24340 mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0x8f :
24343 mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0xa7 : 0xa6),
24345 mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0xa5 :
24348 if (CHSPEC_IS2G(pi->radio_chanspec)) {
24350 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
24353 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
24356 READ_RADIO_REG3(pi, RADIO_2057, TX, off_core,
24359 READ_RADIO_REG3(pi, RADIO_2057, TX, off_core,
24362 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24365 if ((pi->pubpi.radiorev == 3) ||
24366 (pi->pubpi.radiorev == 4) ||
24367 (pi->pubpi.radiorev == 6))
24368 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24370 else if (pi->pubpi.radiorev == 5)
24371 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24374 else if ((pi->pubpi.radiorev == 7)
24375 || (pi->pubpi.radiorev == 8))
24376 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24379 WRITE_RADIO_REG3(pi, RADIO_2057, TX, off_core,
24381 WRITE_RADIO_REG3(pi, RADIO_2057, TX, off_core,
24385 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
24388 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
24391 READ_RADIO_REG3(pi, RADIO_2057, TX, off_core,
24394 READ_RADIO_REG3(pi, RADIO_2057, TX, off_core,
24397 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24400 if ((pi->pubpi.radiorev == 7)
24401 || (pi->pubpi.radiorev == 8))
24402 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24406 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24409 WRITE_RADIO_REG3(pi, RADIO_2057, TX, off_core,
24411 WRITE_RADIO_REG3(pi, RADIO_2057, TX, off_core,
24417 wlc_phy_tx_tone_nphy(pi, tone_freq, 181, 0, 0, false);
24419 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
24422 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
24425 mod_phy_reg(pi, (off_core == PHY_CORE_0) ? 0x297 :
24428 mod_phy_reg(pi, (off_core == PHY_CORE_0) ? 0x2a3 :
24433 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12), 0, 0x3, 0);
24435 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 1, 0, 0);
24437 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 0), 0, 0x3, 0);
24439 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 2), 1, 0x3, 0);
24440 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 1), 1, 0x3, 0);
24442 state->afectrl[core] = read_phy_reg(pi, (core == PHY_CORE_0) ?
24445 read_phy_reg(pi, (core == PHY_CORE_0) ? 0x8f : 0xa5);
24447 mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0xa6 : 0xa7),
24449 mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0x8f :
24456 READ_RADIO_REG2(pi, RADIO_2056, RX, core, VGA_MASTER);
24457 WRITE_RADIO_REG2(pi, RADIO_2056, RX, core, VGA_MASTER, 0x2b);
24458 if (CHSPEC_IS2G(pi->radio_chanspec)) {
24460 READ_RADIO_REG2(pi, RADIO_2056, RX, core,
24463 READ_RADIO_REG2(pi, RADIO_2056, TX, core,
24466 WRITE_RADIO_REG2(pi, RADIO_2056, RX, core, TXFBMIX_G,
24468 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
24472 READ_RADIO_REG2(pi, RADIO_2056, RX, core,
24475 READ_RADIO_REG2(pi, RADIO_2056, TX, core,
24478 WRITE_RADIO_REG2(pi, RADIO_2056, RX, core, TXFBMIX_A,
24480 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
24487 wlc_phy_tx_tone_nphy(pi, tone_freq, 181, 0, 0, false);
24489 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
24492 mod_phy_reg(pi, (off_core == PHY_CORE_0) ? 0x297 :
24495 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 0, 0x3, 0);
24500 wlc_phy_papd_cal_cleanup_nphy(struct brcms_phy *pi,
24505 wlc_phy_stopplayback_nphy(pi);
24507 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
24509 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
24511 if (CHSPEC_IS2G(pi->radio_chanspec)) {
24512 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24514 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24518 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24520 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24526 if ((pi->pubpi.radiorev == 4) || (pi->pubpi.radiorev == 6))
24528 pi, (0x1 << 2),
24533 pi, (0x1 << 2),
24537 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1),
24540 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), 0, 0x3, 1,
24542 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2), 0, 0x3, 1,
24544 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11), 1, 0x3, 1,
24546 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3), 0, 0x3, 1,
24548 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11), 0, 0x3, 1,
24550 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 12), 0, 0x3, 1,
24552 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2), 1, 0x3, 1,
24554 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), 0, 0x3, 1,
24556 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1), 1, 0x3, 1,
24558 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 8), 0, 0x3, 1,
24560 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 9), 1, 0x3, 1,
24562 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 10), 0, 0x3, 1,
24564 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3), 1, 0x3, 1,
24566 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 5), 0, 0x3, 1,
24568 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 4), 0, 0x3, 1,
24571 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
24573 write_phy_reg(pi, (core == PHY_CORE_0) ?
24575 write_phy_reg(pi, (core == PHY_CORE_0) ? 0x8f :
24579 wlc_phy_ipa_set_bbmult_nphy(pi, (state->mm >> 8) & 0xff,
24582 if (NREV_IS(pi->pubpi.phy_rev, 7)
24583 || NREV_GE(pi->pubpi.phy_rev, 8))
24585 pi, (0x1 << 7), 0, 0,
24589 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12), 0, 0x3, 1);
24590 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 13), 0, 0x3, 1);
24591 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 0), 0, 0x3, 1);
24593 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 2), 0, 0x3, 1);
24594 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 1), 0, 0x3, 1);
24596 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
24598 WRITE_RADIO_REG2(pi, RADIO_2056, RX, core, VGA_MASTER,
24600 if (CHSPEC_IS2G(pi->radio_chanspec)) {
24601 WRITE_RADIO_REG2(pi, RADIO_2056, RX, core,
24603 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
24607 WRITE_RADIO_REG2(pi, RADIO_2056, RX, core,
24609 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
24614 write_phy_reg(pi, (core == PHY_CORE_0) ?
24616 write_phy_reg(pi, (core == PHY_CORE_0) ? 0x8f :
24620 wlc_phy_ipa_set_bbmult_nphy(pi, (state->mm >> 8) & 0xff,
24623 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 0, 0x3, 1);
24628 wlc_phy_a1_nphy(struct brcms_phy *pi, u8 core, u32 winsz, u32 start,
24642 wlc_phy_table_read_nphy(pi,
24671 wlc_phy_table_write_nphy(pi,
24680 wlc_phy_a2_nphy(struct brcms_phy *pi, struct nphy_ipa_txcalgains *txgains,
24689 if (NREV_LT(pi->pubpi.phy_rev, 3))
24694 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
24696 phy_a9 = wlc_phy_get_tx_gain_nphy(pi);
24698 if (CHSPEC_IS2G(pi->radio_chanspec))
24711 pi,
24715 if (CHSPEC_IS2G(pi->radio_chanspec)) {
24716 if ((pi->pubpi.radiorev <= 4)
24717 || (pi->pubpi.radiorev == 6))
24718 m[core] = (pi->bw == WL_CHANSPEC_BW_40) ?
24721 m[core] = (pi->bw == WL_CHANSPEC_BW_40) ?
24724 m[core] = (pi->bw == WL_CHANSPEC_BW_40) ? 75 : 107;
24728 wlc_phy_ipa_set_bbmult_nphy(pi, m[0], m[1]);
24732 if (CHSPEC_IS2G(pi->radio_chanspec)) {
24733 if ((pi->pubpi.radiorev == 4)
24734 || (pi->pubpi.radiorev == 6)) {
24742 if ((pi->pubpi.radiorev == 5)
24743 || (pi->pubpi.radiorev == 7)
24744 || (pi->pubpi.radiorev == 8)) {
24754 if ((pi->pubpi.radiorev == 5)
24755 && (CHSPEC_IS2G(pi->radio_chanspec)))
24757 else if (((pi->pubpi.radiorev == 7) &&
24758 (CHSPEC_IS2G(pi->radio_chanspec))) ||
24759 ((pi->pubpi.radiorev == 8) &&
24760 (CHSPEC_IS2G(pi->radio_chanspec))))
24771 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
24774 mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x297 :
24777 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
24780 mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x2a3 :
24783 write_phy_reg(pi, 0x2a1, 0x80);
24784 write_phy_reg(pi, 0x2a2, 0x100);
24786 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
24789 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
24792 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
24795 write_phy_reg(pi, 0x2e5, 0x20);
24797 mod_phy_reg(pi, 0x2a0, (0x3f << 0), (phy_a3) << 0);
24799 mod_phy_reg(pi, 0x29f, (0x3f << 0), (phy_a1) << 0);
24801 mod_phy_reg(pi, 0x29f, (0x3f << 8), (phy_a2) << 8);
24803 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
24806 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
24810 write_phy_reg(pi, 0x2be, 1);
24811 SPINWAIT(read_phy_reg(pi, 0x2be), 10 * 1000 * 1000);
24813 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
24817 wlc_phy_table_write_nphy(pi,
24824 if (CHSPEC_IS5G(pi->radio_chanspec))
24825 wlc_phy_a1_nphy(pi, core, 5, 0, 35);
24829 pi,
24838 if (CHSPEC_IS2G(pi->radio_chanspec)) {
24839 if (NREV_GE(pi->pubpi.phy_rev, 6) &&
24840 pi->sh->chip == BCMA_CHIP_ID_BCM47162) {
24842 } else if (NREV_GE(pi->pubpi.phy_rev, 6)) {
24844 } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
24852 wlc_phy_rfctrl_override_nphy(pi,
24857 wlc_phy_rfctrl_override_nphy(pi,
24864 if (CHSPEC_IS2G(pi->radio_chanspec))
24865 m[core] = (pi->bw == WL_CHANSPEC_BW_40) ? 45 : 64;
24867 m[core] = (pi->bw == WL_CHANSPEC_BW_40) ? 75 : 107;
24870 wlc_phy_ipa_set_bbmult_nphy(pi, m[0], m[1]);
24889 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
24892 mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x297 :
24895 if (NREV_GE(pi->pubpi.phy_rev, 6)) {
24896 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
24899 mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x2a3 :
24902 write_phy_reg(pi, 0x2a1, 0x20);
24903 write_phy_reg(pi, 0x2a2, 0x60);
24905 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
24908 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
24911 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
24914 write_phy_reg(pi, 0x2e5, 0x20);
24916 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
24919 mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x2a3 :
24922 write_phy_reg(pi, 0x2a1, 0x80);
24923 write_phy_reg(pi, 0x2a2, 0x600);
24925 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
24928 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
24931 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
24934 mod_phy_reg(pi, 0x2a0, (0x3f << 8), (0x20) << 8);
24938 mod_phy_reg(pi, 0x2a0, (0x3f << 0), (phy_a3) << 0);
24940 mod_phy_reg(pi, 0x29f, (0x3f << 0), (phy_a1) << 0);
24942 mod_phy_reg(pi, 0x29f, (0x3f << 8), (phy_a2) << 8);
24944 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 1, 0x3, 0);
24946 write_phy_reg(pi, 0x2be, 1);
24947 SPINWAIT(read_phy_reg(pi, 0x2be), 10 * 1000 * 1000);
24949 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 0, 0x3, 0);
24951 wlc_phy_table_write_nphy(pi,
24958 wlc_phy_a1_nphy(pi, core, 5, 0, 40);
24962 static u8 wlc_phy_a3_nphy(struct brcms_phy *pi, u8 start_gain, u8 core)
24981 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
24986 if (CHSPEC_IS2G(pi->radio_chanspec)) {
24987 if (pi->pubpi.radiorev == 5) {
24993 } else if ((pi->pubpi.radiorev == 7)
24994 || (pi->pubpi.radiorev == 8)) {
25016 if (CHSPEC_IS2G(pi->radio_chanspec))
25023 wlc_phy_a2_nphy(pi, &phy_a4, CAL_GCTRL, core);
25025 wlc_phy_table_read_nphy(pi,
25065 wlc_phy_a2_nphy(pi, &phy_a4, CAL_GCTRL, core);
25067 wlc_phy_table_read_nphy(pi,
25104 if (NREV_GE(pi->pubpi.phy_rev, 7))
25111 static void wlc_phy_a4(struct brcms_phy *pi, bool full_cal)
25128 if (pi->nphy_papd_skip == 1)
25131 phy_b3 = (0 == (bcma_read32(pi->d11core, D11REGOFFS(maccontrol)) &
25134 wlapi_suspend_mac_and_wait(pi->sh->physhim);
25136 wlc_phy_stay_in_carriersearch_nphy(pi, true);
25138 pi->nphy_force_papd_cal = false;
25140 for (phy_b5 = 0; phy_b5 < pi->pubpi.phy_corenum; phy_b5++)
25141 pi->nphy_papd_tx_gain_at_last_cal[phy_b5] =
25142 wlc_phy_txpwr_idx_cur_get_nphy(pi, phy_b5);
25144 pi->nphy_papd_last_cal = pi->sh->now;
25145 pi->nphy_papd_recal_counter++;
25147 phy_b4 = pi->nphy_txpwrctrl;
25148 wlc_phy_txpwrctrl_enable_nphy(pi, PHY_TPC_HW_OFF);
25150 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_SCALARTBL0, 64, 0, 32,
25152 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_SCALARTBL1, 64, 0, 32,
25155 phy_b9 = read_phy_reg(pi, 0x01);
25156 mod_phy_reg(pi, 0x01, (0x1 << 15), 0);
25158 for (phy_b5 = 0; phy_b5 < pi->pubpi.phy_corenum; phy_b5++) {
25161 wlc_phy_table_write_nphy(pi,
25169 wlc_phy_ipa_restore_tx_digi_filts_nphy(pi);
25171 phy_b2.mm = wlc_phy_ipa_get_bbmult_nphy(pi);
25172 for (phy_b5 = 0; phy_b5 < pi->pubpi.phy_corenum; phy_b5++) {
25173 wlc_phy_papd_cal_setup_nphy(pi, &phy_b2, phy_b5);
25175 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
25176 if (CHSPEC_IS2G(pi->radio_chanspec)) {
25177 if ((pi->pubpi.radiorev == 3)
25178 || (pi->pubpi.radiorev == 4)
25179 || (pi->pubpi.radiorev == 6)) {
25180 pi->nphy_papd_cal_gain_index[phy_b5] =
25182 } else if (pi->pubpi.radiorev == 5) {
25183 pi->nphy_papd_cal_gain_index[phy_b5] =
25185 pi->nphy_papd_cal_gain_index[phy_b5] =
25187 pi,
25188 pi->
25193 } else if ((pi->pubpi.radiorev == 7)
25194 || (pi->pubpi.radiorev == 8)) {
25196 pi->nphy_papd_cal_gain_index[phy_b5] =
25198 pi->nphy_papd_cal_gain_index[phy_b5] =
25200 pi,
25201 pi->
25209 pi->nphy_papd_cal_gain_index[phy_b5];
25212 pi->nphy_papd_cal_gain_index[phy_b5] = 0;
25213 pi->nphy_papd_cal_gain_index[phy_b5] =
25215 pi,
25216 pi->
25220 pi->nphy_papd_cal_gain_index[phy_b5];
25226 wlc_phy_a3_nphy(pi, phy_b1[phy_b5].index,
25229 pi->nphy_papd_cal_gain_index[phy_b5] =
25233 switch (pi->nphy_papd_cal_type) {
25235 wlc_phy_a2_nphy(pi, &phy_b1[phy_b5], CAL_FULL, phy_b5);
25238 wlc_phy_a2_nphy(pi, &phy_b1[phy_b5], CAL_SOFT, phy_b5);
25242 if (NREV_GE(pi->pubpi.phy_rev, 7))
25243 wlc_phy_papd_cal_cleanup_nphy(pi, &phy_b2);
25246 if (NREV_LT(pi->pubpi.phy_rev, 7))
25247 wlc_phy_papd_cal_cleanup_nphy(pi, &phy_b2);
25249 for (phy_b5 = 0; phy_b5 < pi->pubpi.phy_corenum; phy_b5++) {
25252 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
25253 if (CHSPEC_IS2G(pi->radio_chanspec)) {
25254 if (pi->pubpi.radiorev == 3)
25256 else if (pi->pubpi.radiorev == 5)
25264 if (CHSPEC_IS2G(pi->radio_chanspec)) {
25267 if ((pi->pubpi.radiorev == 3) ||
25268 (pi->pubpi.radiorev == 4) ||
25269 (pi->pubpi.radiorev == 6)) {
25274 } else if (pi->pubpi.radiorev == 5) {
25278 } else if ((pi->pubpi.radiorev == 7) ||
25279 (pi->pubpi.radiorev == 8)) {
25286 if ((pi->pubpi.radiorev == 3) ||
25287 (pi->pubpi.radiorev == 4) ||
25288 (pi->pubpi.radiorev == 6))
25293 else if ((pi->pubpi.radiorev == 7)
25294 || (pi->pubpi.radiorev == 8))
25302 if (CHSPEC_IS2G(pi->radio_chanspec))
25311 mod_phy_reg(pi, (phy_b5 == PHY_CORE_0) ? 0x298 :
25314 pi->nphy_papd_epsilon_offset[phy_b5] = phy_b6;
25316 if (NREV_LT(pi->pubpi.phy_rev, 5))
25323 if (CHSPEC_IS2G(pi->radio_chanspec)) {
25339 mod_phy_reg(pi, (phy_b5 == PHY_CORE_0) ? 0x298 :
25342 pi->nphy_papd_epsilon_offset[phy_b5] = phy_b6;
25346 mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x297 :
25349 mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x297 :
25352 if (NREV_GE(pi->pubpi.phy_rev, 6)) {
25353 mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x2a3 :
25356 mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x2a3 :
25360 mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x2a3 :
25363 mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x2a3 :
25367 pi->nphy_papdcomp = NPHY_PAPD_COMP_ON;
25369 write_phy_reg(pi, 0x01, phy_b9);
25371 wlc_phy_ipa_set_tx_digi_filts_nphy(pi);
25373 wlc_phy_txpwrctrl_enable_nphy(pi, phy_b4);
25375 wlc_phy_txpwr_index_nphy(pi, (1 << 0),
25376 (s8) (pi->nphy_txpwrindex[0].
25378 wlc_phy_txpwr_index_nphy(pi, (1 << 1),
25379 (s8) (pi->nphy_txpwrindex[1].
25383 wlc_phy_stay_in_carriersearch_nphy(pi, false);
25386 wlapi_enable_mac(pi->sh->physhim);
25389 void wlc_phy_cal_perical_nphy_run(struct brcms_phy *pi, u8 caltype)
25397 if (PHY_MUTED(pi))
25401 fullcal = (pi->radio_chanspec != pi->nphy_txiqlocal_chanspec);
25405 if (pi->cal_type_override != PHY_PERICAL_AUTO)
25407 (pi->cal_type_override ==
25410 if (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_INIT) {
25411 if (pi->nphy_txiqlocal_chanspec != pi->radio_chanspec)
25412 wlc_phy_cal_perical_mphase_restart(pi);
25415 if (pi->mphase_cal_phase_id == MPHASE_CAL_STATE_RXCAL)
25416 wlapi_bmac_write_shm(pi->sh->physhim, M_CTS_DURATION, 10000);
25418 wlapi_suspend_mac_and_wait(pi->sh->physhim);
25420 wlc_phyreg_enter((struct brcms_phy_pub *) pi);
25422 if ((pi->mphase_cal_phase_id == MPHASE_CAL_STATE_IDLE) ||
25423 (pi->mphase_cal_phase_id == MPHASE_CAL_STATE_INIT)) {
25424 pi->nphy_cal_orig_pwr_idx[0] =
25425 (u8) ((read_phy_reg(pi, 0x1ed) >> 8) & 0x7f);
25426 pi->nphy_cal_orig_pwr_idx[1] =
25427 (u8) ((read_phy_reg(pi, 0x1ee) >> 8) & 0x7f);
25429 if (pi->nphy_txpwrctrl != PHY_TPC_HW_OFF) {
25430 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2,
25432 pi->nphy_cal_orig_tx_gain);
25434 pi->nphy_cal_orig_tx_gain[0] = 0;
25435 pi->nphy_cal_orig_tx_gain[1] = 0;
25438 target_gain = wlc_phy_get_tx_gain_nphy(pi);
25439 tx_pwr_ctrl_state = pi->nphy_txpwrctrl;
25440 wlc_phy_txpwrctrl_enable_nphy(pi, PHY_TPC_HW_OFF);
25442 if (pi->antsel_type == ANTSEL_2x3)
25443 wlc_phy_antsel_init((struct brcms_phy_pub *) pi, true);
25445 mphase = (pi->mphase_cal_phase_id != MPHASE_CAL_STATE_IDLE);
25448 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
25449 wlc_phy_precal_txgain_nphy(pi);
25450 pi->nphy_cal_target_gain = wlc_phy_get_tx_gain_nphy(pi);
25453 target_gain = pi->nphy_cal_target_gain;
25456 wlc_phy_cal_txiqlo_nphy(pi, target_gain, fullcal,
25458 if (PHY_IPA(pi))
25459 wlc_phy_a4(pi, true);
25461 wlc_phyreg_exit((struct brcms_phy_pub *) pi);
25462 wlapi_enable_mac(pi->sh->physhim);
25463 wlapi_bmac_write_shm(pi->sh->physhim, M_CTS_DURATION,
25465 wlapi_suspend_mac_and_wait(pi->sh->physhim);
25466 wlc_phyreg_enter((struct brcms_phy_pub *) pi);
25468 if (0 == wlc_phy_cal_rxiq_nphy(pi, target_gain,
25469 (pi->first_cal_after_assoc ||
25470 (pi->cal_type_override ==
25472 wlc_phy_savecal_nphy(pi);
25474 wlc_phy_txpwrctrl_coeff_setup_nphy(pi);
25476 pi->nphy_perical_last = pi->sh->now;
25480 wlc_phy_rssi_cal_nphy(pi);
25482 if (pi->first_cal_after_assoc
25483 || (pi->cal_type_override == PHY_PERICAL_FULL)) {
25484 pi->first_cal_after_assoc = false;
25485 wlc_phy_txpwrctrl_idle_tssi_nphy(pi);
25486 wlc_phy_txpwrctrl_pwr_setup_nphy(pi);
25489 if (NREV_GE(pi->pubpi.phy_rev, 3))
25490 wlc_phy_radio205x_vcocal_nphy(pi);
25492 switch (pi->mphase_cal_phase_id) {
25494 pi->nphy_perical_last = pi->sh->now;
25495 pi->nphy_txiqlocal_chanspec = pi->radio_chanspec;
25497 if (NREV_GE(pi->pubpi.phy_rev, 3))
25498 wlc_phy_precal_txgain_nphy(pi);
25500 pi->nphy_cal_target_gain = wlc_phy_get_tx_gain_nphy(pi);
25501 pi->mphase_cal_phase_id++;
25510 if ((pi->radar_percal_mask & 0x10) != 0)
25511 pi->nphy_rxcal_active = true;
25514 (pi, pi->nphy_cal_target_gain, fullcal,
25517 wlc_phy_cal_perical_mphase_reset(pi);
25521 if (NREV_LE(pi->pubpi.phy_rev, 2) &&
25522 (pi->mphase_cal_phase_id ==
25524 pi->mphase_cal_phase_id += 2;
25526 pi->mphase_cal_phase_id++;
25530 if ((pi->radar_percal_mask & 0x2) != 0)
25531 pi->nphy_rxcal_active = true;
25533 if (PHY_IPA(pi))
25534 wlc_phy_a4(pi, true);
25536 pi->mphase_cal_phase_id++;
25540 if ((pi->radar_percal_mask & 0x1) != 0)
25541 pi->nphy_rxcal_active = true;
25542 if (wlc_phy_cal_rxiq_nphy(pi, target_gain,
25543 (pi->first_cal_after_assoc ||
25544 (pi->cal_type_override ==
25547 wlc_phy_savecal_nphy(pi);
25549 pi->mphase_cal_phase_id++;
25553 if ((pi->radar_percal_mask & 0x4) != 0)
25554 pi->nphy_rxcal_active = true;
25555 wlc_phy_txpwrctrl_coeff_setup_nphy(pi);
25556 wlc_phy_rssi_cal_nphy(pi);
25558 if (NREV_GE(pi->pubpi.phy_rev, 3))
25559 wlc_phy_radio205x_vcocal_nphy(pi);
25563 if (pi->first_cal_after_assoc)
25564 pi->mphase_cal_phase_id++;
25566 wlc_phy_cal_perical_mphase_reset(pi);
25571 if ((pi->radar_percal_mask & 0x8) != 0)
25572 pi->nphy_rxcal_active = true;
25574 if (pi->first_cal_after_assoc) {
25575 pi->first_cal_after_assoc = false;
25576 wlc_phy_txpwrctrl_idle_tssi_nphy(pi);
25577 wlc_phy_txpwrctrl_pwr_setup_nphy(pi);
25580 wlc_phy_cal_perical_mphase_reset(pi);
25584 wlc_phy_cal_perical_mphase_reset(pi);
25589 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
25593 wlc_phy_txpwr_index_nphy(pi, 1,
25594 pi->
25597 wlc_phy_txpwr_index_nphy(pi, 2,
25598 pi->
25602 pi->nphy_txpwrindex[0].index = -1;
25603 pi->nphy_txpwrindex[1].index = -1;
25605 wlc_phy_txpwr_index_nphy(pi, (1 << 0),
25606 (s8) (pi->
25611 wlc_phy_txpwr_index_nphy(pi, (1 << 1),
25612 (s8) (pi->
25621 wlc_phy_txpwrctrl_enable_nphy(pi, tx_pwr_ctrl_state);
25622 wlc_phyreg_exit((struct brcms_phy_pub *) pi);
25623 wlapi_enable_mac(pi->sh->physhim);
25627 wlc_phy_cal_txiqlo_nphy(struct brcms_phy *pi, struct nphy_txgains target_gain,
25709 wlc_phy_stay_in_carriersearch_nphy(pi, true);
25711 if (NREV_GE(pi->pubpi.phy_rev, 4)) {
25712 phyhang_avoid_state = pi->phyhang_avoid;
25713 pi->phyhang_avoid = false;
25716 if (CHSPEC_IS40(pi->radio_chanspec))
25721 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, gain_save);
25724 wlc_phy_iqcal_gainparams_nphy(pi, core_no, target_gain,
25729 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, cal_gain);
25731 wlc_phy_txcal_radio_setup_nphy(pi);
25733 wlc_phy_txcal_physetup_nphy(pi);
25736 if (!(NREV_GE(pi->pubpi.phy_rev, 6) ||
25737 (NREV_IS(pi->pubpi.phy_rev, 5) && PHY_IPA(pi)
25738 && (CHSPEC_IS2G(pi->radio_chanspec))))) {
25747 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, tbl_len, 0,
25757 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, tbl_len, 32,
25761 if (NREV_GE(pi->pubpi.phy_rev, 7))
25762 write_phy_reg(pi, 0xc2, 0x8ad9);
25764 write_phy_reg(pi, 0xc2, 0x8aa9);
25769 if (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_TXPHASE0) {
25770 wlc_phy_runsamples_nphy(pi, phy_bw * 8, 0xffff, 0, 1, 0, false);
25774 wlc_phy_tx_tone_nphy(pi, tone_freq, max_val, 1, 0,
25780 if (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_TXPHASE0) {
25781 tbl_ptr = pi->mphase_txcal_bestcoeffs;
25782 tbl_len = ARRAY_SIZE(pi->mphase_txcal_bestcoeffs);
25783 if (NREV_LT(pi->pubpi.phy_rev, 3))
25786 if ((!fullcal) && (pi->nphy_txiqlocal_coeffsvalid)) {
25788 tbl_ptr = pi->nphy_txiqlocal_bestc;
25789 tbl_len = ARRAY_SIZE(pi->nphy_txiqlocal_bestc);
25790 if (NREV_LT(pi->pubpi.phy_rev, 3))
25796 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
25808 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, tbl_len, 64,
25812 max_cal_cmds = (NREV_GE(pi->pubpi.phy_rev, 3)) ?
25817 max_cal_cmds = (NREV_GE(pi->pubpi.phy_rev, 3)) ?
25824 cal_cnt = pi->mphase_txcal_cmdidx;
25825 if ((cal_cnt + pi->mphase_txcal_numcmds) < max_cal_cmds)
25826 num_cals = cal_cnt + pi->mphase_txcal_numcmds;
25837 cal_cmd = (NREV_GE(pi->pubpi.phy_rev, 3)) ?
25842 cal_cmd = (NREV_GE(pi->pubpi.phy_rev, 3)) ?
25851 if (NREV_GE(pi->pubpi.phy_rev, 6) ||
25852 (NREV_IS(pi->pubpi.phy_rev, 5) &&
25853 PHY_IPA(pi)
25854 && (CHSPEC_IS2G(pi->radio_chanspec)))) {
25857 pi,
25866 write_phy_reg(pi, 0xc1, val);
25871 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
25878 wlc_phy_table_write_nphy(pi,
25884 write_phy_reg(pi, 0xc0, cal_cmd);
25886 SPINWAIT(((read_phy_reg(pi, 0xc0) & 0xc000) != 0),
25888 if (WARN(read_phy_reg(pi, 0xc0) & 0xc000,
25892 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
25894 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL,
25907 pi->mphase_txcal_cmdidx = num_cals;
25908 if (pi->mphase_txcal_cmdidx >= max_cal_cmds)
25909 pi->mphase_txcal_cmdidx = 0;
25913 (NREV_LE(pi->pubpi.phy_rev, 2)) ?
25917 || (pi->mphase_cal_phase_id == mphase_cal_lastphase)) {
25919 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 96,
25921 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 80,
25924 if (NREV_LT(pi->pubpi.phy_rev, 2)) {
25932 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 88,
25935 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 101,
25937 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 85,
25940 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 93,
25943 tbl_len = ARRAY_SIZE(pi->nphy_txiqlocal_bestc);
25944 if (NREV_LT(pi->pubpi.phy_rev, 3))
25947 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
25949 pi->nphy_txiqlocal_bestc);
25951 pi->nphy_txiqlocal_coeffsvalid = true;
25952 pi->nphy_txiqlocal_chanspec = pi->radio_chanspec;
25954 tbl_len = ARRAY_SIZE(pi->mphase_txcal_bestcoeffs);
25955 if (NREV_LT(pi->pubpi.phy_rev, 3))
25958 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
25960 pi->mphase_txcal_bestcoeffs);
25963 wlc_phy_stopplayback_nphy(pi);
25965 write_phy_reg(pi, 0xc2, 0x0000);
25969 wlc_phy_txcal_phycleanup_nphy(pi);
25971 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
25974 wlc_phy_txcal_radio_cleanup_nphy(pi);
25976 if (NREV_LT(pi->pubpi.phy_rev, 2)) {
25978 || (pi->mphase_cal_phase_id == mphase_cal_lastphase))
25979 wlc_phy_tx_iq_war_nphy(pi);
25982 if (NREV_GE(pi->pubpi.phy_rev, 4))
25983 pi->phyhang_avoid = phyhang_avoid_state;
25985 wlc_phy_stay_in_carriersearch_nphy(pi, false);
25990 static void wlc_phy_reapply_txcal_coeffs_nphy(struct brcms_phy *pi)
25994 if ((pi->nphy_txiqlocal_chanspec == pi->radio_chanspec) &&
25995 (pi->nphy_txiqlocal_coeffsvalid)) {
25996 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
25999 if ((pi->nphy_txiqlocal_bestc[0] != tbl_buf[0]) ||
26000 (pi->nphy_txiqlocal_bestc[1] != tbl_buf[1]) ||
26001 (pi->nphy_txiqlocal_bestc[2] != tbl_buf[2]) ||
26002 (pi->nphy_txiqlocal_bestc[3] != tbl_buf[3])) {
26004 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 80,
26005 16, pi->nphy_txiqlocal_bestc);
26011 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 88,
26014 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 85,
26016 &pi->nphy_txiqlocal_bestc[5]);
26018 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 93,
26020 &pi->nphy_txiqlocal_bestc[5]);
26026 wlc_phy_rx_iq_coeffs_nphy(struct brcms_phy *pi, u8 write,
26030 write_phy_reg(pi, 0x9a, pcomp->a0);
26031 write_phy_reg(pi, 0x9b, pcomp->b0);
26032 write_phy_reg(pi, 0x9c, pcomp->a1);
26033 write_phy_reg(pi, 0x9d, pcomp->b1);
26035 pcomp->a0 = read_phy_reg(pi, 0x9a);
26036 pcomp->b0 = read_phy_reg(pi, 0x9b);
26037 pcomp->a1 = read_phy_reg(pi, 0x9c);
26038 pcomp->b1 = read_phy_reg(pi, 0x9d);
26043 wlc_phy_rx_iq_est_nphy(struct brcms_phy *pi, struct phy_iq_est *est,
26048 write_phy_reg(pi, 0x12b, num_samps);
26049 mod_phy_reg(pi, 0x12a, (0xff << 0), (wait_time << 0));
26050 mod_phy_reg(pi, 0x129, NPHY_IqestCmd_iqMode,
26053 mod_phy_reg(pi, 0x129, NPHY_IqestCmd_iqstart, NPHY_IqestCmd_iqstart);
26055 SPINWAIT(((read_phy_reg(pi, 0x129) & NPHY_IqestCmd_iqstart) != 0),
26057 if (WARN(read_phy_reg(pi, 0x129) & NPHY_IqestCmd_iqstart,
26061 if ((read_phy_reg(pi, 0x129) & NPHY_IqestCmd_iqstart) == 0) {
26062 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
26064 (read_phy_reg(pi,
26066 | read_phy_reg(pi, NPHY_IqestipwrAccLo(core));
26068 (read_phy_reg(pi,
26070 | read_phy_reg(pi, NPHY_IqestqpwrAccLo(core));
26072 (read_phy_reg(pi,
26074 read_phy_reg(pi, NPHY_IqestIqAccLo(core));
26080 static void wlc_phy_calc_rx_iq_comp_nphy(struct brcms_phy *pi, u8 core_mask)
26095 wlc_phy_rx_iq_coeffs_nphy(pi, 0, &old_comp);
26097 wlc_phy_rx_iq_coeffs_nphy(pi, 1, &new_comp);
26100 wlc_phy_rx_iq_est_nphy(pi, est, 0x4000, 32, 0);
26104 for (curr_core = 0; curr_core < pi->pubpi.phy_corenum; curr_core++) {
26167 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
26177 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
26199 wlc_phy_rx_iq_coeffs_nphy(pi, 1, &new_comp);
26202 static void wlc_phy_rxcal_radio_setup_nphy(struct brcms_phy *pi, u8 rx_core)
26208 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
26210 if (CHSPEC_IS5G(pi->radio_chanspec)) {
26211 pi->tx_rx_cal_radio_saveregs[0] =
26212 read_radio_reg(pi,
26214 pi->tx_rx_cal_radio_saveregs[1] =
26215 read_radio_reg(pi,
26218 write_radio_reg(pi,
26221 write_radio_reg(pi,
26226 pi->tx_rx_cal_radio_saveregs[0] =
26227 read_radio_reg(pi,
26229 pi->tx_rx_cal_radio_saveregs[1] =
26230 read_radio_reg(pi,
26234 pi,
26238 pi,
26244 if (CHSPEC_IS5G(pi->radio_chanspec)) {
26245 pi->tx_rx_cal_radio_saveregs[0] =
26246 read_radio_reg(pi,
26248 pi->tx_rx_cal_radio_saveregs[1] =
26249 read_radio_reg(pi,
26253 pi,
26257 pi,
26262 pi->tx_rx_cal_radio_saveregs[0] =
26263 read_radio_reg(pi,
26265 pi->tx_rx_cal_radio_saveregs[1] =
26266 read_radio_reg(pi,
26269 write_radio_reg(pi,
26272 write_radio_reg(pi,
26280 pi->tx_rx_cal_radio_saveregs[0] =
26281 read_radio_reg(pi,
26284 pi->tx_rx_cal_radio_saveregs[1] =
26285 read_radio_reg(pi,
26289 if (pi->pubpi.radiorev >= 5) {
26290 pi->tx_rx_cal_radio_saveregs[2] =
26291 read_radio_reg(pi,
26294 pi->tx_rx_cal_radio_saveregs[3] =
26295 read_radio_reg(pi,
26300 if (CHSPEC_IS5G(pi->radio_chanspec)) {
26302 if (pi->pubpi.radiorev >= 5) {
26303 pi->tx_rx_cal_radio_saveregs[4] =
26304 read_radio_reg(pi,
26309 pi,
26313 write_radio_reg(pi,
26317 write_radio_reg(pi,
26321 pi->tx_rx_cal_radio_saveregs[4] =
26322 read_radio_reg(pi,
26327 (pi->tx_rx_cal_radio_saveregs
26332 mod_radio_reg(pi,
26338 write_radio_reg(pi,
26341 write_radio_reg(pi,
26345 if (pi->pubpi.radiorev >= 5) {
26346 pi->tx_rx_cal_radio_saveregs[4] =
26348 pi,
26353 pi,
26358 pi,
26364 pi,
26370 pi->tx_rx_cal_radio_saveregs[4] =
26372 pi,
26377 (pi->
26383 mod_radio_reg(pi,
26389 write_radio_reg(pi,
26392 write_radio_reg(pi,
26398 pi->tx_rx_cal_radio_saveregs[0] =
26399 read_radio_reg(pi,
26402 pi->tx_rx_cal_radio_saveregs[1] =
26403 read_radio_reg(pi,
26407 if (pi->pubpi.radiorev >= 5) {
26408 pi->tx_rx_cal_radio_saveregs[2] =
26409 read_radio_reg(pi,
26412 pi->tx_rx_cal_radio_saveregs[3] =
26413 read_radio_reg(pi,
26418 if (CHSPEC_IS5G(pi->radio_chanspec)) {
26420 if (pi->pubpi.radiorev >= 5) {
26421 pi->tx_rx_cal_radio_saveregs[4] =
26423 pi,
26428 pi,
26433 pi,
26439 pi,
26444 pi->tx_rx_cal_radio_saveregs[4] =
26446 pi,
26451 (pi->
26457 mod_radio_reg(pi,
26463 write_radio_reg(pi,
26466 write_radio_reg(pi,
26470 if (pi->pubpi.radiorev >= 5) {
26471 pi->tx_rx_cal_radio_saveregs[4] =
26473 pi,
26478 pi,
26483 pi,
26489 pi,
26494 pi->tx_rx_cal_radio_saveregs[4] =
26496 pi,
26501 (pi->
26507 mod_radio_reg(pi,
26513 write_radio_reg(pi,
26516 write_radio_reg(pi,
26524 static void wlc_phy_rxcal_radio_cleanup_nphy(struct brcms_phy *pi, u8 rx_core)
26526 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
26528 if (CHSPEC_IS5G(pi->radio_chanspec)) {
26530 pi,
26532 pi->
26535 pi,
26537 pi->
26542 pi,
26544 pi->
26547 pi,
26549 pi->
26554 if (CHSPEC_IS5G(pi->radio_chanspec)) {
26556 pi,
26558 pi->
26561 pi,
26563 pi->
26568 pi,
26570 pi->
26573 pi,
26575 pi->
26582 write_radio_reg(pi,
26585 pi->tx_rx_cal_radio_saveregs[0]);
26587 write_radio_reg(pi,
26590 pi->tx_rx_cal_radio_saveregs[1]);
26592 if (pi->pubpi.radiorev >= 5) {
26593 write_radio_reg(pi,
26596 pi->
26599 write_radio_reg(pi,
26602 pi->
26606 if (CHSPEC_IS5G(pi->radio_chanspec)) {
26607 if (pi->pubpi.radiorev >= 5)
26609 pi,
26612 pi->
26617 pi,
26620 pi->
26624 if (pi->pubpi.radiorev >= 5)
26626 pi,
26629 pi->
26634 pi,
26637 pi->
26643 write_radio_reg(pi,
26646 pi->tx_rx_cal_radio_saveregs[0]);
26648 write_radio_reg(pi,
26651 pi->tx_rx_cal_radio_saveregs[1]);
26653 if (pi->pubpi.radiorev >= 5) {
26654 write_radio_reg(pi,
26657 pi->
26660 write_radio_reg(pi,
26663 pi->
26667 if (CHSPEC_IS5G(pi->radio_chanspec)) {
26668 if (pi->pubpi.radiorev >= 5)
26670 pi,
26673 pi->
26678 pi,
26681 pi->
26685 if (pi->pubpi.radiorev >= 5)
26687 pi,
26690 pi->
26695 pi,
26698 pi->
26706 static void wlc_phy_rxcal_physetup_nphy(struct brcms_phy *pi, u8 rx_core)
26711 if (NREV_GE(pi->pubpi.phy_rev, 7))
26716 pi->tx_rx_cal_phy_saveregs[0] = read_phy_reg(pi, 0xa2);
26717 pi->tx_rx_cal_phy_saveregs[1] =
26718 read_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0xa6 : 0xa7);
26719 pi->tx_rx_cal_phy_saveregs[2] =
26720 read_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0x8f : 0xa5);
26721 pi->tx_rx_cal_phy_saveregs[3] = read_phy_reg(pi, 0x91);
26722 pi->tx_rx_cal_phy_saveregs[4] = read_phy_reg(pi, 0x92);
26723 pi->tx_rx_cal_phy_saveregs[5] = read_phy_reg(pi, 0x7a);
26724 pi->tx_rx_cal_phy_saveregs[6] = read_phy_reg(pi, 0x7d);
26725 pi->tx_rx_cal_phy_saveregs[7] = read_phy_reg(pi, 0xe7);
26726 pi->tx_rx_cal_phy_saveregs[8] = read_phy_reg(pi, 0xec);
26727 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
26728 pi->tx_rx_cal_phy_saveregs[11] = read_phy_reg(pi, 0x342);
26729 pi->tx_rx_cal_phy_saveregs[12] = read_phy_reg(pi, 0x343);
26730 pi->tx_rx_cal_phy_saveregs[13] = read_phy_reg(pi, 0x346);
26731 pi->tx_rx_cal_phy_saveregs[14] = read_phy_reg(pi, 0x347);
26734 pi->tx_rx_cal_phy_saveregs[9] = read_phy_reg(pi, 0x297);
26735 pi->tx_rx_cal_phy_saveregs[10] = read_phy_reg(pi, 0x29b);
26736 mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x297 :
26739 mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x297 :
26742 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
26744 mod_phy_reg(pi, 0xa2, (0xf << 0), (1 << tx_core) << 0);
26746 mod_phy_reg(pi, 0xa2, (0xf << 12), (1 << (1 - rx_core)) << 12);
26750 mod_phy_reg(pi, 0xa2, (0xf << 12), (1 << tx_core) << 12);
26751 mod_phy_reg(pi, 0xa2, (0xf << 0), (1 << tx_core) << 0);
26752 mod_phy_reg(pi, 0xa2, (0xf << 4), (1 << rx_core) << 4);
26753 mod_phy_reg(pi, 0xa2, (0xf << 8), (1 << rx_core) << 8);
26756 mod_phy_reg(pi, ((rx_core == PHY_CORE_0) ? 0xa6 : 0xa7), (0x1 << 2), 0);
26757 mod_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0x8f : 0xa5,
26759 if (NREV_LT(pi->pubpi.phy_rev, 7)) {
26760 mod_phy_reg(pi, ((rx_core == PHY_CORE_0) ? 0xa6 : 0xa7),
26762 mod_phy_reg(pi, (rx_core == PHY_CORE_0) ?
26767 wlc_phy_rfctrlintc_override_nphy(pi, NPHY_RfctrlIntc_override_PA, 0,
26771 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
26772 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
26775 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 9), 0, 0, 0,
26777 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 10), 1, 0, 0,
26779 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), 1, 0, 0,
26781 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1), 1, 0, 0,
26783 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11), 0, 0, 0,
26785 if (CHSPEC_IS40(pi->radio_chanspec))
26787 pi,
26793 pi,
26798 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 7),
26801 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 5), 0, 0, 0,
26804 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 0, 3, 0);
26807 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX);
26809 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
26811 wlc_phy_rfctrlintc_override_nphy(pi,
26824 wlc_phy_rfctrlintc_override_nphy(pi,
26827 wlc_phy_rfctrlintc_override_nphy(pi,
26833 static void wlc_phy_rxcal_phycleanup_nphy(struct brcms_phy *pi, u8 rx_core)
26836 write_phy_reg(pi, 0xa2, pi->tx_rx_cal_phy_saveregs[0]);
26837 write_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0xa6 : 0xa7,
26838 pi->tx_rx_cal_phy_saveregs[1]);
26839 write_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0x8f : 0xa5,
26840 pi->tx_rx_cal_phy_saveregs[2]);
26841 write_phy_reg(pi, 0x91, pi->tx_rx_cal_phy_saveregs[3]);
26842 write_phy_reg(pi, 0x92, pi->tx_rx_cal_phy_saveregs[4]);
26844 write_phy_reg(pi, 0x7a, pi->tx_rx_cal_phy_saveregs[5]);
26845 write_phy_reg(pi, 0x7d, pi->tx_rx_cal_phy_saveregs[6]);
26846 write_phy_reg(pi, 0xe7, pi->tx_rx_cal_phy_saveregs[7]);
26847 write_phy_reg(pi, 0xec, pi->tx_rx_cal_phy_saveregs[8]);
26848 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
26849 write_phy_reg(pi, 0x342, pi->tx_rx_cal_phy_saveregs[11]);
26850 write_phy_reg(pi, 0x343, pi->tx_rx_cal_phy_saveregs[12]);
26851 write_phy_reg(pi, 0x346, pi->tx_rx_cal_phy_saveregs[13]);
26852 write_phy_reg(pi, 0x347, pi->tx_rx_cal_phy_saveregs[14]);
26855 write_phy_reg(pi, 0x297, pi->tx_rx_cal_phy_saveregs[9]);
26856 write_phy_reg(pi, 0x29b, pi->tx_rx_cal_phy_saveregs[10]);
26860 wlc_phy_rxcal_gainctrl_nphy_rev5(struct brcms_phy *pi, u8 rx_core,
26882 if (NREV_GE(pi->pubpi.phy_rev, 7))
26890 wlc_phy_rx_iq_coeffs_nphy(pi, 0, &save_comp);
26892 wlc_phy_rx_iq_coeffs_nphy(pi, 1, &zero_comp);
26894 if (CHSPEC_IS5G(pi->radio_chanspec)) {
26895 if (NREV_GE(pi->pubpi.phy_rev, 7))
26897 else if (NREV_GE(pi->pubpi.phy_rev, 4))
26901 if (NREV_GE(pi->pubpi.phy_rev, 7))
26906 if (NREV_GE(pi->pubpi.phy_rev, 7))
26914 hpvga = (NREV_GE(pi->pubpi.phy_rev, 7)) ?
26922 if (NREV_GE(pi->pubpi.phy_rev, 7))
26924 pi,
26931 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12),
26939 pi->nphy_rxcal_pwr_idx[tx_core] = txpwrindex;
26942 nphy_rxcal_txgain[0] = 0x8ff0 | pi->nphy_gmval;
26943 nphy_rxcal_txgain[1] = 0x8ff0 | pi->nphy_gmval;
26944 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
26948 wlc_phy_txpwr_index_nphy(pi, tx_core + 1, txpwrindex,
26952 wlc_phy_tx_tone_nphy(pi, (CHSPEC_IS40(pi->radio_chanspec)) ?
26957 wlc_phy_rx_iq_est_nphy(pi, est, num_samps, 32, 0);
27010 wlc_phy_stopplayback_nphy(pi);
27023 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
27032 pi,
27041 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12),
27059 wlc_phy_rx_iq_coeffs_nphy(pi, 1, &save_comp);
27063 wlc_phy_rxcal_gainctrl_nphy(struct brcms_phy *pi, u8 rx_core, u16 *rxgain,
27066 wlc_phy_rxcal_gainctrl_nphy_rev5(pi, rx_core, rxgain, cal_type);
27070 wlc_phy_rc_sweep_nphy(struct brcms_phy *pi, u8 core_idx, u8 loopback_type)
27104 if (NREV_GE(pi->pubpi.phy_rev, 7))
27109 if (CHSPEC_IS40(pi->radio_chanspec)) {
27132 read_radio_reg(pi,
27136 read_radio_reg(pi,
27140 orig_dcBypass = ((read_phy_reg(pi, 0x48) >> 8) & 1);
27142 orig_RxStrnFilt40Num[0] = read_phy_reg(pi, 0x267);
27143 orig_RxStrnFilt40Num[1] = read_phy_reg(pi, 0x268);
27144 orig_RxStrnFilt40Num[2] = read_phy_reg(pi, 0x269);
27145 orig_RxStrnFilt40Den[0] = read_phy_reg(pi, 0x26a);
27146 orig_RxStrnFilt40Den[1] = read_phy_reg(pi, 0x26b);
27147 orig_RxStrnFilt40Num[3] = read_phy_reg(pi, 0x26c);
27148 orig_RxStrnFilt40Num[4] = read_phy_reg(pi, 0x26d);
27149 orig_RxStrnFilt40Num[5] = read_phy_reg(pi, 0x26e);
27150 orig_RxStrnFilt40Den[2] = read_phy_reg(pi, 0x26f);
27151 orig_RxStrnFilt40Den[3] = read_phy_reg(pi, 0x270);
27153 orig_rfctrloverride[0] = read_phy_reg(pi, 0xe7);
27154 orig_rfctrloverride[1] = read_phy_reg(pi, 0xec);
27155 orig_rfctrlauxreg[0] = read_phy_reg(pi, 0xf8);
27156 orig_rfctrlauxreg[1] = read_phy_reg(pi, 0xfa);
27157 orig_rfctrlrssiothers = read_phy_reg(pi, (core_idx == 0) ? 0x7a : 0x7d);
27159 write_radio_reg(pi, (RADIO_2056_TX_TXLPF_RCCAL | radio_addr_offset_tx),
27162 write_radio_reg(pi,
27166 mod_phy_reg(pi, 0x48, (0x1 << 8), (0x1 << 8));
27168 write_phy_reg(pi, 0x267, 0x02d4);
27169 write_phy_reg(pi, 0x268, 0x0000);
27170 write_phy_reg(pi, 0x269, 0x0000);
27171 write_phy_reg(pi, 0x26a, 0x0000);
27172 write_phy_reg(pi, 0x26b, 0x0000);
27173 write_phy_reg(pi, 0x26c, 0x02d4);
27174 write_phy_reg(pi, 0x26d, 0x0000);
27175 write_phy_reg(pi, 0x26e, 0x0000);
27176 write_phy_reg(pi, 0x26f, 0x0000);
27177 write_phy_reg(pi, 0x270, 0x0000);
27179 or_phy_reg(pi, (core_idx == 0) ? 0xe7 : 0xec, (0x1 << 8));
27180 or_phy_reg(pi, (core_idx == 0) ? 0xec : 0xe7, (0x1 << 15));
27181 or_phy_reg(pi, (core_idx == 0) ? 0xe7 : 0xec, (0x1 << 9));
27182 or_phy_reg(pi, (core_idx == 0) ? 0xe7 : 0xec, (0x1 << 10));
27184 mod_phy_reg(pi, (core_idx == 0) ? 0xfa : 0xf8,
27186 mod_phy_reg(pi, (core_idx == 0) ? 0xf8 : 0xfa,
27188 mod_phy_reg(pi, (core_idx == 0) ? 0xf8 : 0xfa,
27190 mod_phy_reg(pi, (core_idx == 0) ? 0x7a : 0x7d,
27197 write_radio_reg(pi,
27203 wlc_phy_tx_tone_nphy(pi, ref_tone, NPHY_RXCAL_TONEAMP,
27207 wlc_phy_rx_iq_est_nphy(pi, est, num_samps, 32, 0);
27222 wlc_phy_tx_tone_nphy(pi, target_bw, NPHY_RXCAL_TONEAMP,
27227 wlc_phy_rx_iq_est_nphy(pi, est, num_samps, 32, 0);
27260 if (CHSPEC_IS40(pi->radio_chanspec)) {
27270 write_radio_reg(pi,
27276 wlc_phy_stopplayback_nphy(pi);
27278 write_radio_reg(pi, (RADIO_2056_TX_TXLPF_RCCAL | radio_addr_offset_tx),
27280 write_radio_reg(pi,
27284 mod_phy_reg(pi, 0x48, (0x1 << 8), (orig_dcBypass << 8));
27286 write_phy_reg(pi, 0x267, orig_RxStrnFilt40Num[0]);
27287 write_phy_reg(pi, 0x268, orig_RxStrnFilt40Num[1]);
27288 write_phy_reg(pi, 0x269, orig_RxStrnFilt40Num[2]);
27289 write_phy_reg(pi, 0x26a, orig_RxStrnFilt40Den[0]);
27290 write_phy_reg(pi, 0x26b, orig_RxStrnFilt40Den[1]);
27291 write_phy_reg(pi, 0x26c, orig_RxStrnFilt40Num[3]);
27292 write_phy_reg(pi, 0x26d, orig_RxStrnFilt40Num[4]);
27293 write_phy_reg(pi, 0x26e, orig_RxStrnFilt40Num[5]);
27294 write_phy_reg(pi, 0x26f, orig_RxStrnFilt40Den[2]);
27295 write_phy_reg(pi, 0x270, orig_RxStrnFilt40Den[3]);
27297 write_phy_reg(pi, 0xe7, orig_rfctrloverride[0]);
27298 write_phy_reg(pi, 0xec, orig_rfctrloverride[1]);
27299 write_phy_reg(pi, 0xf8, orig_rfctrlauxreg[0]);
27300 write_phy_reg(pi, 0xfa, orig_rfctrlauxreg[1]);
27301 write_phy_reg(pi, (core_idx == 0) ? 0x7a : 0x7d, orig_rfctrlrssiothers);
27303 pi->nphy_anarxlpf_adjusted = false;
27309 static int wlc_phy_cal_rxiq_nphy_rev3(struct brcms_phy *pi,
27325 orig_BBConfig = read_phy_reg(pi, 0x01);
27326 mod_phy_reg(pi, 0x01, (0x1 << 15), 0);
27328 wlc_phy_stay_in_carriersearch_nphy(pi, true);
27330 if (NREV_GE(pi->pubpi.phy_rev, 4)) {
27331 phyhang_avoid_state = pi->phyhang_avoid;
27332 pi->phyhang_avoid = false;
27335 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, gain_save);
27338 wlc_phy_iqcal_gainparams_nphy(pi, core_no, target_gain,
27343 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, cal_gain);
27346 (struct brcms_phy_pub *) pi);
27348 for (rx_core = 0; rx_core < pi->pubpi.phy_corenum; rx_core++) {
27353 wlc_phy_rxcal_physetup_nphy(pi, rx_core);
27355 wlc_phy_rxcal_radio_setup_nphy(pi, rx_core);
27359 wlc_phy_rxcal_gainctrl_nphy(pi, rx_core, NULL, 0);
27361 wlc_phy_tx_tone_nphy(pi,
27363 pi->radio_chanspec)) ?
27372 wlc_phy_calc_rx_iq_comp_nphy(pi, rx_core + 1);
27373 wlc_phy_stopplayback_nphy(pi);
27377 && NREV_LT(pi->pubpi.phy_rev, 7)) {
27383 (struct brcms_phy_pub *) pi, 3);
27385 wlc_phy_rxcal_gainctrl_nphy(pi, rx_core, NULL,
27389 wlc_phy_rc_sweep_nphy(pi, rx_core, 1);
27390 pi->nphy_rccal_value = best_rccal[rx_core];
27394 (struct brcms_phy_pub *) pi,
27399 wlc_phy_rxcal_radio_cleanup_nphy(pi, rx_core);
27401 wlc_phy_rxcal_phycleanup_nphy(pi, rx_core);
27402 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
27408 write_radio_reg(pi,
27412 for (rx_core = 0; rx_core < pi->pubpi.phy_corenum; rx_core++) {
27417 if (PHY_IPA(pi)) {
27419 (pi->bw == WL_CHANSPEC_BW_40) ? 24 : 12;
27420 txlpf_idac = (pi->bw == WL_CHANSPEC_BW_40) ?
27422 WRITE_RADIO_REG2(pi, RADIO_2056, TX, rx_core,
27431 write_radio_reg(pi, (RADIO_2056_RX_RXLPF_RCCAL_HPC |
27437 write_radio_reg(pi, (RADIO_2056_TX_TXLPF_RCCAL |
27445 write_phy_reg(pi, 0x01, orig_BBConfig);
27447 wlc_phy_resetcca_nphy(pi);
27449 if (NREV_GE(pi->pubpi.phy_rev, 7))
27451 pi,
27455 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12), 0, 0x3, 1);
27457 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
27459 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
27462 if (NREV_GE(pi->pubpi.phy_rev, 4))
27463 pi->phyhang_avoid = phyhang_avoid_state;
27465 wlc_phy_stay_in_carriersearch_nphy(pi, false);
27471 wlc_phy_cal_rxiq_nphy_rev2(struct brcms_phy *pi,
27495 wlc_phy_stay_in_carriersearch_nphy(pi, true);
27497 if (NREV_LT(pi->pubpi.phy_rev, 2))
27498 wlc_phy_reapply_txcal_coeffs_nphy(pi);
27500 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, gain_save);
27503 wlc_phy_iqcal_gainparams_nphy(pi, core_no, target_gain,
27508 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, cal_gain);
27518 orig_RfseqCoreActv = read_phy_reg(pi, 0xa2);
27519 orig_AfectrlCore = read_phy_reg(pi, (rx_core == PHY_CORE_0) ?
27521 orig_AfectrlOverride = read_phy_reg(pi, 0xa5);
27522 orig_RfctrlIntcRx = read_phy_reg(pi, (rx_core == PHY_CORE_0) ?
27524 orig_RfctrlIntcTx = read_phy_reg(pi, (tx_core == PHY_CORE_0) ?
27527 mod_phy_reg(pi, 0xa2, (0xf << 12), (1 << tx_core) << 12);
27528 mod_phy_reg(pi, 0xa2, (0xf << 0), (1 << tx_core) << 0);
27530 or_phy_reg(pi, ((rx_core == PHY_CORE_0) ? 0xa6 : 0xa7),
27532 or_phy_reg(pi, 0xa5, ((0x1 << 1) | (0x1 << 2)));
27534 if (((pi->nphy_rxcalparams) & 0xff000000))
27535 write_phy_reg(pi,
27537 (CHSPEC_IS5G(pi->radio_chanspec) ?
27540 write_phy_reg(pi,
27542 (CHSPEC_IS5G(pi->radio_chanspec) ?
27545 write_phy_reg(pi, (tx_core == PHY_CORE_0) ? 0x91 : 0x92,
27546 (CHSPEC_IS5G(pi->radio_chanspec) ? 0x148 :
27558 if ((pi->nphy_rxcalparams & 0x10000)) {
27559 mod_radio_reg(pi, RADIO_2055_CORE1_GEN_SPARE2, mask,
27561 mod_radio_reg(pi, RADIO_2055_CORE2_GEN_SPARE2, mask,
27615 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 10),
27619 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
27621 wlc_phy_stopplayback_nphy(pi);
27624 bcmerror = wlc_phy_tx_tone_nphy(pi, 4000,
27625 (u16) (pi->nphy_rxcalparams &
27629 phy_bw = (CHSPEC_IS40(pi->radio_chanspec)) ?
27631 wlc_phy_runsamples_nphy(pi, phy_bw * 8, 0xffff,
27638 wlc_phy_rx_iq_est_nphy(pi, est,
27648 wlc_phy_calc_rx_iq_comp_nphy(pi,
27653 wlc_phy_stopplayback_nphy(pi);
27660 and_radio_reg(pi, RADIO_2055_CORE1_GEN_SPARE2, ~mask);
27661 and_radio_reg(pi, RADIO_2055_CORE2_GEN_SPARE2, ~mask);
27663 write_phy_reg(pi, (tx_core == PHY_CORE_0) ? 0x91 :
27665 write_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0x91 :
27667 write_phy_reg(pi, 0xa5, orig_AfectrlOverride);
27668 write_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0xa6 :
27670 write_phy_reg(pi, 0xa2, orig_RfseqCoreActv);
27676 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 10), 0, 0x3, 1);
27677 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
27679 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
27682 wlc_phy_stay_in_carriersearch_nphy(pi, false);
27688 wlc_phy_cal_rxiq_nphy(struct brcms_phy *pi, struct nphy_txgains target_gain,
27691 if (NREV_GE(pi->pubpi.phy_rev, 7))
27694 if (NREV_GE(pi->pubpi.phy_rev, 3))
27695 return wlc_phy_cal_rxiq_nphy_rev3(pi, target_gain, cal_type,
27698 return wlc_phy_cal_rxiq_nphy_rev2(pi, target_gain, debug);
27701 void wlc_phy_txpwr_fixpower_nphy(struct brcms_phy *pi)
27709 if (pi->phyhang_avoid)
27710 wlc_phy_stay_in_carriersearch_nphy(pi, true);
27712 if (pi->sh->sromrev < 4) {
27716 chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0);
27731 if (NREV_GE(pi->pubpi.phy_rev, 7))
27733 else if (NREV_GE(pi->pubpi.phy_rev, 3))
27736 if (NREV_LT(pi->pubpi.phy_rev, 7)) {
27743 pi->nphy_txpwrindex[PHY_CORE_0].index_internal = txpi[0];
27744 pi->nphy_txpwrindex[PHY_CORE_1].index_internal = txpi[1];
27745 pi->nphy_txpwrindex[PHY_CORE_0].index_internal_save = txpi[0];
27746 pi->nphy_txpwrindex[PHY_CORE_1].index_internal_save = txpi[1];
27748 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
27749 uint phyrev = pi->pubpi.phy_rev;
27752 if (PHY_IPA(pi)) {
27754 wlc_phy_get_ipa_gaintbl_nphy(pi);
27757 if (CHSPEC_IS5G(pi->radio_chanspec)) {
27764 pi->srom_fem5g.extpagain ==
27777 (pi->srom_fem2g.extpagain == 3)) {
27804 mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0x8f :
27807 mod_phy_reg(pi, 0xa5, (0x1 << 14), (0x1 << 14));
27809 write_phy_reg(pi, (core == PHY_CORE_0) ? 0xaa : 0xab, dac_gain);
27811 wlc_phy_table_write_nphy(pi, 7, 1, (0x110 + core), 16,
27814 wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m1m2);
27817 wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &m1m2);
27819 if (PHY_IPA(pi)) {
27820 wlc_phy_table_read_nphy(pi,
27828 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
27832 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
27838 and_phy_reg(pi, 0xbf, (u16) (~(0x1f << 0)));
27840 if (pi->phyhang_avoid)
27841 wlc_phy_stay_in_carriersearch_nphy(pi, false);
27900 void wlc_phy_txpwr_apply_nphy(struct brcms_phy *pi)
27913 tmp_max_pwr = min(pi->nphy_pwrctrl_info[0].max_pwr_2g,
27914 pi->nphy_pwrctrl_info[1].max_pwr_2g);
27916 pwr_offsets1[0] = pi->cck2gpo;
27917 wlc_phy_txpwr_nphy_srom_convert(pi->tx_srom_max_rate_2g,
27923 pwr_offsets1[0] = (u16) (pi->ofdm2gpo & 0xffff);
27925 (u16) (pi->ofdm2gpo >> 16) & 0xffff;
27927 pwr_offsets2 = pi->mcs2gpo;
27929 tmp_cddpo = pi->cdd2gpo;
27930 tmp_stbcpo = pi->stbc2gpo;
27931 tmp_bw40po = pi->bw402gpo;
27933 tx_srom_max_rate = pi->tx_srom_max_rate_2g;
27937 tmp_max_pwr = min(pi->nphy_pwrctrl_info[0].max_pwr_5gm,
27938 pi->nphy_pwrctrl_info[1].max_pwr_5gm);
27940 pwr_offsets1[0] = (u16) (pi->ofdm5gpo & 0xffff);
27942 (u16) (pi->ofdm5gpo >> 16) & 0xffff;
27944 pwr_offsets2 = pi->mcs5gpo;
27946 tmp_cddpo = pi->cdd5gpo;
27947 tmp_stbcpo = pi->stbc5gpo;
27948 tmp_bw40po = pi->bw405gpo;
27950 tx_srom_max_rate = pi->tx_srom_max_rate_5g_mid;
27954 tmp_max_pwr = min(pi->nphy_pwrctrl_info[0].max_pwr_5gl,
27955 pi->nphy_pwrctrl_info[1].max_pwr_5gl);
27957 pwr_offsets1[0] = (u16) (pi->ofdm5glpo & 0xffff);
27959 (u16) (pi->ofdm5glpo >> 16) & 0xffff;
27961 pwr_offsets2 = pi->mcs5glpo;
27963 tmp_cddpo = pi->cdd5glpo;
27964 tmp_stbcpo = pi->stbc5glpo;
27965 tmp_bw40po = pi->bw405glpo;
27967 tx_srom_max_rate = pi->tx_srom_max_rate_5g_low;
27971 tmp_max_pwr = min(pi->nphy_pwrctrl_info[0].max_pwr_5gh,
27972 pi->nphy_pwrctrl_info[1].max_pwr_5gh);
27974 pwr_offsets1[0] = (u16) (pi->ofdm5ghpo & 0xffff);
27976 (u16) (pi->ofdm5ghpo >> 16) & 0xffff;
27978 pwr_offsets2 = pi->mcs5ghpo;
27980 tmp_cddpo = pi->cdd5ghpo;
27981 tmp_stbcpo = pi->stbc5ghpo;
27982 tmp_bw40po = pi->bw405ghpo;
27984 tx_srom_max_rate = pi->tx_srom_max_rate_5g_hi;
28002 if (NREV_GE(pi->pubpi.phy_rev, 3))
28017 if (NREV_GE(pi->pubpi.phy_rev, 3))
28082 if (NREV_GE(pi->pubpi.phy_rev, 3))
28095 void wlc_phy_txpower_recalc_target_nphy(struct brcms_phy *pi)
28098 wlc_phy_txpwr_limit_to_tbl_nphy(pi);
28099 wlc_phy_txpwrctrl_pwr_setup_nphy(pi);
28101 tx_pwr_ctrl_state = pi->nphy_txpwrctrl;
28103 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
28104 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
28105 (void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
28109 wlc_phy_txpwrctrl_enable_nphy(pi, tx_pwr_ctrl_state);
28111 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12))
28112 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, 0);
28115 static bool wlc_phy_txpwr_ison_nphy(struct brcms_phy *pi)
28117 return read_phy_reg((pi), 0x1e7) & ((0x1 << 15) |
28121 u16 wlc_phy_txpwr_idx_get_nphy(struct brcms_phy *pi)
28126 if (wlc_phy_txpwr_ison_nphy(pi)) {
28127 pwr_idx[0] = wlc_phy_txpwr_idx_cur_get_nphy(pi, PHY_CORE_0);
28128 pwr_idx[1] = wlc_phy_txpwr_idx_cur_get_nphy(pi, PHY_CORE_1);
28132 tmp = ((pi->nphy_txpwrindex[PHY_CORE_0].index_internal & 0xff)
28134 (pi->nphy_txpwrindex[PHY_CORE_1].index_internal & 0xff);
28140 void wlc_phy_txpwr_papd_cal_nphy(struct brcms_phy *pi)
28142 if (PHY_IPA(pi)
28143 && (pi->nphy_force_papd_cal
28144 || (wlc_phy_txpwr_ison_nphy(pi)
28147 abs(wlc_phy_txpwr_idx_cur_get_nphy(pi, 0) -
28148 pi->nphy_papd_tx_gain_at_last_cal[0]) >= 4)
28150 abs(wlc_phy_txpwr_idx_cur_get_nphy(pi, 1) -
28151 pi->nphy_papd_tx_gain_at_last_cal[1]) >= 4)))))
28152 wlc_phy_a4(pi, true);
28155 void wlc_phy_txpwrctrl_enable_nphy(struct brcms_phy *pi, u8 ctrl_type)
28164 if (pi->phyhang_avoid)
28165 wlc_phy_stay_in_carriersearch_nphy(pi, true);
28170 pi->nphy_txpwrctrl = ctrl_type;
28177 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
28179 if (wlc_phy_txpwr_ison_nphy(pi)) {
28180 for (core = 0; core < pi->pubpi.phy_corenum;
28182 pi->nphy_txpwr_idx[core] =
28184 pi,
28194 wlc_phy_table_write_nphy(pi, 26, tbl_len, tbl_offset, 16,
28196 wlc_phy_table_write_nphy(pi, 27, tbl_len, tbl_offset, 16,
28199 if (NREV_GE(pi->pubpi.phy_rev, 3))
28200 and_phy_reg(pi, 0x1e7,
28205 and_phy_reg(pi, 0x1e7,
28208 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
28209 or_phy_reg(pi, 0x8f, (0x1 << 8));
28210 or_phy_reg(pi, 0xa5, (0x1 << 8));
28212 or_phy_reg(pi, 0xa5, (0x1 << 14));
28215 if (NREV_IS(pi->pubpi.phy_rev, 2))
28216 mod_phy_reg(pi, 0xdc, 0x00ff, 0x53);
28217 else if (NREV_LT(pi->pubpi.phy_rev, 2))
28218 mod_phy_reg(pi, 0xdc, 0x00ff, 0x5a);
28220 if (NREV_LT(pi->pubpi.phy_rev, 2) &&
28221 pi->bw == WL_CHANSPEC_BW_40)
28222 wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_IQSWAP_WAR,
28227 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 84, 64,
28228 8, pi->adj_pwr_tbl_nphy);
28229 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 84, 64,
28230 8, pi->adj_pwr_tbl_nphy);
28236 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
28241 mod_phy_reg(pi, 0x1e7, mask, val);
28243 if (CHSPEC_IS5G(pi->radio_chanspec)) {
28244 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
28245 mod_phy_reg(pi, 0x1e7, (0x7f << 0), 0x32);
28246 mod_phy_reg(pi, 0x222, (0xff << 0), 0x32);
28248 mod_phy_reg(pi, 0x1e7, (0x7f << 0), 0x64);
28249 if (NREV_GT(pi->pubpi.phy_rev, 1))
28250 mod_phy_reg(pi, 0x222,
28255 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
28256 if ((pi->nphy_txpwr_idx[0] != 128)
28257 && (pi->nphy_txpwr_idx[1] != 128))
28258 wlc_phy_txpwr_idx_cur_set_nphy(pi,
28259 pi->
28262 pi->
28267 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
28268 and_phy_reg(pi, 0x8f, ~(0x1 << 8));
28269 and_phy_reg(pi, 0xa5, ~(0x1 << 8));
28271 and_phy_reg(pi, 0xa5, ~(0x1 << 14));
28274 if (NREV_IS(pi->pubpi.phy_rev, 2))
28275 mod_phy_reg(pi, 0xdc, 0x00ff, 0x3b);
28276 else if (NREV_LT(pi->pubpi.phy_rev, 2))
28277 mod_phy_reg(pi, 0xdc, 0x00ff, 0x40);
28279 if (NREV_LT(pi->pubpi.phy_rev, 2) &&
28280 pi->bw == WL_CHANSPEC_BW_40)
28281 wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_IQSWAP_WAR,
28284 if (PHY_IPA(pi)) {
28285 mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x297 :
28288 mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x297 :
28295 if (pi->phyhang_avoid)
28296 wlc_phy_stay_in_carriersearch_nphy(pi, false);
28300 wlc_phy_txpwr_index_nphy(struct brcms_phy *pi, u8 core_mask, s8 txpwrindex,
28317 if (pi->phyhang_avoid)
28318 wlc_phy_stay_in_carriersearch_nphy(pi, true);
28324 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
28332 if (pi->nphy_txpwrindex[core].index < 0)
28335 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
28336 mod_phy_reg(pi, 0x8f,
28338 pi->nphy_txpwrindex[core].
28340 mod_phy_reg(pi, 0xa5, (0x1 << 8),
28341 pi->nphy_txpwrindex[core].
28344 mod_phy_reg(pi, 0xa5,
28346 pi->nphy_txpwrindex[core].
28350 write_phy_reg(pi, (core == PHY_CORE_0) ?
28352 pi->nphy_txpwrindex[core].AfeCtrlDacGain);
28354 wlc_phy_table_write_nphy(pi, 7, 1, (0x110 + core), 16,
28355 &pi->nphy_txpwrindex[core].
28358 wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m1m2);
28361 (pi->nphy_txpwrindex[core].bbmult << 8) :
28362 (pi->nphy_txpwrindex[core].bbmult << 0));
28363 wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &m1m2);
28367 pi, 15, 2, (80 + 2 * core), 16,
28368 &pi->nphy_txpwrindex[core].iqcomp_a);
28370 pi, 15, 1, (85 + core), 16,
28371 &pi->nphy_txpwrindex[core].locomp);
28373 pi, 15, 1, (93 + core), 16,
28374 &pi->nphy_txpwrindex[core].locomp);
28377 wlc_phy_txpwrctrl_enable_nphy(pi, pi->nphy_txpwrctrl);
28379 pi->nphy_txpwrindex[core].index_internal =
28380 pi->nphy_txpwrindex[core].index_internal_save;
28383 if (pi->nphy_txpwrindex[core].index < 0) {
28385 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
28386 mod_phy_reg(pi, 0x8f,
28388 pi->nphy_txpwrindex[core].
28390 mod_phy_reg(pi, 0xa5, (0x1 << 8),
28391 pi->nphy_txpwrindex[core].
28394 pi->nphy_txpwrindex[core].
28396 read_phy_reg(pi, 0xa5);
28399 pi->nphy_txpwrindex[core].AfeCtrlDacGain =
28400 read_phy_reg(pi, (core == PHY_CORE_0) ?
28403 wlc_phy_table_read_nphy(pi, 7, 1,
28405 &pi->
28409 wlc_phy_table_read_nphy(pi, 15, 1, 87, 16,
28413 pi->nphy_txpwrindex[core].bbmult = (u8) tmpval;
28415 wlc_phy_table_read_nphy(pi, 15, 2,
28417 &pi->
28421 wlc_phy_table_read_nphy(pi, 15, 1, (85 + core),
28423 &pi->
28427 pi->nphy_txpwrindex[core].index_internal_save =
28428 pi->nphy_txpwrindex[core].
28432 tx_pwr_ctrl_state = pi->nphy_txpwrctrl;
28433 wlc_phy_txpwrctrl_enable_nphy(pi, PHY_TPC_HW_OFF);
28435 if (NREV_IS(pi->pubpi.phy_rev, 1))
28436 wlapi_bmac_phyclk_fgc(pi->sh->physhim, ON);
28438 wlc_phy_table_read_nphy(pi, txpwrctl_tbl, 1,
28442 if (NREV_GE(pi->pubpi.phy_rev, 3))
28452 if (NREV_GE(pi->pubpi.phy_rev, 3))
28453 mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0x8f :
28456 mod_phy_reg(pi, 0xa5, (0x1 << 14), (0x1 << 14));
28458 write_phy_reg(pi, (core == PHY_CORE_0) ?
28461 wlc_phy_table_write_nphy(pi, 7, 1, (0x110 + core), 16,
28464 wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m1m2);
28469 wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &m1m2);
28471 wlc_phy_table_read_nphy(pi, txpwrctl_tbl, 1,
28480 wlc_phy_table_write_nphy(pi, 15, 2,
28485 wlc_phy_table_read_nphy(pi, txpwrctl_tbl, 1,
28489 wlc_phy_table_write_nphy(pi, 15, 1, (85 + core),
28492 if (NREV_IS(pi->pubpi.phy_rev, 1))
28493 wlapi_bmac_phyclk_fgc(pi->sh->physhim, OFF);
28495 if (PHY_IPA(pi)) {
28496 wlc_phy_table_read_nphy(pi,
28503 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
28507 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
28512 wlc_phy_txpwrctrl_enable_nphy(pi, tx_pwr_ctrl_state);
28515 pi->nphy_txpwrindex[core].index = txpwrindex;
28518 if (pi->phyhang_avoid)
28519 wlc_phy_stay_in_carriersearch_nphy(pi, false);
28523 wlc_phy_txpower_sromlimit_get_nphy(struct brcms_phy *pi, uint chan, u8 *max_pwr,
28528 chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, chan);
28531 *max_pwr = pi->tx_srom_max_rate_2g[txp_rate_idx];
28534 *max_pwr = pi->tx_srom_max_rate_5g_mid[txp_rate_idx];
28537 *max_pwr = pi->tx_srom_max_rate_5g_low[txp_rate_idx];
28540 *max_pwr = pi->tx_srom_max_rate_5g_hi[txp_rate_idx];
28543 *max_pwr = pi->tx_srom_max_rate_2g[txp_rate_idx];
28550 void wlc_phy_stay_in_carriersearch_nphy(struct brcms_phy *pi, bool enable)
28555 if (pi->nphy_deaf_count == 0) {
28556 pi->classifier_state =
28557 wlc_phy_classifier_nphy(pi, 0, 0);
28558 wlc_phy_classifier_nphy(pi, (0x7 << 0), 4);
28559 wlc_phy_clip_det_nphy(pi, 0, pi->clip_state);
28560 wlc_phy_clip_det_nphy(pi, 1, clip_off);
28563 pi->nphy_deaf_count++;
28565 wlc_phy_resetcca_nphy(pi);
28568 pi->nphy_deaf_count--;
28570 if (pi->nphy_deaf_count == 0) {
28571 wlc_phy_classifier_nphy(pi, (0x7 << 0),
28572 pi->classifier_state);
28573 wlc_phy_clip_det_nphy(pi, 1, pi->clip_state);
28578 void wlc_nphy_deaf_mode(struct brcms_phy *pi, bool mode)
28580 wlapi_suspend_mac_and_wait(pi->sh->physhim);
28583 if (pi->nphy_deaf_count == 0)
28584 wlc_phy_stay_in_carriersearch_nphy(pi, true);
28585 } else if (pi->nphy_deaf_count > 0) {
28586 wlc_phy_stay_in_carriersearch_nphy(pi, false);
28589 wlapi_enable_mac(pi->sh->physhim);