Lines Matching refs:pi
26 #define VALID_RADIO(pi, radioid) ( \
27 (ISNPHY(pi) ? VALID_N_RADIO(radioid) : false) || \
28 (ISLCNPHY(pi) ? VALID_LCN_RADIO(radioid) : false))
120 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
121 wlapi_bmac_ucode_wake_override_phyreg_set(pi->sh->physhim);
126 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
127 wlapi_bmac_ucode_wake_override_phyreg_clear(pi->sh->physhim);
132 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
133 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, MCTL_LOCK_RADIO);
140 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
142 (void)bcma_read16(pi->d11core, D11REGOFFS(phyversion));
143 pi->phy_wreg = 0;
144 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, 0);
147 u16 read_radio_reg(struct brcms_phy *pi, u16 addr)
154 switch (pi->pubpi.phy_type) {
158 if (NREV_GE(pi->pubpi.phy_rev, 7))
174 if ((D11REV_GE(pi->sh->corerev, 24)) ||
175 (D11REV_IS(pi->sh->corerev, 22)
176 && (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
177 bcma_wflush16(pi->d11core, D11REGOFFS(radioregaddr), addr);
178 data = bcma_read16(pi->d11core, D11REGOFFS(radioregdata));
180 bcma_wflush16(pi->d11core, D11REGOFFS(phy4waddr), addr);
181 data = bcma_read16(pi->d11core, D11REGOFFS(phy4wdatalo));
183 pi->phy_wreg = 0;
188 void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val)
190 if ((D11REV_GE(pi->sh->corerev, 24)) ||
191 (D11REV_IS(pi->sh->corerev, 22)
192 && (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
194 bcma_wflush16(pi->d11core, D11REGOFFS(radioregaddr), addr);
195 bcma_write16(pi->d11core, D11REGOFFS(radioregdata), val);
197 bcma_wflush16(pi->d11core, D11REGOFFS(phy4waddr), addr);
198 bcma_write16(pi->d11core, D11REGOFFS(phy4wdatalo), val);
201 if ((pi->d11core->bus->hosttype == BCMA_HOSTTYPE_PCI) &&
202 (++pi->phy_wreg >= pi->phy_wreg_limit)) {
203 (void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
204 pi->phy_wreg = 0;
208 static u32 read_radio_id(struct brcms_phy *pi)
212 if (D11REV_GE(pi->sh->corerev, 24)) {
215 bcma_wflush16(pi->d11core, D11REGOFFS(radioregaddr), 0);
216 b0 = (u32) bcma_read16(pi->d11core, D11REGOFFS(radioregdata));
217 bcma_wflush16(pi->d11core, D11REGOFFS(radioregaddr), 1);
218 b1 = (u32) bcma_read16(pi->d11core, D11REGOFFS(radioregdata));
219 bcma_wflush16(pi->d11core, D11REGOFFS(radioregaddr), 2);
220 b2 = (u32) bcma_read16(pi->d11core, D11REGOFFS(radioregdata));
225 bcma_wflush16(pi->d11core, D11REGOFFS(phy4waddr), RADIO_IDCODE);
226 id = (u32) bcma_read16(pi->d11core, D11REGOFFS(phy4wdatalo));
227 id |= (u32) bcma_read16(pi->d11core,
230 pi->phy_wreg = 0;
234 void and_radio_reg(struct brcms_phy *pi, u16 addr, u16 val)
238 rval = read_radio_reg(pi, addr);
239 write_radio_reg(pi, addr, (rval & val));
242 void or_radio_reg(struct brcms_phy *pi, u16 addr, u16 val)
246 rval = read_radio_reg(pi, addr);
247 write_radio_reg(pi, addr, (rval | val));
250 void xor_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask)
254 rval = read_radio_reg(pi, addr);
255 write_radio_reg(pi, addr, (rval ^ mask));
258 void mod_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val)
262 rval = read_radio_reg(pi, addr);
263 write_radio_reg(pi, addr, (rval & ~mask) | (val & mask));
266 void write_phy_channel_reg(struct brcms_phy *pi, uint val)
268 bcma_write16(pi->d11core, D11REGOFFS(phychannel), val);
271 u16 read_phy_reg(struct brcms_phy *pi, u16 addr)
273 bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr), addr);
275 pi->phy_wreg = 0;
276 return bcma_read16(pi->d11core, D11REGOFFS(phyregdata));
279 void write_phy_reg(struct brcms_phy *pi, u16 addr, u16 val)
282 bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr), addr);
283 bcma_write16(pi->d11core, D11REGOFFS(phyregdata), val);
285 (void)bcma_read16(pi->d11core, D11REGOFFS(phyregdata));
287 bcma_write32(pi->d11core, D11REGOFFS(phyregaddr), addr | (val << 16));
288 if ((pi->d11core->bus->hosttype == BCMA_HOSTTYPE_PCI) &&
289 (++pi->phy_wreg >= pi->phy_wreg_limit)) {
290 pi->phy_wreg = 0;
291 (void)bcma_read16(pi->d11core, D11REGOFFS(phyversion));
296 void and_phy_reg(struct brcms_phy *pi, u16 addr, u16 val)
298 bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr), addr);
299 bcma_mask16(pi->d11core, D11REGOFFS(phyregdata), val);
300 pi->phy_wreg = 0;
303 void or_phy_reg(struct brcms_phy *pi, u16 addr, u16 val)
305 bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr), addr);
306 bcma_set16(pi->d11core, D11REGOFFS(phyregdata), val);
307 pi->phy_wreg = 0;
310 void mod_phy_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val)
313 bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr), addr);
314 bcma_maskset16(pi->d11core, D11REGOFFS(phyregdata), ~mask, val);
315 pi->phy_wreg = 0;
318 static void wlc_set_phy_uninitted(struct brcms_phy *pi)
322 pi->initialized = false;
324 pi->tx_vos = 0xffff;
325 pi->nrssi_table_delta = 0x7fffffff;
326 pi->rc_cal = 0xffff;
327 pi->mintxbias = 0xffff;
328 pi->txpwridx = -1;
329 if (ISNPHY(pi)) {
330 pi->phy_spuravoid = SPURAVOID_DISABLE;
332 if (NREV_GE(pi->pubpi.phy_rev, 3)
333 && NREV_LT(pi->pubpi.phy_rev, 7))
334 pi->phy_spuravoid = SPURAVOID_AUTO;
336 pi->nphy_papd_skip = 0;
337 pi->nphy_papd_epsilon_offset[0] = 0xf588;
338 pi->nphy_papd_epsilon_offset[1] = 0xf588;
339 pi->nphy_txpwr_idx[0] = 128;
340 pi->nphy_txpwr_idx[1] = 128;
341 pi->nphy_txpwrindex[0].index_internal = 40;
342 pi->nphy_txpwrindex[1].index_internal = 40;
343 pi->phy_pabias = 0;
345 pi->phy_spuravoid = SPURAVOID_AUTO;
347 pi->radiopwr = 0xffff;
350 pi->stats_11b_txpower[i][j] = -1;
388 struct brcms_phy *pi = ptr;
391 if (PHY_PERICAL_MPHASE_PENDING(pi)) {
392 if (!pi->sh->up) {
393 wlc_phy_cal_perical_mphase_reset(pi);
397 if (SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)) {
400 wlc_phy_cal_perical_mphase_restart(pi);
402 wlc_phy_cal_perical_nphy_run(pi, PHY_PERICAL_AUTO);
403 wlapi_add_timer(pi->phycal_timer, delay, 0);
409 static u32 wlc_phy_get_radio_ver(struct brcms_phy *pi)
413 ver = read_radio_id(pi);
422 struct brcms_phy *pi;
438 pi = sh->phy_head;
439 if ((sflags & SISF_DB_PHY) && pi) {
440 wlapi_bmac_corereset(pi->sh->physhim, pi->pubpi.coreflags);
441 pi->refcnt++;
442 return &pi->pubpi_ro;
445 pi = kzalloc(sizeof(struct brcms_phy), GFP_ATOMIC);
446 if (pi == NULL)
448 pi->wiphy = wiphy;
449 pi->d11core = d11core;
450 pi->sh = sh;
451 pi->phy_init_por = true;
452 pi->phy_wreg_limit = PHY_WREG_LIMIT;
454 pi->txpwr_percent = 100;
456 pi->do_initcal = true;
458 pi->phycal_tempdelta = 0;
461 pi->pubpi.coreflags = SICF_GMODE;
463 wlapi_bmac_corereset(pi->sh->physhim, pi->pubpi.coreflags);
464 phyversion = bcma_read16(pi->d11core, D11REGOFFS(phyversion));
466 pi->pubpi.phy_type = PHY_TYPE(phyversion);
467 pi->pubpi.phy_rev = phyversion & PV_PV_MASK;
469 if (pi->pubpi.phy_type == PHY_TYPE_LCNXN) {
470 pi->pubpi.phy_type = PHY_TYPE_N;
471 pi->pubpi.phy_rev += LCNXN_BASEREV;
473 pi->pubpi.phy_corenum = PHY_CORE_NUM_2;
474 pi->pubpi.ana_rev = (phyversion & PV_AV_MASK) >> PV_AV_SHIFT;
476 if (pi->pubpi.phy_type != PHY_TYPE_N &&
477 pi->pubpi.phy_type != PHY_TYPE_LCN)
481 if (!ISNPHY(pi))
483 } else if (!ISNPHY(pi) && !ISLCNPHY(pi)) {
487 wlc_phy_anacore((struct brcms_phy_pub *) pi, ON);
489 idcode = wlc_phy_get_radio_ver(pi);
490 pi->pubpi.radioid =
492 pi->pubpi.radiorev =
494 pi->pubpi.radiover =
496 if (!VALID_RADIO(pi, pi->pubpi.radioid))
499 wlc_phy_switch_radio((struct brcms_phy_pub *) pi, OFF);
501 wlc_set_phy_uninitted(pi);
503 pi->bw = WL_CHANSPEC_BW_20;
504 pi->radio_chanspec = (bandtype == BRCM_BAND_2G) ?
507 pi->rxiq_samps = PHY_NOISE_SAMPLE_LOG_NUM_NPHY;
508 pi->rxiq_antsel = ANT_RX_DIV_DEF;
510 pi->watchdog_override = true;
512 pi->cal_type_override = PHY_PERICAL_AUTO;
514 pi->nphy_saved_noisevars.bufcount = 0;
516 if (ISNPHY(pi))
517 pi->min_txpower = PHY_TXPWR_MIN_NPHY;
519 pi->min_txpower = PHY_TXPWR_MIN;
521 pi->sh->phyrxchain = 0x3;
523 pi->rx2tx_biasentry = -1;
525 pi->phy_txcore_disable_temp = PHY_CHAIN_TX_DISABLE_TEMP;
526 pi->phy_txcore_enable_temp =
528 pi->phy_tempsense_offset = 0;
529 pi->phy_txcore_heatedup = false;
531 pi->nphy_lastcal_temp = -50;
533 pi->phynoise_polling = true;
534 if (ISNPHY(pi) || ISLCNPHY(pi))
535 pi->phynoise_polling = false;
538 pi->txpwr_limit[i] = BRCMS_TXPWR_MAX;
539 pi->txpwr_env_limit[i] = BRCMS_TXPWR_MAX;
540 pi->tx_user_target[i] = BRCMS_TXPWR_MAX;
543 pi->radiopwr_override = RADIOPWR_OVERRIDE_DEF;
545 pi->user_txpwr_at_rfport = false;
547 if (ISNPHY(pi)) {
549 pi->phycal_timer = wlapi_init_timer(pi->sh->physhim,
551 pi, "phycal");
552 if (!pi->phycal_timer)
555 wlc_phy_attach_nphy(pi);
557 } else if (ISLCNPHY(pi)) {
558 if (!wlc_phy_attach_lcnphy(pi))
563 pi->refcnt++;
564 pi->next = pi->sh->phy_head;
565 sh->phy_head = pi;
567 memcpy(&pi->pubpi_ro, &pi->pubpi, sizeof(struct brcms_phy_pub));
569 return &pi->pubpi_ro;
572 kfree(pi);
578 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
581 if (--pi->refcnt)
584 if (pi->phycal_timer) {
585 wlapi_free_timer(pi->phycal_timer);
586 pi->phycal_timer = NULL;
589 if (pi->sh->phy_head == pi)
590 pi->sh->phy_head = pi->next;
591 else if (pi->sh->phy_head->next == pi)
592 pi->sh->phy_head->next = NULL;
594 if (pi->pi_fptr.detach)
595 (pi->pi_fptr.detach)(pi);
597 kfree(pi);
605 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
606 *phytype = (u16) pi->pubpi.phy_type;
607 *phyrev = (u16) pi->pubpi.phy_rev;
608 *radioid = pi->pubpi.radioid;
609 *radiover = pi->pubpi.radiorev;
616 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
617 return pi->pubpi.abgphy_encore;
622 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
623 return pi->pubpi.coreflags;
628 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
630 if (ISNPHY(pi)) {
632 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
633 write_phy_reg(pi, 0xa6, 0x0d);
634 write_phy_reg(pi, 0x8f, 0x0);
635 write_phy_reg(pi, 0xa7, 0x0d);
636 write_phy_reg(pi, 0xa5, 0x0);
638 write_phy_reg(pi, 0xa5, 0x0);
641 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
642 write_phy_reg(pi, 0x8f, 0x07ff);
643 write_phy_reg(pi, 0xa6, 0x0fd);
644 write_phy_reg(pi, 0xa5, 0x07ff);
645 write_phy_reg(pi, 0xa7, 0x0fd);
647 write_phy_reg(pi, 0xa5, 0x7fff);
650 } else if (ISLCNPHY(pi)) {
652 and_phy_reg(pi, 0x43b,
655 or_phy_reg(pi, 0x43c,
657 or_phy_reg(pi, 0x43b,
665 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
669 if (pi && (ISNPHY(pi) || ISLCNPHY(pi))) {
670 switch (pi->bw) {
690 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
692 pi->phy_init_por = true;
697 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
699 pi->edcrs_threshold_lock = lock;
701 write_phy_reg(pi, 0x22c, 0x46b);
702 write_phy_reg(pi, 0x22d, 0x46b);
703 write_phy_reg(pi, 0x22e, 0x3c0);
704 write_phy_reg(pi, 0x22f, 0x3c0);
709 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
711 pi->do_initcal = initcal;
716 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
718 if (!pi || !pi->sh)
721 pi->sh->clk = newstate;
726 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
728 if (!pi || !pi->sh)
731 pi->sh->up = newstate;
738 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
740 if (pi->init_in_progress)
743 pi->init_in_progress = true;
745 pi->radio_chanspec = chanspec;
747 mc = bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
751 if (!(pi->measure_hold & PHY_HOLD_FOR_SCAN))
752 pi->measure_hold |= PHY_HOLD_FOR_NOT_ASSOC;
754 if (WARN(!(bcma_aread32(pi->d11core, BCMA_IOST) & SISF_FCLKA),
758 phy_init = pi->pi_fptr.init;
765 if (CHSPEC_BW(pi->radio_chanspec) != pi->bw)
766 wlapi_bmac_bw_set(pi->sh->physhim,
767 CHSPEC_BW(pi->radio_chanspec));
769 pi->nphy_gain_boost = true;
771 wlc_phy_switch_radio((struct brcms_phy_pub *) pi, ON);
773 (*phy_init)(pi);
775 pi->phy_init_por = false;
777 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12))
778 wlc_phy_do_dummy_tx(pi, true, OFF);
780 if (!(ISNPHY(pi)))
781 wlc_phy_txpower_update_shm(pi);
783 wlc_phy_ant_rxdiv_set((struct brcms_phy_pub *) pi, pi->sh->rx_antdiv);
785 pi->init_in_progress = false;
790 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
793 if (WARN((bcma_read32(pi->d11core, D11REGOFFS(maccontrol)) &
797 if (!pi->initialized) {
798 cal_init = pi->pi_fptr.calinit;
800 (*cal_init)(pi);
802 pi->initialized = true;
808 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
811 if (pi->phycal_timer
812 && !wlapi_del_timer(pi->phycal_timer))
815 pi->nphy_iqcal_chanspec_2G = 0;
816 pi->nphy_iqcal_chanspec_5G = 0;
822 wlc_phy_table_addr(struct brcms_phy *pi, uint tbl_id, uint tbl_offset,
825 write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
827 pi->tbl_data_hi = tblDataHi;
828 pi->tbl_data_lo = tblDataLo;
830 if (pi->sh->chip == BCMA_CHIP_ID_BCM43224 &&
831 pi->sh->chiprev == 1) {
832 pi->tbl_addr = tblAddr;
833 pi->tbl_save_id = tbl_id;
834 pi->tbl_save_offset = tbl_offset;
838 void wlc_phy_table_data_write(struct brcms_phy *pi, uint width, u32 val)
840 if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224) &&
841 (pi->sh->chiprev == 1) &&
842 (pi->tbl_save_id == NPHY_TBL_ID_ANTSWCTRLLUT)) {
843 read_phy_reg(pi, pi->tbl_data_lo);
845 write_phy_reg(pi, pi->tbl_addr,
846 (pi->tbl_save_id << 10) | pi->tbl_save_offset);
847 pi->tbl_save_offset++;
851 write_phy_reg(pi, pi->tbl_data_hi, (u16) (val >> 16));
852 write_phy_reg(pi, pi->tbl_data_lo, (u16) val);
854 write_phy_reg(pi, pi->tbl_data_lo, (u16) val);
859 wlc_phy_write_table(struct brcms_phy *pi, const struct phytbl_info *ptbl_info,
870 write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
874 if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224) &&
875 (pi->sh->chiprev == 1) &&
877 read_phy_reg(pi, tblDataLo);
879 write_phy_reg(pi, tblAddr,
884 write_phy_reg(pi, tblDataHi,
886 write_phy_reg(pi, tblDataLo, (u16) ptbl_32b[idx]);
888 write_phy_reg(pi, tblDataLo, ptbl_16b[idx]);
890 write_phy_reg(pi, tblDataLo, ptbl_8b[idx]);
896 wlc_phy_read_table(struct brcms_phy *pi, const struct phytbl_info *ptbl_info,
907 write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
911 if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224) &&
912 (pi->sh->chiprev == 1)) {
913 (void)read_phy_reg(pi, tblDataLo);
915 write_phy_reg(pi, tblAddr,
920 ptbl_32b[idx] = read_phy_reg(pi, tblDataLo);
921 ptbl_32b[idx] |= (read_phy_reg(pi, tblDataHi) << 16);
923 ptbl_16b[idx] = read_phy_reg(pi, tblDataLo);
925 ptbl_8b[idx] = (u8) read_phy_reg(pi, tblDataLo);
931 wlc_phy_init_radio_regs_allbands(struct brcms_phy *pi,
938 write_radio_reg(pi, radioregs[i].address,
948 wlc_phy_init_radio_regs(struct brcms_phy *pi,
956 if (CHSPEC_IS5G(pi->radio_chanspec)) {
958 write_radio_reg(pi,
962 if (ISNPHY(pi) && (++count % 4 == 0))
963 BRCMS_PHY_WAR_PR51571(pi);
967 write_radio_reg(pi,
971 if (ISNPHY(pi) && (++count % 4 == 0))
972 BRCMS_PHY_WAR_PR51571(pi);
982 void wlc_phy_do_dummy_tx(struct brcms_phy *pi, bool ofdm, bool pa_on)
985 struct bcma_device *core = pi->d11core;
998 wlapi_bmac_write_template_ram(pi->sh->physhim, 0, DUMMY_PKT_LEN,
1003 if (D11REV_GE(pi->sh->corerev, 11))
1010 if (ISNPHY(pi) || ISLCNPHY(pi))
1025 if (ISNPHY(pi))
1026 wlc_phy_pa_override_nphy(pi, OFF);
1029 if (ISNPHY(pi) || ISLCNPHY(pi))
1055 if (ISNPHY(pi))
1056 wlc_phy_pa_override_nphy(pi, ON);
1062 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
1065 mboolset(pi->measure_hold, id);
1067 mboolclr(pi->measure_hold, id);
1074 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
1077 mboolset(pi->measure_hold, PHY_HOLD_FOR_MUTE);
1079 mboolclr(pi->measure_hold, PHY_HOLD_FOR_MUTE);
1082 pi->nphy_perical_last = pi->sh->now - pi->sh->glacial_timer;
1088 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
1090 if (ISNPHY(pi)) {
1093 wlapi_bmac_write_shm(pi->sh->physhim, M_B_TSSI_0, NULL_TSSI_W);
1094 wlapi_bmac_write_shm(pi->sh->physhim, M_B_TSSI_1, NULL_TSSI_W);
1095 wlapi_bmac_write_shm(pi->sh->physhim, M_G_TSSI_0, NULL_TSSI_W);
1096 wlapi_bmac_write_shm(pi->sh->physhim, M_G_TSSI_1, NULL_TSSI_W);
1100 static bool wlc_phy_cal_txpower_recalc_sw(struct brcms_phy *pi)
1107 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
1108 (void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
1110 if (ISNPHY(pi)) {
1111 wlc_phy_switch_radio_nphy(pi, on);
1112 } else if (ISLCNPHY(pi)) {
1114 and_phy_reg(pi, 0x44c,
1118 and_phy_reg(pi, 0x4b0, ~((0x1 << 3) | (0x1 << 11)));
1119 and_phy_reg(pi, 0x4f9, ~(0x1 << 3));
1121 and_phy_reg(pi, 0x44d,
1125 or_phy_reg(pi, 0x44c,
1130 and_phy_reg(pi, 0x4b7, ~((0x7f << 8)));
1131 and_phy_reg(pi, 0x4b1, ~((0x1 << 13)));
1132 or_phy_reg(pi, 0x4b0, (0x1 << 3) | (0x1 << 11));
1133 and_phy_reg(pi, 0x4fa, ~((0x1 << 3)));
1134 or_phy_reg(pi, 0x4f9, (0x1 << 3));
1141 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1143 return pi->bw;
1148 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1150 pi->bw = bw;
1155 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1156 pi->radio_chanspec = newch;
1162 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1164 return pi->radio_chanspec;
1169 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1177 wlapi_bmac_write_shm(pi->sh->physhim, M_CURCHANNEL, m_cur_channel);
1179 chanspec_set = pi->pi_fptr.chanset;
1181 (*chanspec_set)(pi, chanspec);
1201 int wlc_phy_chanspec_bandrange_get(struct brcms_phy *pi, u16 chanspec)
1207 if (ISNPHY(pi))
1208 range = wlc_phy_get_chan_freq_range_nphy(pi, channel);
1209 else if (ISLCNPHY(pi))
1218 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1220 pi->channel_14_wide_filter = wide_filter;
1238 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1247 if ((pi->a_band_high_disable) && (channel >= FIRST_REF5_CHANNUM)
1259 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1267 if (ISNPHY(pi) && pi->bw == WL_CHANSPEC_BW_40) {
1289 if ((pi->a_band_high_disable) && (channel >= FIRST_REF5_CHANNUM)
1303 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1305 *qdbm = pi->tx_user_target[0];
1307 *override = pi->txpwroverride;
1315 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1317 memcpy(&pi->tx_user_target[TXP_FIRST_CCK],
1320 memcpy(&pi->tx_user_target[TXP_FIRST_OFDM],
1322 memcpy(&pi->tx_user_target[TXP_FIRST_OFDM_20_CDD],
1325 memcpy(&pi->tx_user_target[TXP_FIRST_OFDM_40_SISO],
1327 memcpy(&pi->tx_user_target[TXP_FIRST_OFDM_40_CDD],
1330 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_SISO],
1332 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_CDD],
1334 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_STBC],
1336 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_SDM],
1339 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_SISO],
1341 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_CDD],
1343 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_STBC],
1345 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_SDM],
1348 if (bcma_read32(pi->d11core, D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
1352 wlapi_suspend_mac_and_wait(pi->sh->physhim);
1354 wlc_phy_txpower_recalc_target(pi);
1355 wlc_phy_cal_txpower_recalc_sw(pi);
1358 wlapi_enable_mac(pi->sh->physhim);
1363 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1370 pi->tx_user_target[i] = (u8) qdbm;
1372 pi->txpwroverride = false;
1374 if (pi->sh->up) {
1375 if (!SCAN_INPROG_PHY(pi)) {
1378 suspend = (0 == (bcma_read32(pi->d11core,
1383 wlapi_suspend_mac_and_wait(pi->sh->physhim);
1385 wlc_phy_txpower_recalc_target(pi);
1386 wlc_phy_cal_txpower_recalc_sw(pi);
1389 wlapi_enable_mac(pi->sh->physhim);
1399 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1402 *min_pwr = pi->min_txpower * BRCMS_TXPWR_DB_FACTOR;
1404 if (ISNPHY(pi)) {
1407 wlc_phy_txpower_sromlimit_get_nphy(pi, channel, max_pwr,
1413 *max_pwr = pi->tx_srom_max_rate_2g[txp_rate_idx];
1426 if (pi->hwtxpwr) {
1427 *max_pwr = pi->hwtxpwr[i];
1432 pi->tx_srom_max_rate_5g_mid[txp_rate_idx];
1436 pi->tx_srom_max_rate_5g_hi[txp_rate_idx];
1439 pi->tx_srom_max_rate_5g_low[txp_rate_idx];
1448 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1456 max_num_rate = ISNPHY(pi) ? TXP_NUM_RATES :
1457 ISLCNPHY(pi) ? (TXP_LAST_SISO_MCS_20 +
1485 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1487 return pi->tx_power_min;
1492 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1494 return pi->tx_power_max;
1497 static s8 wlc_phy_env_measure_vbat(struct brcms_phy *pi)
1499 if (ISLCNPHY(pi))
1500 return wlc_lcnphy_vbatsense(pi, 0);
1505 static s8 wlc_phy_env_measure_temperature(struct brcms_phy *pi)
1507 if (ISLCNPHY(pi))
1508 return wlc_lcnphy_tempsense_degree(pi, 0);
1513 static void wlc_phy_upd_env_txpwr_rate_limits(struct brcms_phy *pi, u32 band)
1518 pi->txpwr_env_limit[i] = BRCMS_TXPWR_MAX;
1520 wlc_phy_env_measure_vbat(pi);
1521 wlc_phy_env_measure_temperature(pi);
1525 wlc_user_txpwr_antport_to_rfport(struct brcms_phy *pi, uint chan, u32 band,
1531 void wlc_phy_txpower_recalc_target(struct brcms_phy *pi)
1542 u32 band = CHSPEC2BAND(pi->radio_chanspec);
1545 chspec = pi->radio_chanspec;
1554 if (ISLCNPHY(pi)) {
1557 if (CHSPEC_IS40(pi->radio_chanspec)) {
1558 offset_mcs = pi->mcs40_po;
1561 pi->tx_srom_max_rate_2g[i - 8] =
1562 pi->tx_srom_max_2g -
1567 offset_mcs = pi->mcs20_po;
1570 pi->tx_srom_max_rate_2g[i - 8] =
1571 pi->tx_srom_max_2g -
1578 max_num_rate = ((ISNPHY(pi)) ? (TXP_NUM_RATES) :
1579 ((ISLCNPHY(pi)) ?
1582 wlc_phy_upd_env_txpwr_rate_limits(pi, band);
1586 tx_pwr_target[rate] = pi->tx_user_target[rate];
1588 if (pi->user_txpwr_at_rfport)
1590 wlc_user_txpwr_antport_to_rfport(pi,
1595 wlc_phy_txpower_sromlimit((struct brcms_phy_pub *) pi,
1599 maxtxpwr = min(maxtxpwr, pi->txpwr_limit[rate]);
1607 if (pi->txpwr_percent <= 100)
1608 maxtxpwr = (maxtxpwr * pi->txpwr_percent) / 100;
1613 min(tx_pwr_target[rate], pi->txpwr_env_limit[rate]);
1622 memset(pi->tx_power_offset, 0, sizeof(pi->tx_power_offset));
1623 pi->tx_power_max = tx_pwr_max;
1624 pi->tx_power_min = tx_pwr_min;
1625 pi->tx_power_max_rate_ind = tx_pwr_max_rate_ind;
1628 pi->tx_power_target[rate] = tx_pwr_target[rate];
1630 if (!pi->hwpwrctrl || ISNPHY(pi))
1631 pi->tx_power_offset[rate] =
1632 pi->tx_power_max - pi->tx_power_target[rate];
1634 pi->tx_power_offset[rate] =
1635 pi->tx_power_target[rate] - pi->tx_power_min;
1638 txpwr_recalc_fn = pi->pi_fptr.txpwrrecalc;
1640 (*txpwr_recalc_fn)(pi);
1644 wlc_phy_txpower_reg_limit_calc(struct brcms_phy *pi, struct txpwr_limits *txpwr,
1653 pi->txpwr_limit[rate1] = txpwr->cck[rate2];
1657 pi->txpwr_limit[rate1] = txpwr->ofdm[rate2];
1659 if (ISNPHY(pi)) {
1702 pi->txpwr_limit[rate1] =
1747 pi->txpwr_limit[rate1] =
1768 pi->txpwr_limit[rate1] = txpwr_ptr1[rate2];
1787 pi->txpwr_limit[rate1] = txpwr_ptr1[rate2];
1790 pi->txpwr_limit[WL_TX_POWER_MCS_32] = txpwr->mcs32;
1792 pi->txpwr_limit[WL_TX_POWER_MCS40_CDD_FIRST] =
1793 min(pi->txpwr_limit[WL_TX_POWER_MCS40_CDD_FIRST],
1794 pi->txpwr_limit[WL_TX_POWER_MCS_32]);
1795 pi->txpwr_limit[WL_TX_POWER_MCS_32] =
1796 pi->txpwr_limit[WL_TX_POWER_MCS40_CDD_FIRST];
1802 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1804 pi->txpwr_percent = txpwr_percent;
1809 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1811 pi->sh->machwcap = machwcap;
1816 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1821 if (!ISNPHY(pi))
1824 if (NREV_IS(pi->pubpi.phy_rev, 3)
1825 || NREV_IS(pi->pubpi.phy_rev, 4)) {
1826 bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr),
1828 bcma_set16(pi->d11core, D11REGOFFS(phyregdata),
1832 if (NREV_IS(pi->pubpi.phy_rev, 3)
1833 || NREV_IS(pi->pubpi.phy_rev, 4)) {
1834 bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr),
1836 bcma_write16(pi->d11core, D11REGOFFS(phyregdata), rxc);
1847 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1849 wlc_phy_txpower_reg_limit_calc(pi, txpwr, chanspec);
1851 if (ISLCNPHY(pi)) {
1856 pi->txpwr_limit[i] = txpwr->mcs_20_siso[j];
1858 pi->txpwr_limit[i] = txpwr->ofdm[j];
1862 wlapi_suspend_mac_and_wait(pi->sh->physhim);
1864 wlc_phy_txpower_recalc_target(pi);
1865 wlc_phy_cal_txpower_recalc_sw(pi);
1866 wlapi_enable_mac(pi->sh->physhim);
1871 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
1873 pi->ofdm_rateset_war = war;
1878 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
1880 pi->bf_preempt_4306 = bf_preempt;
1883 void wlc_phy_txpower_update_shm(struct brcms_phy *pi)
1886 if (ISNPHY(pi))
1889 if (!pi->sh->clk)
1892 if (pi->hwpwrctrl) {
1895 wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_MAX, 63);
1896 wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_N,
1899 wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_TARGET,
1900 pi->tx_power_min << NUM_TSSI_FRAMES);
1902 wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_CUR,
1903 pi->hwpwr_txcur);
1910 pi->sh->physhim,
1912 wlapi_bmac_write_shm(pi->sh->physhim, offset + 6,
1913 pi->tx_power_offset[j]);
1914 wlapi_bmac_write_shm(pi->sh->physhim, offset + 14,
1915 -(pi->tx_power_offset[j] / 2));
1918 wlapi_bmac_mhf(pi->sh->physhim, MHF2, MHF2_HWPWRCTL,
1924 pi->tx_power_offset[i] =
1925 (u8) roundup(pi->tx_power_offset[i], 8);
1926 wlapi_bmac_write_shm(pi->sh->physhim, M_OFDM_OFFSET,
1928 ((pi->tx_power_offset[TXP_FIRST_OFDM]
1935 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1937 if (ISNPHY(pi))
1938 return pi->nphy_txpwrctrl;
1940 return pi->hwpwrctrl;
1945 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1948 if (!pi->hwpwrctrl_capable)
1951 pi->hwpwrctrl = hwpwrctrl;
1952 pi->nphy_txpwrctrl = hwpwrctrl;
1953 pi->txpwrctrl = hwpwrctrl;
1955 if (ISNPHY(pi)) {
1956 suspend = (0 == (bcma_read32(pi->d11core,
1960 wlapi_suspend_mac_and_wait(pi->sh->physhim);
1962 wlc_phy_txpwrctrl_enable_nphy(pi, pi->nphy_txpwrctrl);
1963 if (pi->nphy_txpwrctrl == PHY_TPC_HW_OFF)
1964 wlc_phy_txpwr_fixpower_nphy(pi);
1966 mod_phy_reg(pi, 0x1e7, (0x7f << 0),
1967 pi->saved_txpwr_idx);
1970 wlapi_enable_mac(pi->sh->physhim);
1974 void wlc_phy_txpower_ipa_upd(struct brcms_phy *pi)
1977 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
1978 pi->ipa2g_on = (pi->srom_fem2g.extpagain == 2);
1979 pi->ipa5g_on = (pi->srom_fem5g.extpagain == 2);
1981 pi->ipa2g_on = false;
1982 pi->ipa5g_on = false;
1986 static u32 wlc_phy_txpower_est_power_nphy(struct brcms_phy *pi)
1993 estPower1 = read_phy_reg(pi, 0x118);
1994 estPower2 = read_phy_reg(pi, 0x119);
2006 tx0_status = read_phy_reg(pi, 0x1ed);
2007 tx1_status = read_phy_reg(pi, 0x1ee);
2028 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
2036 if (ISNPHY(pi)) {
2039 if (pi->nphy_txpwrctrl == PHY_TPC_HW_ON)
2042 } else if (ISLCNPHY(pi)) {
2045 if (pi->radiopwr_override == RADIOPWR_OVERRIDE_DEF)
2047 if (pi->hwpwrctrl)
2051 num_rates = ((ISNPHY(pi)) ? (TXP_NUM_RATES) :
2052 ((ISLCNPHY(pi)) ?
2056 power->user_limit[rate] = pi->tx_user_target[rate];
2060 power->target[rate] = pi->tx_power_target[rate];
2063 if (ISNPHY(pi)) {
2066 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2067 wlc_phyreg_enter((struct brcms_phy_pub *) pi);
2068 est_pout = wlc_phy_txpower_est_power_nphy(pi);
2069 wlc_phyreg_exit((struct brcms_phy_pub *) pi);
2070 wlapi_enable_mac(pi->sh->physhim);
2090 power->tx_power_max[0] = pi->tx_power_max;
2091 power->tx_power_max[1] = pi->tx_power_max;
2093 power->tx_power_max_rate_ind[0] = pi->tx_power_max_rate_ind;
2094 power->tx_power_max_rate_ind[1] = pi->tx_power_max_rate_ind;
2095 } else if (pi->hwpwrctrl && pi->sh->up) {
2098 if (ISLCNPHY(pi)) {
2100 power->tx_power_max[0] = pi->tx_power_max;
2101 power->tx_power_max[1] = pi->tx_power_max;
2104 pi->tx_power_max_rate_ind;
2106 pi->tx_power_max_rate_ind;
2108 if (wlc_phy_tpc_isenabled_lcnphy(pi))
2117 wlc_lcnphy_get_tssi(pi, (s8 *) &power->est_Pout[0],
2126 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
2128 pi->antsel_type = antsel_type;
2133 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
2135 return pi->phytest_on;
2140 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
2143 pi->sh->rx_antdiv = val;
2145 if (!(ISNPHY(pi) && D11REV_IS(pi->sh->corerev, 16))) {
2147 wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_ANTDIV,
2150 wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_ANTDIV, 0,
2154 if (ISNPHY(pi))
2157 if (!pi->sh->clk)
2160 suspend = (0 == (bcma_read32(pi->d11core, D11REGOFFS(maccontrol)) &
2163 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2165 if (ISLCNPHY(pi)) {
2167 mod_phy_reg(pi, 0x410, (0x1 << 1), 0x01 << 1);
2168 mod_phy_reg(pi, 0x410,
2172 mod_phy_reg(pi, 0x410, (0x1 << 1), 0x00 << 1);
2173 mod_phy_reg(pi, 0x410, (0x1 << 0), (u16) val << 0);
2178 wlapi_enable_mac(pi->sh->physhim);
2184 wlc_phy_noise_calc_phy(struct brcms_phy *pi, u32 *cmplx_pwr, s8 *pwr_ant)
2190 wlc_phy_compute_dB(cmplx_pwr, cmplx_pwr_dbm, pi->pubpi.phy_corenum);
2192 for (i = 0; i < pi->pubpi.phy_corenum; i++) {
2193 if (NREV_GE(pi->pubpi.phy_rev, 3))
2200 for (i = 0; i < pi->pubpi.phy_corenum; i++) {
2201 pi->nphy_noise_win[i][pi->nphy_noise_index] = cmplx_pwr_dbm[i];
2204 pi->nphy_noise_index =
2205 MODINC_POW2(pi->nphy_noise_index, PHY_NOISE_WINDOW_SZ);
2209 static void wlc_phy_noise_cb(struct brcms_phy *pi, u8 channel, s8 noise_dbm)
2211 if (!pi->phynoise_state)
2214 if (pi->phynoise_state & PHY_NOISE_STATE_MON) {
2215 if (pi->phynoise_chan_watchdog == channel) {
2216 pi->sh->phy_noise_window[pi->sh->phy_noise_index] =
2218 pi->sh->phy_noise_index =
2219 MODINC(pi->sh->phy_noise_index, MA_WINDOW_SZ);
2221 pi->phynoise_state &= ~PHY_NOISE_STATE_MON;
2224 if (pi->phynoise_state & PHY_NOISE_STATE_EXTERNAL)
2225 pi->phynoise_state &= ~PHY_NOISE_STATE_EXTERNAL;
2229 static s8 wlc_phy_noise_read_shmem(struct brcms_phy *pi)
2241 for (idx = 0, core = 0; core < pi->pubpi.phy_corenum; idx += 2,
2243 lo = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP(idx));
2244 hi = wlapi_bmac_read_shm(pi->sh->physhim,
2255 wlc_phy_noise_calc_phy(pi, cmplx_pwr, noise_dbm_ant);
2257 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
2258 pi->nphy_noise_win[core][pi->nphy_noise_index] =
2264 pi->nphy_noise_index =
2265 MODINC_POW2(pi->nphy_noise_index, PHY_NOISE_WINDOW_SZ);
2273 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2278 if (ISLCNPHY(pi)) {
2284 jssi_aux = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_AUX);
2287 lo = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP0);
2288 hi = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP1);
2291 lo = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP2);
2292 hi = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP3);
2297 status_1 = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_0);
2302 pi->pubpi.phy_corenum);
2303 pwr_offset_dB = (read_phy_reg(pi, 0x434) & 0xFF);
2314 } else if (ISNPHY(pi)) {
2316 jssi_aux = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_AUX);
2319 noise_dbm = wlc_phy_noise_read_shmem(pi);
2322 wlc_phy_noise_cb(pi, channel, noise_dbm);
2329 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2331 bool sampling_in_progress = (pi->phynoise_state != 0);
2336 pi->phynoise_chan_watchdog = ch;
2337 pi->phynoise_state |= PHY_NOISE_STATE_MON;
2341 pi->phynoise_state |= PHY_NOISE_STATE_EXTERNAL;
2351 pi->phynoise_now = pi->sh->now;
2353 if (pi->phy_fixed_noise) {
2354 if (ISNPHY(pi)) {
2355 pi->nphy_noise_win[WL_ANT_IDX_1][pi->nphy_noise_index] =
2357 pi->nphy_noise_win[WL_ANT_IDX_2][pi->nphy_noise_index] =
2359 pi->nphy_noise_index = MODINC_POW2(pi->nphy_noise_index,
2370 if (ISLCNPHY(pi)) {
2371 if (!pi->phynoise_polling
2373 wlapi_bmac_write_shm(pi->sh->physhim, M_JSSI_0, 0);
2374 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP0, 0);
2375 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP1, 0);
2376 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);
2377 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);
2379 bcma_set32(pi->d11core, D11REGOFFS(maccommand),
2382 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2383 wlc_lcnphy_deaf_mode(pi, (bool) 0);
2384 noise_dbm = (s8) wlc_lcnphy_rx_signal_power(pi, 20);
2385 wlc_lcnphy_deaf_mode(pi, (bool) 1);
2386 wlapi_enable_mac(pi->sh->physhim);
2389 } else if (ISNPHY(pi)) {
2390 if (!pi->phynoise_polling
2393 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP0, 0);
2394 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP1, 0);
2395 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);
2396 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);
2398 bcma_set32(pi->d11core, D11REGOFFS(maccommand),
2416 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2417 classif_state = wlc_phy_classifier_nphy(pi, 0, 0);
2418 wlc_phy_classifier_nphy(pi, 3, 0);
2419 wlc_phy_rx_iq_est_nphy(pi, est, num_samps, wait_time,
2421 wlc_phy_classifier_nphy(pi, (0x7 << 0), classif_state);
2422 wlapi_enable_mac(pi->sh->physhim);
2424 for (i = 0; i < pi->pubpi.phy_corenum; i++)
2428 wlc_phy_noise_calc_phy(pi, cmplx_pwr, noise_dbm_ant);
2430 for (i = 0; i < pi->pubpi.phy_corenum; i++) {
2431 pi->nphy_noise_win[i][pi->nphy_noise_index] =
2437 pi->nphy_noise_index = MODINC_POW2(pi->nphy_noise_index,
2447 wlc_phy_noise_cb(pi, ch, noise_dbm);
2521 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2523 if ((pi->sh->corerev >= 11)
2529 if (ISLCNPHY(pi)) {
2531 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
2546 if (ISLCNPHY(pi)) {
2551 rssi = wlc_phy_rssi_compute_nphy(pi, rxh);
2570 struct brcms_phy *pi;
2571 pi = (struct brcms_phy *) ppi;
2573 if (ISLCNPHY(pi))
2574 wlc_lcnphy_deaf_mode(pi, true);
2575 else if (ISNPHY(pi))
2576 wlc_nphy_deaf_mode(pi, true);
2581 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2583 pi->sh->now++;
2585 if (!pi->watchdog_override)
2588 if (!(SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)))
2589 wlc_phy_noise_sample_request((struct brcms_phy_pub *) pi,
2591 CHSPEC_CHANNEL(pi->
2594 if (pi->phynoise_state && (pi->sh->now - pi->phynoise_now) > 5)
2595 pi->phynoise_state = 0;
2597 if ((!pi->phycal_txpower) ||
2598 ((pi->sh->now - pi->phycal_txpower) >= pi->sh->fast_timer)) {
2600 if (!SCAN_INPROG_PHY(pi) && wlc_phy_cal_txpower_recalc_sw(pi))
2601 pi->phycal_txpower = pi->sh->now;
2604 if ((SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)
2605 || ASSOC_INPROG_PHY(pi)))
2608 if (ISNPHY(pi) && !pi->disable_percal && !delay_phy_cal) {
2610 if ((pi->nphy_perical != PHY_PERICAL_DISABLE) &&
2611 (pi->nphy_perical != PHY_PERICAL_MANUAL) &&
2612 ((pi->sh->now - pi->nphy_perical_last) >=
2613 pi->sh->glacial_timer))
2614 wlc_phy_cal_perical((struct brcms_phy_pub *) pi,
2617 wlc_phy_txpwr_papd_cal_nphy(pi);
2620 if (ISLCNPHY(pi)) {
2621 if (pi->phy_forcecal ||
2622 ((pi->sh->now - pi->phy_lastcal) >=
2623 pi->sh->glacial_timer)) {
2624 if (!(SCAN_RM_IN_PROGRESS(pi) || ASSOC_INPROG_PHY(pi)))
2626 pi,
2629 (SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)
2630 || ASSOC_INPROG_PHY(pi)
2631 || pi->carrier_suppr_disable
2632 || pi->disable_percal))
2633 wlc_lcnphy_calib_modes(pi,
2641 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2646 pi->sh->phy_noise_window[i] = (s8) (rssi & 0xff);
2647 if (ISLCNPHY(pi)) {
2649 pi->sh->phy_noise_window[i] =
2652 pi->sh->phy_noise_index = 0;
2656 pi->nphy_noise_win[k][i] = PHY_NOISE_FIXED_VAL_NPHY;
2658 pi->nphy_noise_index = 0;
2673 void wlc_phy_cal_perical_mphase_reset(struct brcms_phy *pi)
2675 wlapi_del_timer(pi->phycal_timer);
2677 pi->cal_type_override = PHY_PERICAL_AUTO;
2678 pi->mphase_cal_phase_id = MPHASE_CAL_STATE_IDLE;
2679 pi->mphase_txcal_cmdidx = 0;
2683 wlc_phy_cal_perical_mphase_schedule(struct brcms_phy *pi, uint delay)
2686 if ((pi->nphy_perical != PHY_PERICAL_MPHASE) &&
2687 (pi->nphy_perical != PHY_PERICAL_MANUAL))
2690 wlapi_del_timer(pi->phycal_timer);
2692 pi->mphase_cal_phase_id = MPHASE_CAL_STATE_INIT;
2693 wlapi_add_timer(pi->phycal_timer, delay, 0);
2701 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2703 if (!ISNPHY(pi))
2706 if ((pi->nphy_perical == PHY_PERICAL_DISABLE) ||
2707 (pi->nphy_perical == PHY_PERICAL_MANUAL))
2715 if (pi->nphy_perical == PHY_PERICAL_MPHASE) {
2716 if (PHY_PERICAL_MPHASE_PENDING(pi))
2717 wlc_phy_cal_perical_mphase_reset(pi);
2720 pi,
2728 if ((pi->nphy_perical == PHY_PERICAL_MPHASE) &&
2729 PHY_PERICAL_MPHASE_PENDING(pi))
2730 wlc_phy_cal_perical_mphase_reset(pi);
2732 pi->first_cal_after_assoc = true;
2734 pi->cal_type_override = PHY_PERICAL_FULL;
2736 if (pi->phycal_tempdelta)
2737 pi->nphy_lastcal_temp = wlc_phy_tempsense_nphy(pi);
2739 wlc_phy_cal_perical_nphy_run(pi, PHY_PERICAL_FULL);
2743 if (pi->phycal_tempdelta) {
2744 nphy_currtemp = wlc_phy_tempsense_nphy(pi);
2746 (nphy_currtemp > pi->nphy_lastcal_temp) ?
2747 nphy_currtemp - pi->nphy_lastcal_temp :
2748 pi->nphy_lastcal_temp - nphy_currtemp;
2750 if ((delta_temp < (s16) pi->phycal_tempdelta) &&
2751 (pi->nphy_txiqlocal_chanspec ==
2752 pi->radio_chanspec))
2755 pi->nphy_lastcal_temp = nphy_currtemp;
2759 if (pi->nphy_perical == PHY_PERICAL_MPHASE) {
2760 if (!PHY_PERICAL_MPHASE_PENDING(pi))
2762 pi,
2764 } else if (pi->nphy_perical == PHY_PERICAL_SPHASE)
2765 wlc_phy_cal_perical_nphy_run(pi,
2774 void wlc_phy_cal_perical_mphase_restart(struct brcms_phy *pi)
2776 pi->mphase_cal_phase_id = MPHASE_CAL_STATE_INIT;
2777 pi->mphase_txcal_cmdidx = 0;
2794 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2796 pi->sh->hw_phytxchain = txchain;
2797 pi->sh->hw_phyrxchain = rxchain;
2798 pi->sh->phytxchain = txchain;
2799 pi->sh->phyrxchain = rxchain;
2800 pi->pubpi.phy_corenum = (u8)hweight8(pi->sh->phyrxchain);
2805 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2807 pi->sh->phytxchain = txchain;
2809 if (ISNPHY(pi))
2812 pi->pubpi.phy_corenum = (u8)hweight8(pi->sh->phyrxchain);
2817 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2819 *txchain = pi->sh->phytxchain;
2820 *rxchain = pi->sh->phyrxchain;
2827 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2829 active_bitmap = (pi->phy_txcore_heatedup) ? 0x31 : 0x33;
2831 if (!pi->watchdog_override)
2834 if (NREV_GE(pi->pubpi.phy_rev, 6)) {
2835 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2836 nphy_currtemp = wlc_phy_tempsense_nphy(pi);
2837 wlapi_enable_mac(pi->sh->physhim);
2839 if (!pi->phy_txcore_heatedup) {
2840 if (nphy_currtemp >= pi->phy_txcore_disable_temp) {
2842 pi->phy_txcore_heatedup = true;
2845 if (nphy_currtemp <= pi->phy_txcore_enable_temp) {
2847 pi->phy_txcore_heatedup = false;
2857 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2867 if (pi->tx_power_target[siso_mcs_id] >
2868 (pi->tx_power_target[cdd_mcs_id] + 12))
2879 void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode)
2881 if ((pi->sh->chip == BCMA_CHIP_ID_BCM4313) &&
2882 (pi->sh->boardflags & BFL_FEM)) {
2885 txant = wlapi_bmac_get_txant(pi->sh->physhim);
2887 mod_phy_reg(pi, 0x44d, (0x1 << 2), (1) << 2);
2889 mod_phy_reg(pi, 0x44c, (0x1 << 2), (1) << 2);
2893 bcma_chipco_gpio_control(&pi->d11core->bus->drv_cc,
2895 bcma_chipco_gpio_out(&pi->d11core->bus->drv_cc,
2897 bcma_chipco_gpio_outen(&pi->d11core->bus->drv_cc,
2900 mod_phy_reg(pi, 0x44c, (0x1 << 2), (0) << 2);
2902 mod_phy_reg(pi, 0x44d, (0x1 << 2), (0) << 2);
2904 bcma_chipco_gpio_out(&pi->d11core->bus->drv_cc,
2906 bcma_chipco_gpio_outen(&pi->d11core->bus->drv_cc,
2908 bcma_chipco_gpio_control(&pi->d11core->bus->drv_cc,
2920 wlc_phy_get_pwrdet_offsets(struct brcms_phy *pi, s8 *cckoffset, s8 *ofdmoffset)
2926 s8 wlc_phy_upd_rssi_offset(struct brcms_phy *pi, s8 rssi, u16 chanspec)
2934 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
2936 if (ISNPHY(pi))
2937 return wlc_phy_n_txpower_ipa_ison(pi);