Lines Matching refs:B43_LP_NORTH
296 #define B43_LP_NORTH(radio_reg) B43_LP_RADIO(radio_reg)
301 #define B2062_N_COMM1 B43_LP_NORTH(0x000) /* Common 01 (north) */
302 #define B2062_N_COMM2 B43_LP_NORTH(0x002) /* Common 02 (north) */
303 #define B2062_N_COMM3 B43_LP_NORTH(0x003) /* Common 03 (north) */
304 #define B2062_N_COMM4 B43_LP_NORTH(0x004) /* Common 04 (north) */
305 #define B2062_N_COMM5 B43_LP_NORTH(0x005) /* Common 05 (north) */
306 #define B2062_N_COMM6 B43_LP_NORTH(0x006) /* Common 06 (north) */
307 #define B2062_N_COMM7 B43_LP_NORTH(0x007) /* Common 07 (north) */
308 #define B2062_N_COMM8 B43_LP_NORTH(0x008) /* Common 08 (north) */
309 #define B2062_N_COMM9 B43_LP_NORTH(0x009) /* Common 09 (north) */
310 #define B2062_N_COMM10 B43_LP_NORTH(0x00A) /* Common 10 (north) */
311 #define B2062_N_COMM11 B43_LP_NORTH(0x00B) /* Common 11 (north) */
312 #define B2062_N_COMM12 B43_LP_NORTH(0x00C) /* Common 12 (north) */
313 #define B2062_N_COMM13 B43_LP_NORTH(0x00D) /* Common 13 (north) */
314 #define B2062_N_COMM14 B43_LP_NORTH(0x00E) /* Common 14 (north) */
315 #define B2062_N_COMM15 B43_LP_NORTH(0x00F) /* Common 15 (north) */
316 #define B2062_N_PDN_CTL0 B43_LP_NORTH(0x010) /* PDN Control 0 (north) */
317 #define B2062_N_PDN_CTL1 B43_LP_NORTH(0x011) /* PDN Control 1 (north) */
318 #define B2062_N_PDN_CTL2 B43_LP_NORTH(0x012) /* PDN Control 2 (north) */
319 #define B2062_N_PDN_CTL3 B43_LP_NORTH(0x013) /* PDN Control 3 (north) */
320 #define B2062_N_PDN_CTL4 B43_LP_NORTH(0x014) /* PDN Control 4 (north) */
321 #define B2062_N_GEN_CTL0 B43_LP_NORTH(0x015) /* GEN Control 0 (north) */
322 #define B2062_N_IQ_CALIB B43_LP_NORTH(0x016) /* IQ Calibration (north) */
323 #define B2062_N_LGENC B43_LP_NORTH(0x017) /* LGENC (north) */
324 #define B2062_N_LGENA_LPF B43_LP_NORTH(0x018) /* LGENA LPF (north) */
325 #define B2062_N_LGENA_BIAS0 B43_LP_NORTH(0x019) /* LGENA Bias 0 (north) */
326 #define B2062_N_LGNEA_BIAS1 B43_LP_NORTH(0x01A) /* LGNEA Bias 1 (north) */
327 #define B2062_N_LGENA_CTL0 B43_LP_NORTH(0x01B) /* LGENA Control 0 (north) */
328 #define B2062_N_LGENA_CTL1 B43_LP_NORTH(0x01C) /* LGENA Control 1 (north) */
329 #define B2062_N_LGENA_CTL2 B43_LP_NORTH(0x01D) /* LGENA Control 2 (north) */
330 #define B2062_N_LGENA_TUNE0 B43_LP_NORTH(0x01E) /* LGENA Tune 0 (north) */
331 #define B2062_N_LGENA_TUNE1 B43_LP_NORTH(0x01F) /* LGENA Tune 1 (north) */
332 #define B2062_N_LGENA_TUNE2 B43_LP_NORTH(0x020) /* LGENA Tune 2 (north) */
333 #define B2062_N_LGENA_TUNE3 B43_LP_NORTH(0x021) /* LGENA Tune 3 (north) */
334 #define B2062_N_LGENA_CTL3 B43_LP_NORTH(0x022) /* LGENA Control 3 (north) */
335 #define B2062_N_LGENA_CTL4 B43_LP_NORTH(0x023) /* LGENA Control 4 (north) */
336 #define B2062_N_LGENA_CTL5 B43_LP_NORTH(0x024) /* LGENA Control 5 (north) */
337 #define B2062_N_LGENA_CTL6 B43_LP_NORTH(0x025) /* LGENA Control 6 (north) */
338 #define B2062_N_LGENA_CTL7 B43_LP_NORTH(0x026) /* LGENA Control 7 (north) */
339 #define B2062_N_RXA_CTL0 B43_LP_NORTH(0x027) /* RXA Control 0 (north) */
340 #define B2062_N_RXA_CTL1 B43_LP_NORTH(0x028) /* RXA Control 1 (north) */
341 #define B2062_N_RXA_CTL2 B43_LP_NORTH(0x029) /* RXA Control 2 (north) */
342 #define B2062_N_RXA_CTL3 B43_LP_NORTH(0x02A) /* RXA Control 3 (north) */
343 #define B2062_N_RXA_CTL4 B43_LP_NORTH(0x02B) /* RXA Control 4 (north) */
344 #define B2062_N_RXA_CTL5 B43_LP_NORTH(0x02C) /* RXA Control 5 (north) */
345 #define B2062_N_RXA_CTL6 B43_LP_NORTH(0x02D) /* RXA Control 6 (north) */
346 #define B2062_N_RXA_CTL7 B43_LP_NORTH(0x02E) /* RXA Control 7 (north) */
347 #define B2062_N_RXBB_CTL0 B43_LP_NORTH(0x02F) /* RXBB Control 0 (north) */
348 #define B2062_N_RXBB_CTL1 B43_LP_NORTH(0x030) /* RXBB Control 1 (north) */
349 #define B2062_N_RXBB_CTL2 B43_LP_NORTH(0x031) /* RXBB Control 2 (north) */
350 #define B2062_N_RXBB_GAIN0 B43_LP_NORTH(0x032) /* RXBB Gain 0 (north) */
351 #define B2062_N_RXBB_GAIN1 B43_LP_NORTH(0x033) /* RXBB Gain 1 (north) */
352 #define B2062_N_RXBB_GAIN2 B43_LP_NORTH(0x034) /* RXBB Gain 2 (north) */
353 #define B2062_N_RXBB_GAIN3 B43_LP_NORTH(0x035) /* RXBB Gain 3 (north) */
354 #define B2062_N_RXBB_RSSI0 B43_LP_NORTH(0x036) /* RXBB RSSI 0 (north) */
355 #define B2062_N_RXBB_RSSI1 B43_LP_NORTH(0x037) /* RXBB RSSI 1 (north) */
356 #define B2062_N_RXBB_CALIB0 B43_LP_NORTH(0x038) /* RXBB Calibration0 (north) */
357 #define B2062_N_RXBB_CALIB1 B43_LP_NORTH(0x039) /* RXBB Calibration1 (north) */
358 #define B2062_N_RXBB_CALIB2 B43_LP_NORTH(0x03A) /* RXBB Calibration2 (north) */
359 #define B2062_N_RXBB_BIAS0 B43_LP_NORTH(0x03B) /* RXBB Bias 0 (north) */
360 #define B2062_N_RXBB_BIAS1 B43_LP_NORTH(0x03C) /* RXBB Bias 1 (north) */
361 #define B2062_N_RXBB_BIAS2 B43_LP_NORTH(0x03D) /* RXBB Bias 2 (north) */
362 #define B2062_N_RXBB_BIAS3 B43_LP_NORTH(0x03E) /* RXBB Bias 3 (north) */
363 #define B2062_N_RXBB_BIAS4 B43_LP_NORTH(0x03F) /* RXBB Bias 4 (north) */
364 #define B2062_N_RXBB_BIAS5 B43_LP_NORTH(0x040) /* RXBB Bias 5 (north) */
365 #define B2062_N_RXBB_RSSI2 B43_LP_NORTH(0x041) /* RXBB RSSI 2 (north) */
366 #define B2062_N_RXBB_RSSI3 B43_LP_NORTH(0x042) /* RXBB RSSI 3 (north) */
367 #define B2062_N_RXBB_RSSI4 B43_LP_NORTH(0x043) /* RXBB RSSI 4 (north) */
368 #define B2062_N_RXBB_RSSI5 B43_LP_NORTH(0x044) /* RXBB RSSI 5 (north) */
369 #define B2062_N_TX_CTL0 B43_LP_NORTH(0x045) /* TX Control 0 (north) */
370 #define B2062_N_TX_CTL1 B43_LP_NORTH(0x046) /* TX Control 1 (north) */
371 #define B2062_N_TX_CTL2 B43_LP_NORTH(0x047) /* TX Control 2 (north) */
372 #define B2062_N_TX_CTL3 B43_LP_NORTH(0x048) /* TX Control 3 (north) */
373 #define B2062_N_TX_CTL4 B43_LP_NORTH(0x049) /* TX Control 4 (north) */
374 #define B2062_N_TX_CTL5 B43_LP_NORTH(0x04A) /* TX Control 5 (north) */
375 #define B2062_N_TX_CTL6 B43_LP_NORTH(0x04B) /* TX Control 6 (north) */
376 #define B2062_N_TX_CTL7 B43_LP_NORTH(0x04C) /* TX Control 7 (north) */
377 #define B2062_N_TX_CTL8 B43_LP_NORTH(0x04D) /* TX Control 8 (north) */
378 #define B2062_N_TX_CTL9 B43_LP_NORTH(0x04E) /* TX Control 9 (north) */
379 #define B2062_N_TX_CTL_A B43_LP_NORTH(0x04F) /* TX Control A (north) */
380 #define B2062_N_TX_GC2G B43_LP_NORTH(0x050) /* TX GC2G (north) */
381 #define B2062_N_TX_GC5G B43_LP_NORTH(0x051) /* TX GC5G (north) */
382 #define B2062_N_TX_TUNE B43_LP_NORTH(0x052) /* TX Tune (north) */
383 #define B2062_N_TX_PAD B43_LP_NORTH(0x053) /* TX PAD (north) */
384 #define B2062_N_TX_PGA B43_LP_NORTH(0x054) /* TX PGA (north) */
385 #define B2062_N_TX_PADAUX B43_LP_NORTH(0x055) /* TX PADAUX (north) */
386 #define B2062_N_TX_PGAAUX B43_LP_NORTH(0x056) /* TX PGAAUX (north) */
387 #define B2062_N_TSSI_CTL0 B43_LP_NORTH(0x057) /* TSSI Control 0 (north) */
388 #define B2062_N_TSSI_CTL1 B43_LP_NORTH(0x058) /* TSSI Control 1 (north) */
389 #define B2062_N_TSSI_CTL2 B43_LP_NORTH(0x059) /* TSSI Control 2 (north) */
390 #define B2062_N_IQ_CALIB_CTL0 B43_LP_NORTH(0x05A) /* IQ Calibration Control 0 (north) */
391 #define B2062_N_IQ_CALIB_CTL1 B43_LP_NORTH(0x05B) /* IQ Calibration Control 1 (north) */
392 #define B2062_N_IQ_CALIB_CTL2 B43_LP_NORTH(0x05C) /* IQ Calibration Control 2 (north) */
393 #define B2062_N_CALIB_TS B43_LP_NORTH(0x05D) /* Calibration TS (north) */
394 #define B2062_N_CALIB_CTL0 B43_LP_NORTH(0x05E) /* Calibration Control 0 (north) */
395 #define B2062_N_CALIB_CTL1 B43_LP_NORTH(0x05F) /* Calibration Control 1 (north) */
396 #define B2062_N_CALIB_CTL2 B43_LP_NORTH(0x060) /* Calibration Control 2 (north) */
397 #define B2062_N_CALIB_CTL3 B43_LP_NORTH(0x061) /* Calibration Control 3 (north) */
398 #define B2062_N_CALIB_CTL4 B43_LP_NORTH(0x062) /* Calibration Control 4 (north) */
399 #define B2062_N_CALIB_DBG0 B43_LP_NORTH(0x063) /* Calibration Debug 0 (north) */
400 #define B2062_N_CALIB_DBG1 B43_LP_NORTH(0x064) /* Calibration Debug 1 (north) */
401 #define B2062_N_CALIB_DBG2 B43_LP_NORTH(0x065) /* Calibration Debug 2 (north) */
402 #define B2062_N_CALIB_DBG3 B43_LP_NORTH(0x066) /* Calibration Debug 3 (north) */
403 #define B2062_N_PSENSE_CTL0 B43_LP_NORTH(0x069) /* PSENSE Control 0 (north) */
404 #define B2062_N_PSENSE_CTL1 B43_LP_NORTH(0x06A) /* PSENSE Control 1 (north) */
405 #define B2062_N_PSENSE_CTL2 B43_LP_NORTH(0x06B) /* PSENSE Control 2 (north) */
406 #define B2062_N_TEST_BUF0 B43_LP_NORTH(0x06C) /* TEST BUF0 (north) */