ath/wcn36xx/txrx.h

42 	u32	dpu_fb:8;
43 	u32	adu_fb:8;
44 	u32	pdu_id:16;
47 	u32	tail_pdu_idx:16;
48 	u32	head_pdu_idx:16;
51 	u32	pdu_count:7;
52 	u32	mpdu_data_off:9;
53 	u32	mpdu_header_off:8;
54 	u32	mpdu_header_len:8;
57 	u32	reserved4:8;
58 	u32	tid:4;
59 	u32	bd_ssn:2;
60 	u32	reserved3:2;
61 	u32	mpdu_len:16;
65 	u32	bdt:2;
66 	u32	ft:1;
67 	u32	dpu_ne:1;
68 	u32	rx_key_id:3;
69 	u32	ub:1;
70 	u32	rmf:1;
71 	u32	uma_bypass:1;
72 	u32	csr11:1;
73 	u32	reserved0:1;
74 	u32	scan_learn:1;
75 	u32	rx_ch:4;
76 	u32	rtsf:1;
77 	u32	bsf:1;
78 	u32	a2hf:1;
79 	u32	st_auf:1;
80 	u32	dpu_sign:3;
81 	u32	dpu_rf:8;
86 	u32	addr3:8;
87 	u32	addr2:8;
88 	u32	addr1:8;
89 	u32	dpu_desc_idx:8;
92 	u32	rxp_flags:23;
93 	u32	rate_id:9;
95 	u32	phy_stat0;
96 	u32	phy_stat1;
99 	u32	rx_times;
101 	u32	pmi_cmd[6];
104 	u32	reserved7:4;
105 	u32	reorder_slot_id:6;
106 	u32	reorder_fwd_id:6;
107 	u32	reserved6:12;
108 	u32	reorder_code:4;
111 	u32	exp_seq_num:12;
112 	u32	cur_seq_num:12;
113 	u32	rf_band:2;
114 	u32	fr_type_subtype:6;
117 	u32	msdu_size:16;
118 	u32	sub_fr_id:4;
119 	u32	proc_order:4;
120 	u32	reserved9:4;
121 	u32	aef:1;
122 	u32	lsf:1;
123 	u32	esf:1;
124 	u32	asf:1;
128 	u32	bdt:2;
129 	u32	ft:1;
130 	u32	dpu_ne:1;
131 	u32	fw_tx_comp:1;
132 	u32	tx_comp:1;
133 	u32	reserved1:1;
134 	u32	ub:1;
135 	u32	rmf:1;
136 	u32	reserved0:12;
137 	u32	dpu_sign:3;
138 	u32	dpu_rf:8;
143 	u32	reserved5:7;
144 	u32	queue_id:5;
145 	u32	bd_rate:2;
146 	u32	ack_policy:2;
147 	u32	sta_index:8;
148 	u32	dpu_desc_idx:8;
150 	u32	tx_bd_sign;
151 	u32	reserved6;
152 	u32	dxe_start_time;
153 	u32	dxe_end_time;
155 	/*u32	tcp_udp_start_off:10;
156 	u32	header_cks:16;
157 	u32	reserved7:6;*/