ath/carl9170/phy.c

441 	u32 val;
459 		val = carl9170_def_val(AR9170_PHY_REG_SETTLING,
461 		SET_VAL(AR9170_PHY_SETTLING_SWITCH, val, m->switchSettling);
462 		carl9170_regwrite(AR9170_PHY_REG_SETTLING, val);
466 	val = carl9170_def_val(AR9170_PHY_REG_DESIRED_SZ, is_2ghz, is_40mhz);
467 	SET_VAL(AR9170_PHY_DESIRED_SZ_PGA, val, m->pgaDesiredSize);
468 	SET_VAL(AR9170_PHY_DESIRED_SZ_ADC, val, m->adcDesiredSize);
469 	carl9170_regwrite(AR9170_PHY_REG_DESIRED_SZ, val);
472 	val = carl9170_def_val(AR9170_PHY_REG_RF_CTL4, is_2ghz, is_40mhz);
473 	SET_VAL(AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF, val, m->txEndToXpaOff);
474 	SET_VAL(AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF, val, m->txEndToXpaOff);
475 	SET_VAL(AR9170_PHY_RF_CTL4_FRAME_XPAB_ON, val, m->txFrameToXpaOn);
476 	SET_VAL(AR9170_PHY_RF_CTL4_FRAME_XPAA_ON, val, m->txFrameToXpaOn);
477 	carl9170_regwrite(AR9170_PHY_REG_RF_CTL4, val);
480 	val = carl9170_def_val(AR9170_PHY_REG_RF_CTL3, is_2ghz, is_40mhz);
481 	SET_VAL(AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON, val, m->txEndToRxOn);
482 	carl9170_regwrite(AR9170_PHY_REG_RF_CTL3, val);
485 	val = carl9170_def_val(0x1c8864, is_2ghz, is_40mhz);
486 	val = (val & ~0x7f000) | (m->thresh62 << 12);
487 	carl9170_regwrite(0x1c8864, val);
490 	val = carl9170_def_val(AR9170_PHY_REG_RXGAIN, is_2ghz, is_40mhz);
491 	SET_VAL(AR9170_PHY_RXGAIN_TXRX_ATTEN, val, m->txRxAttenCh[0]);
492 	carl9170_regwrite(AR9170_PHY_REG_RXGAIN, val);
495 	val = carl9170_def_val(AR9170_PHY_REG_RXGAIN_CHAIN_2,
497 	SET_VAL(AR9170_PHY_RXGAIN_TXRX_ATTEN, val, m->txRxAttenCh[1]);
498 	carl9170_regwrite(AR9170_PHY_REG_RXGAIN_CHAIN_2, val);
501 	val = carl9170_def_val(AR9170_PHY_REG_GAIN_2GHZ, is_2ghz, is_40mhz);
502 	SET_VAL(AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN, val, m->rxTxMarginCh[0]);
505 		SET_VAL(AR9170_PHY_GAIN_2GHZ_BSW_MARGIN, val, m->bswMargin[0]);
506 	carl9170_regwrite(AR9170_PHY_REG_GAIN_2GHZ, val);
509 	val = carl9170_def_val(AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2,
511 	SET_VAL(AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN, val, m->rxTxMarginCh[1]);
512 	carl9170_regwrite(AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2, val);
515 	val = carl9170_def_val(AR9170_PHY_REG_TIMING_CTRL4(0),
517 	SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, val, m->iqCalICh[0]);
518 	SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, val, m->iqCalQCh[0]);
519 	carl9170_regwrite(AR9170_PHY_REG_TIMING_CTRL4(0), val);
522 	val = carl9170_def_val(AR9170_PHY_REG_TIMING_CTRL4(2),
524 	SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, val, m->iqCalICh[1]);
525 	SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, val, m->iqCalQCh[1]);
526 	carl9170_regwrite(AR9170_PHY_REG_TIMING_CTRL4(2), val);
529 	val = carl9170_def_val(AR9170_PHY_REG_TPCRG1, is_2ghz, is_40mhz);
530 	SET_VAL(AR9170_PHY_TPCRG1_PD_GAIN_1, val,
532 	SET_VAL(AR9170_PHY_TPCRG1_PD_GAIN_2, val,
534 	carl9170_regwrite(AR9170_PHY_REG_TPCRG1, val);
546 	u32 val;
555 				val = ar5416_phy_init[i]._2ghz_40;
557 				val = ar5416_phy_init[i]._5ghz_40;
560 				val = ar5416_phy_init[i]._2ghz_20;
562 				val = ar5416_phy_init[i]._5ghz_20;
565 		carl9170_regwrite(ar5416_phy_init[i].reg, val);