ath/carl9170/phy.c

44 static int carl9170_init_power_cal(struct ar9170 *ar)
46 	carl9170_regwrite_begin(ar);
432 static int carl9170_init_phy_from_eeprom(struct ar9170 *ar,
440 	struct ar9170_eeprom_modal *m = &ar->eeprom.modal_header[is_2ghz];
443 	carl9170_regwrite_begin(ar);
536 	carl9170_regwrite(AR9170_PHY_REG_RX_CHAINMASK, ar->eeprom.rx_mask);
537 	carl9170_regwrite(AR9170_PHY_REG_CAL_CHAINMASK, ar->eeprom.rx_mask);
543 static int carl9170_init_phy(struct ar9170 *ar, enum nl80211_band band)
548 	bool is_40mhz = conf_is_ht40(&ar->hw->conf);
550 	carl9170_regwrite_begin(ar);
573 	err = carl9170_init_phy_from_eeprom(ar, is_2ghz, is_40mhz);
577 	err = carl9170_init_power_cal(ar);
581 	if (!ar->fw.hw_counters) {
582 		err = carl9170_write_reg(ar, AR9170_PWR_REG_PLL_ADDAC,
672 static int carl9170_init_rf_banks_0_7(struct ar9170 *ar, bool band5ghz)
676 	carl9170_regwrite_begin(ar);
686 		wiphy_err(ar->hw->wiphy, "rf init failed\n");
966 static int carl9170_init_rf_bank4_pwr(struct ar9170 *ar, bool band5ghz,
1021 	carl9170_regwrite_begin(ar);
1117 static int carl9170_set_freq_cal_data(struct ar9170 *ar,
1130 		cal_freq_pier = ar->eeprom.cal_freq_pier_2G;
1136 		cal_freq_pier = ar->eeprom.cal_freq_pier_5G;
1153 	carl9170_regwrite_begin(ar);
1162 				cal_pier_data = &ar->eeprom.
1167 				cal_pier_data = &ar->eeprom.
1217 static u8 carl9170_get_max_edge_power(struct ar9170 *ar,
1259 static u8 carl9170_get_heavy_clip(struct ar9170 *ar, u32 freq,
1289  * and apply them to ar->power* (derived from otus hal/hpmain.c, line 3706)
1291 static void carl9170_calc_ctl(struct ar9170 *ar, u32 freq, enum carl9170_bw bw)
1308 		{ CTL_11B, 0, ar->power_2G_cck, 4 },
1309 		{ CTL_11G, 0, ar->power_2G_ofdm, 4 },
1310 		{ CTL_2GHT20, 0, ar->power_2G_ht20, 8 },
1311 		{ CTL_2GHT40, 0, ar->power_2G_ht40, 8 },
1314 		{ CTL_11A, 0, ar->power_5G_leg, 4 },
1315 		{ CTL_5GHT20, 0, ar->power_5G_ht20, 8 },
1316 		{ CTL_5GHT40, 0, ar->power_5G_ht40, 8 },
1320 #define EDGES(c, n) (ar->eeprom.ctl_data[c].control_edges[n])
1322 	ar->heavy_clip = 0;
1332 	ctl_grp = ath_regd_get_band_ctl(&ar->common.regulatory,
1333 					ar->hw->conf.chandef.chan->band);
1343 	if (ar->hw->conf.chandef.chan->band == NL80211_BAND_2GHZ) {
1354 			if (c == ar->eeprom.ctl_index[ctl_idx])
1364 				ar->heavy_clip =
1365 					carl9170_get_heavy_clip(ar,
1379 				carl9170_get_max_edge_power(ar,
1407 		/* apply max power to pwr_cal_data (ar->power_*) */
1414 	if (ar->heavy_clip & 0xf0) {
1415 		ar->power_2G_ht40[0]--;
1416 		ar->power_2G_ht40[1]--;
1417 		ar->power_2G_ht40[2]--;
1419 	if (ar->heavy_clip & 0xf) {
1420 		ar->power_2G_ht20[0]++;
1421 		ar->power_2G_ht20[1]++;
1422 		ar->power_2G_ht20[2]++;
1428 static void carl9170_set_power_cal(struct ar9170 *ar, u32 freq,
1452 			ctpl = &ar->eeprom.cal_tgt_pwr_5G[0];
1454 			ctpres = ar->power_5G_leg;
1457 			ctpl = &ar->eeprom.cal_tgt_pwr_2G_cck[0];
1459 			ctpres = ar->power_2G_cck;
1462 			ctpl = &ar->eeprom.cal_tgt_pwr_2G_ofdm[0];
1464 			ctpres = ar->power_2G_ofdm;
1487 			ctph = &ar->eeprom.cal_tgt_pwr_5G_ht20[0];
1489 			ctpres = ar->power_5G_ht20;
1492 			ctph = &ar->eeprom.cal_tgt_pwr_5G_ht40[0];
1494 			ctpres = ar->power_5G_ht40;
1497 			ctph = &ar->eeprom.cal_tgt_pwr_2G_ht20[0];
1499 			ctpres = ar->power_2G_ht20;
1502 			ctph = &ar->eeprom.cal_tgt_pwr_2G_ht40[0];
1504 			ctpres = ar->power_2G_ht40;
1523 	/* calc. conformance test limits and apply to ar->power*[] */
1524 	carl9170_calc_ctl(ar, freq, bw);
1527 int carl9170_get_noisefloor(struct ar9170 *ar)
1535 	BUILD_BUG_ON(ARRAY_SIZE(phy_regs) != ARRAY_SIZE(ar->noise));
1537 	err = carl9170_read_mreg(ar, ARRAY_SIZE(phy_regs), phy_regs, phy_res);
1542 		ar->noise[i] = sign_extend32(GET_VAL(
1545 		ar->noise[i + 2] = sign_extend32(GET_VAL(
1549 	if (ar->channel)
1550 		ar->survey[ar->channel->hw_value].noise = ar->noise[0];
1570 int carl9170_set_channel(struct ar9170 *ar, struct ieee80211_channel *channel,
1583 	if (conf_is_ht(&ar->hw->conf))
1586 	if (conf_is_ht40(&ar->hw->conf))
1590 	if (ar->channel) {
1591 		old_channel = ar->channel;
1592 		ar->channel = NULL;
1596 	err = carl9170_write_reg(ar, AR9170_PWR_REG_RESET,
1601 	err = carl9170_write_reg(ar, AR9170_PWR_REG_RESET, 0x0);
1605 	err = carl9170_init_phy(ar, channel->band);
1609 	err = carl9170_init_rf_banks_0_7(ar,
1614 	err = carl9170_exec_cmd(ar, CARL9170_CMD_FREQ_START, 0, NULL, 0, NULL);
1618 	err = carl9170_write_reg(ar, AR9170_PHY_REG_HEAVY_CLIP_ENABLE,
1623 	err = carl9170_init_rf_bank4_pwr(ar,
1651 	if (ar->eeprom.tx_mask != 1)
1654 	err = carl9170_write_reg(ar, AR9170_PHY_REG_TURBO, tmp);
1658 	err = carl9170_set_freq_cal_data(ar, channel);
1662 	carl9170_set_power_cal(ar, channel->center_freq, bw);
1664 	err = carl9170_set_mac_tpc(ar, channel);
1671 	if (conf_is_ht40(&ar->hw->conf))
1680 	err = carl9170_exec_cmd(ar, CARL9170_CMD_RF_INIT, sizeof(rf), &rf,
1687 		ar->chan_fail++;
1688 		ar->total_chan_fail++;
1690 		wiphy_err(ar->hw->wiphy, "channel change: %d -> %d "
1695 		if (ar->chan_fail > 3) {
1702 			carl9170_restart(ar, CARL9170_RR_TOO_MANY_PHY_ERRORS);
1706 		err = carl9170_set_channel(ar, channel, _bw);
1710 		ar->chan_fail = 0;
1713 	if (ar->heavy_clip) {
1714 		err = carl9170_write_reg(ar, AR9170_PHY_REG_HEAVY_CLIP_ENABLE,
1715 					 0x200 | ar->heavy_clip);
1718 				wiphy_err(ar->hw->wiphy, "failed to set "
1726 	ar->channel = channel;
1727 	ar->ht_settings = new_ht;