ath/ath9k/eeprom_def.c

208 	struct base_eep_header *pBase = &eep->baseEepHeader;
209 	u32 binBuildNumber = le32_to_cpu(pBase->binBuildNumber);
225 	PR_EEP("Checksum", le16_to_cpu(pBase->checksum));
226 	PR_EEP("Length", le16_to_cpu(pBase->length));
227 	PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
228 	PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
229 	PR_EEP("TX Mask", pBase->txMask);
230 	PR_EEP("RX Mask", pBase->rxMask);
231 	PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
232 	PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));
233 	PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &
235 	PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &
237 	PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &
239 	PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &
241 	PR_EEP("Big Endian", !!(pBase->eepMisc & AR5416_EEPMISC_BIG_ENDIAN));
245 	PR_EEP("OpenLoop Power Ctrl", pBase->openLoopPwrCntl);
248 			 pBase->macAddr);
338 	struct base_eep_header *pBase = &eep->baseEepHeader;
347 		return get_unaligned_be16(pBase->macAddr);
349 		return get_unaligned_be16(pBase->macAddr + 2);
351 		return get_unaligned_be16(pBase->macAddr + 4);
353 		return le16_to_cpu(pBase->regDmn[0]);
355 		return le16_to_cpu(pBase->deviceCap);
357 		return pBase->opCapFlags;
359 		return le16_to_cpu(pBase->rfSilent);
369 		return pBase->txMask;
371 		return pBase->rxMask;
373 		return pBase->fastClk5g;
375 		return pBase->rxGainType;
377 		return pBase->txGainType;
380 			return pBase->openLoopPwrCntl ? true : false;
385 			return pBase->rcChainMask;
390 			return pBase->dacHiPwrMode_5G;
395 			return pBase->frac_n_5g;
400 			return pBase->pwr_table_offset;