Lines Matching refs:ah
21 static void ath9k_get_txgain_index(struct ath_hw *ah,
31 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
49 while (pcdac > ah->originalGain[i] &&
56 static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
64 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
66 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
69 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
80 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
82 u16 version = le16_to_cpu(ah->eeprom.def.baseEepHeader.version);
88 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
90 u16 version = le16_to_cpu(ah->eeprom.def.baseEepHeader.version);
97 static bool __ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
99 u16 *eep_data = (u16 *)&ah->eeprom.def;
103 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
111 static bool __ath9k_hw_usb_def_fill_eeprom(struct ath_hw *ah)
113 u16 *eep_data = (u16 *)&ah->eeprom.def;
115 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data,
120 static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
122 struct ath_common *common = ath9k_hw_common(ah);
124 if (!ath9k_hw_use_flash(ah)) {
129 return __ath9k_hw_usb_def_fill_eeprom(ah);
131 return __ath9k_hw_def_fill_eeprom(ah);
204 static u32 ath9k_hw_def_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
207 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
223 PR_EEP("Major Version", ath9k_hw_def_get_eeprom_ver(ah));
224 PR_EEP("Minor Version", ath9k_hw_def_get_eeprom_rev(ah));
257 static u32 ath9k_hw_def_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
264 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
266 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
267 struct ath_common *common = ath9k_hw_common(ah);
272 err = ath9k_hw_nvram_swap_data(ah, &need_swap, SIZE_EEPROM_DEF);
282 if (!ath9k_hw_nvram_validate_checksum(ah, el))
314 if (!ath9k_hw_nvram_check_version(ah, AR5416_EEP_VER,
319 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
322 ah->need_an_top2_fixup = true;
325 (AR_SREV_9280(ah)))
333 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
336 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
379 if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_19)
384 if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_19)
389 if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_20)
394 if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_22)
399 if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_21)
416 static void ath9k_hw_def_set_gain(struct ath_hw *ah,
421 ENABLE_REG_RMW_BUFFER(ah);
422 if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_3) {
425 if (AR_SREV_9280_20_OR_LATER(ah)) {
426 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
429 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
432 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
435 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
439 REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
442 REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
448 if (AR_SREV_9280_20_OR_LATER(ah)) {
449 REG_RMW_FIELD(ah,
452 REG_RMW_FIELD(ah,
456 REG_RMW(ah, AR_PHY_RXGAIN + regChainOffset,
459 REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
463 REG_RMW_BUFFER_FLUSH(ah);
466 static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
470 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
479 REG_WRITE(ah, AR_PHY_SWITCH_COM, antCtrlCommon & 0xffff);
482 if (AR_SREV_9280(ah)) {
487 if ((ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
492 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
495 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
496 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
504 ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
508 if (AR_SREV_9280_20_OR_LATER(ah)) {
510 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
514 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
518 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
522 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
527 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
531 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
535 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
539 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
544 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
548 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
553 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
557 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
559 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
562 if (!AR_SREV_9280_20_OR_LATER(ah))
563 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
567 REG_WRITE(ah, AR_PHY_RF_CTL4,
576 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
579 if (AR_SREV_9280_20_OR_LATER(ah)) {
580 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
582 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
586 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
588 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
593 if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_2) {
594 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
597 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
601 if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_3) {
603 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
608 if (AR_SREV_9280_20_OR_LATER(ah) &&
609 ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_19)
610 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
615 if (AR_SREV_9280_20(ah) &&
616 ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_20) {
618 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
621 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
623 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
628 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
631 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
637 static void ath9k_hw_def_set_addac(struct ath_hw *ah,
642 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
645 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
648 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
659 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
682 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
685 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
691 static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
706 if (AR_SREV_9280_20_OR_LATER(ah)) {
732 static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
745 if (AR_SREV_9280_20_OR_LATER(ah)) {
761 static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
767 struct ath_common *common = ath9k_hw_common(ah);
768 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
785 pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
787 if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_2) {
791 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
803 if (OLC_FOR_AR9280_20_LATER(ah) && IS_CHAN_2GHZ(chan)) {
805 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
821 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
823 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
825 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
827 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
831 if ((ah->rxchainmask == 5 || ah->txchainmask == 5) &&
844 if (OLC_FOR_AR9280_20_LATER(ah)) {
848 ath9k_get_txgain_index(ah, chan,
851 ath9k_olc_get_pdadcs(ah, pcdacIdx,
854 ath9k_hw_get_gain_boundaries_pdadcs(ah,
863 diff = ath9k_change_gain_boundary_setting(ah,
870 ENABLE_REGWRITE_BUFFER(ah);
872 if (OLC_FOR_AR9280_20_LATER(ah)) {
873 REG_WRITE(ah,
880 REG_WRITE(ah,
890 ath9k_adjust_pdadc_values(ah, pwr_table_offset,
896 REG_WRITE(ah, regOffset, reg32);
911 REGWRITE_BUFFER_FLUSH(ah);
919 static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
926 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
955 tx_chainmask = ah->txchainmask;
957 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
959 scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
967 ath9k_hw_get_legacy_target_powers(ah, chan,
971 ath9k_hw_get_legacy_target_powers(ah, chan,
975 ath9k_hw_get_target_powers(ah, chan,
982 ath9k_hw_get_target_powers(ah, chan,
986 ath9k_hw_get_legacy_target_powers(ah, chan,
990 ath9k_hw_get_legacy_target_powers(ah, chan,
1000 ath9k_hw_get_legacy_target_powers(ah, chan,
1004 ath9k_hw_get_target_powers(ah, chan,
1011 ath9k_hw_get_target_powers(ah, chan,
1015 ath9k_hw_get_legacy_target_powers(ah, chan,
1142 static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1149 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1150 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1159 if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_2)
1162 ath9k_hw_set_def_power_per_rate_table(ah, chan,
1167 ath9k_hw_set_def_power_cal_table(ah, chan);
1177 ath9k_hw_update_regulatory_maxpower(ah);
1182 if (AR_SREV_9280_20_OR_LATER(ah)) {
1186 pwr_table_offset = ah->eep_ops->get_eeprom(ah,
1192 ENABLE_REGWRITE_BUFFER(ah);
1194 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1199 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1206 if (OLC_FOR_AR9280_20_LATER(ah)) {
1208 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1213 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1219 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1224 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1232 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1237 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1244 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1253 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1262 if (OLC_FOR_AR9280_20_LATER(ah)) {
1263 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1269 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1277 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1282 if (ah->tpc_enabled) {
1286 ar5008_hw_init_rate_txpower(ah, ratesArray, chan, ht40_delta);
1288 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX,
1292 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER);
1295 REGWRITE_BUFFER_FLUSH(ah);
1298 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1300 __le16 spch = ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan;
1305 static u8 ath9k_hw_def_get_eepmisc(struct ath_hw *ah)
1307 return ah->eeprom.def.baseEepHeader.eepMisc;