ath/ath9k/eeprom_9287.c

130 	struct base_eep_ar9287_header *pBase = &eep->baseEepHeader;
131 	u32 binBuildNumber = le32_to_cpu(pBase->binBuildNumber);
143 	PR_EEP("Checksum", le16_to_cpu(pBase->checksum));
144 	PR_EEP("Length", le16_to_cpu(pBase->length));
145 	PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
146 	PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
147 	PR_EEP("TX Mask", pBase->txMask);
148 	PR_EEP("RX Mask", pBase->rxMask);
149 	PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
150 	PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));
151 	PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &
153 	PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &
155 	PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &
157 	PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &
159 	PR_EEP("Big Endian", !!(pBase->eepMisc & AR5416_EEPMISC_BIG_ENDIAN));
163 	PR_EEP("Power Table Offset", pBase->pwrTableOffset);
164 	PR_EEP("OpenLoop Power Ctrl", pBase->openLoopPwrCntl);
167 			 pBase->macAddr);
237 	struct base_eep_ar9287_header *pBase = &eep->baseEepHeader;
244 		return get_unaligned_be16(pBase->macAddr);
246 		return get_unaligned_be16(pBase->macAddr + 2);
248 		return get_unaligned_be16(pBase->macAddr + 4);
250 		return le16_to_cpu(pBase->regDmn[0]);
252 		return le16_to_cpu(pBase->deviceCap);
254 		return pBase->opCapFlags;
256 		return le16_to_cpu(pBase->rfSilent);
258 		return pBase->txMask;
260 		return pBase->rxMask;
262 		return pBase->deviceType;
264 		return pBase->openLoopPwrCntl;
267 			return pBase->tempSensSlope;
272 			return pBase->tempSensSlopePalOn;