Lines Matching refs:pBase
134 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
135 u32 binBuildNumber = le32_to_cpu(pBase->binBuildNumber);
147 PR_EEP("Checksum", le16_to_cpu(pBase->checksum));
148 PR_EEP("Length", le16_to_cpu(pBase->length));
149 PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
150 PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
151 PR_EEP("TX Mask", pBase->txMask);
152 PR_EEP("RX Mask", pBase->rxMask);
153 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
154 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));
155 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &
157 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &
159 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &
161 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &
163 PR_EEP("Big Endian", !!(pBase->eepMisc & AR5416_EEPMISC_BIG_ENDIAN));
167 PR_EEP("TX Gain type", pBase->txGainType);
170 pBase->macAddr);
239 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
245 return get_unaligned_be16(pBase->macAddr);
247 return get_unaligned_be16(pBase->macAddr + 2);
249 return get_unaligned_be16(pBase->macAddr + 4);
251 return le16_to_cpu(pBase->regDmn[0]);
253 return le16_to_cpu(pBase->deviceCap);
255 return pBase->opCapFlags;
257 return le16_to_cpu(pBase->rfSilent);
263 return pBase->txMask;
265 return pBase->rxMask;
275 return pBase->txGainType;
762 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
1009 if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) {