Lines Matching refs:ah
21 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
23 u16 version = le16_to_cpu(ah->eeprom.map4k.baseEepHeader.version);
29 static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
31 u16 version = le16_to_cpu(ah->eeprom.map4k.baseEepHeader.version);
38 static bool __ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
40 u16 *eep_data = (u16 *)&ah->eeprom.map4k;
44 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data))
52 static bool __ath9k_hw_usb_4k_fill_eeprom(struct ath_hw *ah)
54 u16 *eep_data = (u16 *)&ah->eeprom.map4k;
56 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data, 64, SIZE_EEPROM_4K);
61 static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
63 struct ath_common *common = ath9k_hw_common(ah);
65 if (!ath9k_hw_use_flash(ah)) {
70 return __ath9k_hw_usb_4k_fill_eeprom(ah);
72 return __ath9k_hw_4k_fill_eeprom(ah);
130 static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
133 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
145 PR_EEP("Major Version", ath9k_hw_4k_get_eeprom_ver(ah));
146 PR_EEP("Minor Version", ath9k_hw_4k_get_eeprom_rev(ah));
179 static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
186 static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
188 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
193 err = ath9k_hw_nvram_swap_data(ah, &need_swap, SIZE_EEPROM_4K);
203 if (!ath9k_hw_nvram_validate_checksum(ah, el))
225 if (!ath9k_hw_nvram_check_version(ah, AR5416_EEP_VER,
234 static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
237 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
283 static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
286 struct ath_common *common = ath9k_hw_common(ah);
287 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
300 if (ath9k_hw_4k_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_2)
304 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
322 ENABLE_REG_RMW_BUFFER(ah);
323 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
325 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
327 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
329 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
330 REG_RMW_BUFFER_FLUSH(ah);
338 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
344 ENABLE_REGWRITE_BUFFER(ah);
346 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
361 REG_WRITE(ah, regOffset, reg32);
381 REGWRITE_BUFFER_FLUSH(ah);
386 static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
408 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
424 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
431 ath9k_hw_get_legacy_target_powers(ah, chan,
435 ath9k_hw_get_legacy_target_powers(ah, chan,
439 ath9k_hw_get_target_powers(ah, chan,
446 ath9k_hw_get_target_powers(ah, chan,
450 ath9k_hw_get_legacy_target_powers(ah, chan,
454 ath9k_hw_get_legacy_target_powers(ah, chan,
482 ar5416_get_ntxchains(ah->txchainmask) - 1],
577 static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
583 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
584 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
592 if (ath9k_hw_4k_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_2)
595 ath9k_hw_set_4k_power_per_rate_table(ah, chan,
600 ath9k_hw_set_4k_power_cal_table(ah, chan);
617 ENABLE_REGWRITE_BUFFER(ah);
620 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
625 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
632 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
637 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
644 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
649 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
657 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
666 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
675 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
683 if (ah->tpc_enabled) {
687 ar5008_hw_init_rate_txpower(ah, ratesArray, chan, ht40_delta);
689 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX,
693 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER);
696 REGWRITE_BUFFER_FLUSH(ah);
699 static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
704 ENABLE_REG_RMW_BUFFER(ah);
705 REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0,
708 REG_RMW(ah, AR_PHY_TIMING_CTRL4(0),
713 if (ath9k_hw_4k_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_3) {
716 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
718 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
720 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
723 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
727 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
730 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
732 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
735 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
740 REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
742 REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
745 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
747 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
749 REG_RMW_BUFFER_FLUSH(ah);
756 static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
759 struct ath9k_hw_capabilities *pCap = &ah->caps;
761 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
772 REG_WRITE(ah, AR_PHY_SWITCH_COM, le32_to_cpu(pModal->antCtrlCommon));
775 ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
782 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
797 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
798 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
799 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
804 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
805 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
812 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
822 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
861 ENABLE_REG_RMW_BUFFER(ah);
862 if (AR_SREV_9271(ah)) {
863 ath9k_hw_analog_shift_rmw(ah,
868 ath9k_hw_analog_shift_rmw(ah,
873 ath9k_hw_analog_shift_rmw(ah,
878 ath9k_hw_analog_shift_rmw(ah,
883 ath9k_hw_analog_shift_rmw(ah,
889 ath9k_hw_analog_shift_rmw(ah,
894 ath9k_hw_analog_shift_rmw(ah,
899 ath9k_hw_analog_shift_rmw(ah,
904 ath9k_hw_analog_shift_rmw(ah,
909 ath9k_hw_analog_shift_rmw(ah,
915 ath9k_hw_analog_shift_rmw(ah,
920 ath9k_hw_analog_shift_rmw(ah,
925 ath9k_hw_analog_shift_rmw(ah,
930 ath9k_hw_analog_shift_rmw(ah,
935 ath9k_hw_analog_shift_rmw(ah,
940 ath9k_hw_analog_shift_rmw(ah,
945 ath9k_hw_analog_shift_rmw(ah,
950 ath9k_hw_analog_shift_rmw(ah,
955 ath9k_hw_analog_shift_rmw(ah,
960 ath9k_hw_analog_shift_rmw(ah,
966 REG_RMW_BUFFER_FLUSH(ah);
968 ENABLE_REG_RMW_BUFFER(ah);
969 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
971 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
974 REG_RMW(ah, AR_PHY_RF_CTL4,
980 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
983 if (AR_SREV_9271_10(ah))
984 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
986 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
988 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
991 if (ath9k_hw_4k_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_2) {
992 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
994 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
998 if (ath9k_hw_4k_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_3) {
1000 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1005 REG_RMW_BUFFER_FLUSH(ah);
1015 ENABLE_REG_RMW_BUFFER(ah);
1016 REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr);
1017 REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr);
1018 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr);
1023 REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr);
1028 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr);
1029 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr);
1030 REG_RMW_BUFFER_FLUSH(ah);
1034 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1036 return le16_to_cpu(ah->eeprom.map4k.modalHeader.spurChans[i].spurChan);
1039 static u8 ath9k_hw_4k_get_eepmisc(struct ath_hw *ah)
1041 return ah->eeprom.map4k.baseEepHeader.eepMisc;