ath/ath9k/ar9003_wow.c

23 static void ath9k_hw_set_sta_powersave(struct ath_hw *ah)
25 	if (!ath9k_hw_mci_is_enabled(ah))
31 	if (ar9003_mci_state(ah, MCI_STATE_GET_WLAN_PS_STATE) != MCI_PS_DISABLE)
34 	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
37 static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
39 	struct ath_common *common = ath9k_hw_common(ah);
41 	ath9k_hw_set_sta_powersave(ah);
44 	REG_WRITE(ah, AR_CR, AR_CR_RXD);
46 	if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE(ah), 0, AH_WAIT_TIMEOUT)) {
48 			REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
52 	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
53 		if (!REG_READ(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL))
54 			REG_CLR_BIT(ah, AR_DIRECT_CONNECT, AR_DC_TSF2_ENABLE);
55 	} else if (AR_SREV_9485(ah)){
56 		if (!(REG_READ(ah, AR_NDP2_TIMER_MODE) &
58 			REG_CLR_BIT(ah, AR_DIRECT_CONNECT, AR_DC_TSF2_ENABLE);
61 	if (ath9k_hw_mci_is_enabled(ah))
62 		REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
64 	REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_ON_INT);
67 static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
69 	struct ath_common *common = ath9k_hw_common(ah);
83 	ctl[7] = (ah->txchainmask) << 2;
86 	if (IS_CHAN_2GHZ(ah->curchan))
92 		REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
106 	if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565(ah)) {
111 		REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0);
118 		REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]);
121 int ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
129 	if (pattern_count >= ah->wow.max_patterns)
133 		REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
135 		REG_SET_BIT(ah, AR_MAC_PCU_WOW4, BIT(pattern_count - 8));
139 		REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
146 		REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
151 		ah->wow.wow_event_mask |=
154 		ah->wow.wow_event_mask2 |=
161 		REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
166 		REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
171 		REG_RMW(ah, AR_WOW_LENGTH3, set, clr);
176 		REG_RMW(ah, AR_WOW_LENGTH4, set, clr);
183 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
192 	rval = REG_READ(ah, AR_WOW_PATTERN);
200 	val &= ah->wow.wow_event_mask;
213 	rval = REG_READ(ah, AR_MAC_PCU_WOW4);
215 	val &= ah->wow.wow_event_mask2;
229 	REG_RMW(ah, AR_PCIE_PM_CTRL(ah), AR_PMCTRL_WOW_PME_CLR,
235 	REG_WRITE(ah, AR_WOW_PATTERN,
236 		  AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
237 	REG_WRITE(ah, AR_MAC_PCU_WOW4,
238 		  AR_WOW_CLEAR_EVENTS2(REG_READ(ah, AR_MAC_PCU_WOW4)));
243 	REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
252 	if (ah->is_pciexpress)
253 		ath9k_hw_configpcipowersave(ah, false);
255 	if (AR_SREV_9462(ah) || AR_SREV_9565(ah) || AR_SREV_9485(ah)) {
256 		u32 dc = REG_READ(ah, AR_DIRECT_CONNECT);
259 			ath9k_hw_gen_timer_start_tsf2(ah);
262 	ah->wow.wow_event_mask = 0;
263 	ah->wow.wow_event_mask2 = 0;
269 static void ath9k_hw_wow_set_arwr_reg(struct ath_hw *ah)
273 	if (!ah->is_pciexpress)
281 	wa_reg = REG_READ(ah, AR_WA(ah));
286 	REG_WRITE(ah, AR_WA(ah), wa_reg);
289 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
294 	wow_event_mask = ah->wow.wow_event_mask;
312 	REG_SET_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PMCTRL_HOST_PME_EN |
316 	REG_CLR_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PMCTRL_WOW_PME_CLR);
326 	REG_SET_BIT(ah, AR_WOW_PATTERN,
332 	REG_SET_BIT(ah, AR_WOW_COUNT, AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
339 		REG_WRITE(ah, AR_WOW_BCN_TIMO, AR_WOW_BEACON_TIMO);
341 		REG_WRITE(ah, AR_WOW_BCN_TIMO, AR_WOW_BEACON_TIMO_MAX);
347 		REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, AR_WOW_KEEP_ALIVE_NEVER);
349 		REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, KAL_TIMEOUT * 32);
354 	REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, KAL_DELAY * 1000);
359 	ath9k_wow_create_keep_alive_pattern(ah);
364 	keep_alive = REG_READ(ah, AR_WOW_KEEP_ALIVE);
376 	REG_WRITE(ah, AR_WOW_KEEP_ALIVE, keep_alive);
382 	REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
387 		REG_SET_BIT(ah, AR_WOW_BCN_EN, AR_WOW_BEACON_FAIL_EN);
389 		REG_CLR_BIT(ah, AR_WOW_BCN_EN, AR_WOW_BEACON_FAIL_EN);
395 	magic_pattern = REG_READ(ah, AR_WOW_PATTERN);
405 	REG_WRITE(ah, AR_WOW_PATTERN, magic_pattern);
411 	REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
417 	host_pm_ctrl = REG_READ(ah, AR_PCIE_PM_CTRL(ah));
423 	if (AR_SREV_9462(ah)) {
433 	REG_WRITE(ah, AR_PCIE_PM_CTRL(ah), host_pm_ctrl);
438 	REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
441 	REG_SET_BIT(ah, AR_PCIE_PHY_REG3, BIT(13));
443 	ath9k_hw_wow_set_arwr_reg(ah);
445 	if (ath9k_hw_mci_is_enabled(ah))
446 		REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
449 	REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, BIT(5));
451 	ath9k_hw_set_powermode_wow_sleep(ah);
452 	ah->wow.wow_event_mask = wow_event_mask;