Lines Matching defs:set
26 goto set;
28 * If MCI is being used, set PWR_SAV only when MCI's
33 set:
43 /* set rx disable bit */
79 /* set the transmit buffer */
127 u32 set, clr;
158 set = (pattern_len & AR_WOW_LENGTH_MAX) <<
161 REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
163 set = (pattern_len & AR_WOW_LENGTH_MAX) <<
166 REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
168 set = (pattern_len & AR_WOW_LENGTH_MAX) <<
171 REG_RMW(ah, AR_WOW_LENGTH3, set, clr);
173 set = (pattern_len & AR_WOW_LENGTH_MAX) <<
176 REG_RMW(ah, AR_WOW_LENGTH4, set, clr);
223 * set and clear WOW_PME_CLEAR registers for the chip to
303 * needs to be set for WoW in PCI mode.