ath/ath9k/ar9003_paprd.c

21 void ar9003_paprd_enable(struct ath_hw *ah, bool val)
23 	struct ath9k_channel *chan = ah->curchan;
41 			if (ar9003_get_paprd_rate_mask_ht20(ah, is2ghz)
45 			if (ar9003_get_paprd_rate_mask_ht20(ah, is2ghz)
49 			if (ar9003_get_paprd_rate_mask_ht20(ah, is2ghz)
56 		ah->paprd_table_write_done = true;
57 		ath9k_hw_apply_txpower(ah, chan, false);
60 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0,
62 	if (ah->caps.tx_chainmask & BIT(1))
63 		REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B1,
65 	if (ah->caps.tx_chainmask & BIT(2))
66 		REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B2,
71 static int ar9003_get_training_power_2g(struct ath_hw *ah)
73 	struct ath9k_channel *chan = ah->curchan;
76 	scale = ar9003_get_paprd_scale_factor(ah, chan);
78 	if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
79 	    AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
80 		power = ah->paprd_target_power + 2;
81 	} else if (AR_SREV_9485(ah)) {
84 		power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE5,
87 		delta = abs((int) ah->paprd_target_power - (int) power);
98 static int ar9003_get_training_power_5g(struct ath_hw *ah)
100 	struct ath_common *common = ath9k_hw_common(ah);
101 	struct ath9k_channel *chan = ah->curchan;
104 	scale = ar9003_get_paprd_scale_factor(ah, chan);
107 		power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE8,
110 		power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE6,
114 	delta = abs((int) ah->paprd_target_power - (int) power);
118 	switch (get_streams(ah->txchainmask)) {
131 			ah->txchainmask);
138 static int ar9003_paprd_setup_single_table(struct ath_hw *ah)
140 	struct ath_common *common = ath9k_hw_common(ah);
153 	u32 am2pm_mask = ah->paprd_ratemask;
155 	if (IS_CHAN_2GHZ(ah->curchan))
156 		training_power = ar9003_get_training_power_2g(ah);
158 		training_power = ar9003_get_training_power_5g(ah);
161 		training_power, ah->paprd_target_power);
168 	ah->paprd_training_power = training_power;
170 	if (AR_SREV_9330(ah))
173 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2AM, AR_PHY_PAPRD_AM2AM_MASK,
174 		      ah->paprd_ratemask);
175 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK,
177 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK,
178 		      ah->paprd_ratemask_ht40);
181 		ah->paprd_ratemask, ah->paprd_ratemask_ht40);
183 	for (i = 0; i < ah->caps.max_txchains; i++) {
184 		REG_RMW_FIELD(ah, ctrl0[i],
186 		REG_RMW_FIELD(ah, ctrl1[i],
188 		REG_RMW_FIELD(ah, ctrl1[i],
190 		REG_RMW_FIELD(ah, ctrl1[i],
192 		REG_RMW_FIELD(ah, ctrl1[i],
194 		REG_RMW_FIELD(ah, ctrl1[i],
196 		REG_RMW_FIELD(ah, ctrl1[i],
198 		REG_RMW_FIELD(ah, ctrl0[i],
202 	ar9003_paprd_enable(ah, false);
204 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1(ah),
206 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1(ah),
208 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1(ah),
210 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1(ah),
212 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1(ah),
214 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1(ah),
216 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1(ah),
219 	if (AR_SREV_9485(ah)) {
222 		if (IS_CHAN_2GHZ(ah->curchan)) {
223 			if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
232 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL2(ah),
234 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3(ah),
236 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3(ah),
238 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3(ah),
240 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3(ah),
243 	if (AR_SREV_9485(ah) ||
244 	    AR_SREV_9462(ah) ||
245 	    AR_SREV_9565(ah) ||
246 	    AR_SREV_9550(ah) ||
247 	    AR_SREV_9330(ah) ||
248 	    AR_SREV_9340(ah))
249 		REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3(ah),
252 		REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3(ah),
257 	if (IS_CHAN_2GHZ(ah->curchan) && !AR_SREV_9462(ah) && !AR_SREV_9565(ah))
260 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3(ah),
263 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3(ah),
265 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL4(ah),
267 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL4(ah),
269 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL4(ah),
272 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_0_B0,
274 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_1_B0,
276 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_2_B0,
278 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_3_B0,
280 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_4_B0,
282 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_5_B0,
284 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_6_B0,
286 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_7_B0,
291 static void ar9003_paprd_get_gain_table(struct ath_hw *ah)
293 	u32 *entry = ah->paprd_gain_table_entries;
294 	u8 *index = ah->paprd_gain_table_index;
299 		entry[i] = REG_READ(ah, reg);
305 static unsigned int ar9003_get_desired_gain(struct ath_hw *ah, int chain,
316 	REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1(ah),
318 	desired_scale = REG_READ_FIELD(ah, AR_PHY_TPC_12,
320 	alpha_therm = REG_READ_FIELD(ah, AR_PHY_TPC_19,
322 	alpha_volt = REG_READ_FIELD(ah, AR_PHY_TPC_19,
324 	therm_cal_value = REG_READ_FIELD(ah, AR_PHY_TPC_18,
326 	volt_cal_value = REG_READ_FIELD(ah, AR_PHY_TPC_18,
328 	therm_value = REG_READ_FIELD(ah, AR_PHY_BB_THERM_ADC_4,
330 	volt_value = REG_READ_FIELD(ah, AR_PHY_BB_THERM_ADC_4,
347 		ath_dbg(ath9k_hw_common(ah), CALIBRATE,
352 	olpc_gain_delta = REG_READ_FIELD(ah, reg_olpc,
354 	cl_gain_mod = REG_READ_FIELD(ah, reg_cl_gain,
370 static void ar9003_tx_force_gain(struct ath_hw *ah, unsigned int gain_index)
374 	u32 *gain_table_entries = ah->paprd_gain_table_entries;
385 	REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
387 	REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
389 	REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
391 	REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
393 	REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
395 	REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
397 	REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
399 	REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
401 	REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
403 	REG_RMW_FIELD(ah, AR_PHY_TPC_1, AR_PHY_TPC_1_FORCED_DAC_GAIN, 0);
404 	REG_RMW_FIELD(ah, AR_PHY_TPC_1, AR_PHY_TPC_1_FORCE_DAC_GAIN, 0);
751 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
757 	u32 training_power = ah->paprd_training_power;
769 		REG_WRITE(ah, reg, paprd_table_val[i]);
780 	REG_RMW_FIELD(ah, reg, AR_PHY_PA_GAIN123_PA_GAIN1, small_signal_gain);
782 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B0,
786 	if (ah->caps.tx_chainmask & BIT(1))
787 		REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B1,
791 	if (ah->caps.tx_chainmask & BIT(2))
793 		REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B2,
799 void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain)
802 	unsigned int train_power = ah->paprd_training_power;
804 	desired_gain = ar9003_get_desired_gain(ah, chain, train_power);
808 		if (ah->paprd_gain_table_index[i] >= desired_gain)
813 	ar9003_tx_force_gain(ah, gain_index);
815 	REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1(ah),
820 static bool ar9003_paprd_retrain_pa_in(struct ath_hw *ah,
830 	if (!AR_SREV_9485(ah) && !AR_SREV_9330(ah))
833 	capdiv2g = REG_READ_FIELD(ah, AR_PHY_65NM_CH0_TXRF3,
836 	quick_drop = REG_READ_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3(ah),
847 	if (AR_SREV_9485(ah)) {
876 	} else if (AR_SREV_9330(ah)) {
907 	REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3,
909 	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3(ah),
916 int ar9003_paprd_create_curve(struct ath_hw *ah,
935 	REG_CLR_BIT(ah, AR_PHY_CHAN_INFO_MEMORY(ah),
940 		data_L[i] = REG_READ(ah, reg + (i << 2));
942 	REG_SET_BIT(ah, AR_PHY_CHAN_INFO_MEMORY(ah),
946 		data_U[i] = REG_READ(ah, reg + (i << 2));
951 	if (ar9003_paprd_retrain_pa_in(ah, caldata, chain))
954 	REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1(ah),
963 int ar9003_paprd_init_table(struct ath_hw *ah)
967 	ret = ar9003_paprd_setup_single_table(ah);
971 	ar9003_paprd_get_gain_table(ah);
976 bool ar9003_paprd_is_done(struct ath_hw *ah)
980 	paprd_done = REG_READ_FIELD(ah, AR_PHY_PAPRD_TRAINER_STAT1(ah),
983 	if (AR_SREV_9485(ah))
987 		agc2_pwr = REG_READ_FIELD(ah, AR_PHY_PAPRD_TRAINER_STAT1(ah),
990 		ath_dbg(ath9k_hw_common(ah), CALIBRATE,
1006 bool ar9003_is_paprd_enabled(struct ath_hw *ah)
1008 	if ((ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->config.enable_paprd)