Lines Matching refs:ah
2958 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2973 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2976 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3003 if (AR_SREV_9565(ah))
3016 static bool ar9300_eeprom_read_byte(struct ath_hw *ah, int address,
3021 if (unlikely(!ath9k_hw_nvram_read(ah, address / 2, &val)))
3028 static bool ar9300_eeprom_read_word(struct ath_hw *ah, int address,
3033 if (unlikely(!ath9k_hw_nvram_read(ah, address / 2, &val)))
3042 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3045 struct ath_common *common = ath9k_hw_common(ah);
3059 if (!ar9300_eeprom_read_byte(ah, address--, buffer++))
3066 if (!ar9300_eeprom_read_word(ah, address, buffer))
3074 if (!ar9300_eeprom_read_byte(ah, address, buffer))
3085 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3087 REG_READ(ah, AR9300_OTP_BASE(ah) + (4 * addr));
3089 if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS(ah), AR9300_OTP_STATUS_TYPE,
3093 *data = REG_READ(ah, AR9300_OTP_READ_DATA(ah));
3097 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3105 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3143 static bool ar9300_uncompress_block(struct ath_hw *ah,
3153 struct ath_common *common = ath9k_hw_common(ah);
3180 static int ar9300_compress_decision(struct ath_hw *ah,
3187 struct ath_common *common = ath9k_hw_common(ah);
3217 ar9300_uncompress_block(ah, mptr, mdata_size,
3227 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3236 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3241 if (!read(ah, base_addr, header, 4))
3247 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3254 if (!ath9k_hw_nvram_read(ah, i, data))
3266 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3278 struct ath_common *common = ath9k_hw_common(ah);
3282 if (ath9k_hw_use_flash(ah)) {
3285 if (ar9300_eeprom_restore_flash(ah, mptr, mdata_size))
3302 if (AR_SREV_9485(ah))
3304 else if (AR_SREV_9330(ah))
3310 if (ar9300_check_eeprom_header(ah, read, cptr))
3316 if (ar9300_check_eeprom_header(ah, read, cptr))
3322 if (ar9300_check_eeprom_header(ah, read, cptr))
3328 if (ar9300_check_eeprom_header(ah, read, cptr))
3333 if (ar9300_check_eeprom_header(ah, read, cptr))
3342 if (!read(ah, cptr, word, COMP_HDR_LEN))
3353 if ((!AR_SREV_9485(ah) && length >= 1024) ||
3354 (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485) ||
3362 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3368 ar9300_compress_decision(ah, it, code, reference, mptr,
3390 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3392 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3394 if (ar9300_eeprom_restore_internal(ah, mptr,
3440 static u32 ar9003_dump_cal_data(struct ath_hw *ah, char *buf, u32 len, u32 size,
3443 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3494 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3497 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3507 len = ar9003_dump_cal_data(ah, buf, len, size, true);
3515 len = ar9003_dump_cal_data(ah, buf, len, size, false);
3522 PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion);
3566 ah->eeprom.ar9300_eep.macAddr);
3574 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3582 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3584 return ah->eeprom.ar9300_eep.eepromVersion;
3588 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3593 static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah,
3596 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3604 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3606 int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl;
3608 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
3609 AR_SREV_9531(ah) || AR_SREV_9561(ah))
3610 REG_RMW_FIELD(ah, AR_CH0_TOP2(ah), AR_CH0_TOP2_XPABIASLVL, bias);
3611 else if (AR_SREV_9462(ah) || AR_SREV_9550(ah) || AR_SREV_9565(ah))
3612 REG_RMW_FIELD(ah, AR_CH0_TOP(ah), AR_CH0_TOP_XPABIASLVL, bias);
3614 REG_RMW_FIELD(ah, AR_CH0_TOP(ah), AR_CH0_TOP_XPABIASLVL, bias);
3615 REG_RMW_FIELD(ah, AR_CH0_THERM(ah),
3618 REG_RMW_FIELD(ah, AR_CH0_THERM(ah),
3623 static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz)
3625 return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt);
3628 u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3630 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon);
3633 u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3635 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2);
3638 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain,
3641 __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain];
3645 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3647 struct ath_common *common = ath9k_hw_common(ah);
3648 struct ath9k_hw_capabilities *pCap = &ah->caps;
3657 if (AR_SREV_9485(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0)) {
3658 if (ah->config.xlna_gpio)
3659 gpio = ah->config.xlna_gpio;
3663 ath9k_hw_gpio_request_out(ah, gpio, NULL,
3667 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3669 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3670 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3672 } else if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
3673 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3676 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3693 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565(ah)) {
3694 value = ar9003_switch_com_spdt_get(ah, is2ghz);
3695 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
3697 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE);
3700 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3701 if (AR_SREV_9485(ah) && common->bt_ant_diversity) {
3703 value |= ah->config.ant_ctrl_comm2g_switch_enable;
3706 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3708 if ((AR_SREV_9462(ah)) && (ah->rxchainmask == 0x2)) {
3709 value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
3710 REG_RMW_FIELD(ah, switch_chain_reg[0],
3715 if ((ah->rxchainmask & BIT(chain)) ||
3716 (ah->txchainmask & BIT(chain))) {
3717 value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3719 REG_RMW_FIELD(ah, switch_chain_reg[chain],
3724 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3725 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3730 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3737 if (AR_SREV_9485(ah) && common->bt_ant_diversity)
3740 if (AR_SREV_9565(ah)) {
3744 REG_SET_BIT(ah, AR_PHY_RESTART,
3748 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
3754 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
3758 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
3763 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3766 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3770 if ((AR_SREV_9485(ah) || AR_SREV_9565(ah))
3774 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3777 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3791 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3796 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3798 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3807 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3815 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3817 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3828 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3830 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3835 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3838 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3843 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3866 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3871 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3893 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3902 if ((AR_SREV_9462(ah)) && (ah->rxchainmask == 0x2)) {
3903 value = ar9003_hw_atten_chain_get(ah, 1, chan);
3904 REG_RMW_FIELD(ah, ext_atten_reg[0],
3907 value = ar9003_hw_atten_chain_get_margin(ah, 1, chan);
3908 REG_RMW_FIELD(ah, ext_atten_reg[0],
3915 if (ah->txchainmask & BIT(i)) {
3916 value = ar9003_hw_atten_chain_get(ah, i, chan);
3917 REG_RMW_FIELD(ah, ext_atten_reg[i],
3920 if (AR_SREV_9485(ah) &&
3921 (ar9003_hw_get_rx_gain_idx(ah) == 0) &&
3922 ah->config.xatten_margin_cfg)
3925 value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3927 if (ah->config.alt_mingainidx)
3928 REG_RMW_FIELD(ah, AR_PHY_EXT_ATTEN_CTL_0,
3932 REG_RMW_FIELD(ah, ext_atten_reg[i],
3939 static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3943 while (pmu_set != REG_READ(ah, pmu_reg)) {
3946 REG_WRITE(ah, pmu_reg, pmu_set);
3953 void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3955 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3960 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3963 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2(ah)) & ~AR_PHY_PMU2_PGM;
3964 REG_WRITE(ah, AR_PHY_PMU2(ah), reg_pmu_set);
3965 if (!is_pmu_set(ah, AR_PHY_PMU2(ah), reg_pmu_set))
3968 if (AR_SREV_9330(ah)) {
3969 if (ah->is_clk_25mhz) {
3987 REG_WRITE(ah, AR_PHY_PMU1(ah), reg_pmu_set);
3988 if (!is_pmu_set(ah, AR_PHY_PMU1(ah), reg_pmu_set))
3991 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2(ah)) & ~0xFFC00000)
3993 REG_WRITE(ah, AR_PHY_PMU2(ah), reg_pmu_set);
3994 if (!is_pmu_set(ah, AR_PHY_PMU2(ah), reg_pmu_set))
3997 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2(ah)) & ~0x00200000)
3999 REG_WRITE(ah, AR_PHY_PMU2(ah), reg_pmu_set);
4000 if (!is_pmu_set(ah, AR_PHY_PMU2(ah), reg_pmu_set))
4002 } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah) ||
4003 AR_SREV_9561(ah)) {
4005 REG_WRITE(ah, AR_PHY_PMU1(ah), reg_val);
4007 if (AR_SREV_9561(ah))
4008 REG_WRITE(ah, AR_PHY_PMU2(ah), 0x10200000);
4012 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
4013 REG_READ(ah, AR_RTC_REG_CONTROL1) &
4015 REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val);
4017 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
4018 REG_READ(ah,
4023 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
4024 REG_RMW_FIELD(ah, AR_PHY_PMU2(ah), AR_PHY_PMU2_PGM, 0);
4025 while (REG_READ_FIELD(ah, AR_PHY_PMU2(ah),
4029 REG_RMW_FIELD(ah, AR_PHY_PMU1(ah), AR_PHY_PMU1_PWD, 0x1);
4030 while (!REG_READ_FIELD(ah, AR_PHY_PMU1(ah),
4033 REG_RMW_FIELD(ah, AR_PHY_PMU2(ah), AR_PHY_PMU2_PGM, 0x1);
4034 while (!REG_READ_FIELD(ah, AR_PHY_PMU2(ah),
4037 } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
4038 REG_RMW_FIELD(ah, AR_PHY_PMU1(ah), AR_PHY_PMU1_PWD, 0x1);
4040 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK(ah)) |
4042 REG_WRITE(ah, AR_RTC_SLEEP_CLK(ah), reg_val);
4048 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
4050 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4053 if (AR_SREV_9340(ah) || AR_SREV_9531(ah))
4058 REG_RMW_FIELD(ah, AR_CH0_XTAL(ah), AR_CH0_XTAL_CAPINDAC,
4060 REG_RMW_FIELD(ah, AR_CH0_XTAL(ah), AR_CH0_XTAL_CAPOUTDAC,
4065 static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)
4067 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4075 if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9340(ah)) {
4084 REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
4088 static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz)
4092 value = ar9003_modal_header(ah, is2ghz)->txEndToXpaOff;
4094 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
4096 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
4100 static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz)
4102 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4108 if (!AR_SREV_9300(ah) &&
4109 !AR_SREV_9340(ah) &&
4110 !AR_SREV_9580(ah) &&
4111 !AR_SREV_9531(ah) &&
4112 !AR_SREV_9561(ah))
4115 xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn;
4117 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
4120 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
4124 static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz)
4126 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4132 if (!AR_SREV_9300(ah))
4135 bias = ar9003_modal_header(ah, is2ghz)->xlna_bias_strength;
4136 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
4139 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
4142 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
4146 static int ar9003_hw_get_thermometer(struct ath_hw *ah)
4148 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4155 static void ar9003_hw_thermometer_apply(struct ath_hw *ah)
4157 struct ath9k_hw_capabilities *pCap = &ah->caps;
4158 int thermometer = ar9003_hw_get_thermometer(ah);
4161 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4,
4164 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4,
4167 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4,
4171 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4,
4175 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4,
4180 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4,
4185 static void ar9003_hw_thermo_cal_apply(struct ath_hw *ah)
4189 if (!AR_SREV_9462_20_OR_LATER(ah))
4192 ar9300_otp_read_word(ah, 1, &data);
4196 REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3,
4198 REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3,
4204 static void ar9003_hw_apply_minccapwr_thresh(struct ath_hw *ah,
4207 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4225 if (!(ah->caps.tx_chainmask & BIT(chain)))
4228 val = ar9003_modal_header(ah, is2ghz)->noiseFloorThreshCh[chain];
4229 REG_RMW_FIELD(ah, cca_ctrl[chain],
4235 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
4239 ar9003_hw_xpa_timing_control_apply(ah, is2ghz);
4240 ar9003_hw_xpa_bias_level_apply(ah, is2ghz);
4241 ar9003_hw_ant_ctrl_apply(ah, is2ghz);
4242 ar9003_hw_drive_strength_apply(ah);
4243 ar9003_hw_xlna_bias_strength_apply(ah, is2ghz);
4244 ar9003_hw_atten_apply(ah, chan);
4245 ar9003_hw_quick_drop_apply(ah, chan->channel);
4246 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9531(ah))
4247 ar9003_hw_internal_regulator_apply(ah);
4248 ar9003_hw_apply_tuning_caps(ah);
4249 ar9003_hw_apply_minccapwr_thresh(ah, is2ghz);
4250 ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz);
4251 ar9003_hw_thermometer_apply(ah);
4252 ar9003_hw_thermo_cal_apply(ah);
4255 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
4323 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
4329 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4358 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
4365 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4394 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
4401 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4430 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
4436 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4455 static void ar9003_hw_selfgen_tpc_txpower(struct ath_hw *ah,
4471 REG_WRITE(ah, AR_TPC, val);
4475 int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
4479 REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
4484 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
4491 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
4500 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
4507 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
4517 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
4527 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
4535 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
4543 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
4553 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
4565 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
4573 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
4581 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
4592 static void ar9003_hw_get_legacy_target_powers(struct ath_hw *ah, u16 freq,
4597 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4600 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4603 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4606 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4610 static void ar9003_hw_get_cck_target_powers(struct ath_hw *ah, u16 freq,
4614 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4617 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4619 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4621 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4624 static void ar9003_hw_get_ht20_target_powers(struct ath_hw *ah, u16 freq,
4628 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4631 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4634 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4637 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4640 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4643 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4646 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4649 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4652 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4655 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4658 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4661 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4664 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4667 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4671 static void ar9003_hw_get_ht40_target_powers(struct ath_hw *ah,
4680 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4683 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4687 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4690 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4693 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4696 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4699 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4702 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4705 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4708 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4711 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4714 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4717 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4720 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4724 static void ar9003_hw_get_target_power_eeprom(struct ath_hw *ah,
4730 struct ath_common *common = ath9k_hw_common(ah);
4734 ar9003_hw_get_cck_target_powers(ah, freq, targetPowerValT2);
4736 ar9003_hw_get_legacy_target_powers(ah, freq, targetPowerValT2, is2GHz);
4737 ar9003_hw_get_ht20_target_powers(ah, freq, targetPowerValT2, is2GHz);
4740 ar9003_hw_get_ht40_target_powers(ah, freq, targetPowerValT2,
4749 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4760 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4761 struct ath_common *common = ath9k_hw_common(ah);
4803 static void ar9003_hw_power_control_override(struct ath_hw *ah,
4809 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4812 REG_RMW(ah, AR_PHY_TPC_11_B0,
4815 if (ah->caps.tx_chainmask & BIT(1))
4816 REG_RMW(ah, AR_PHY_TPC_11_B1,
4819 if (ah->caps.tx_chainmask & BIT(2))
4820 REG_RMW(ah, AR_PHY_TPC_11_B2,
4825 REG_RMW(ah, AR_PHY_TPC_6_B0,
4828 if (ah->caps.tx_chainmask & BIT(1))
4829 REG_RMW(ah, AR_PHY_TPC_6_B1,
4832 if (ah->caps.tx_chainmask & BIT(2))
4833 REG_RMW(ah, AR_PHY_TPC_6_B2,
4844 if (AR_SREV_9550(ah)) {
4892 if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
4902 REG_RMW_FIELD(ah, AR_PHY_TPC_19,
4906 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4910 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
4915 REG_RMW_FIELD(ah, AR_PHY_TPC_19,
4919 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4923 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
4933 REG_RMW_FIELD(ah, AR_PHY_TPC_19,
4936 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4939 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
4943 REG_RMW_FIELD(ah, AR_PHY_TPC_19,
4947 if (AR_SREV_9462_20_OR_LATER(ah))
4948 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4952 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4957 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4974 struct ath_common *common = ath9k_hw_common(ah);
4989 if (!ar9003_hw_cal_pier_get(ah, is2ghz, ipier, ichain,
5117 ar9003_hw_power_control_override(ah, frequency, correction, voltage,
5127 ah->nf_2g.cal[ichain] = nf_cal[ichain];
5128 ah->nf_2g.pwr[ichain] = nf_pwr[ichain];
5130 ah->nf_5g.cal[ichain] = nf_cal[ichain];
5131 ah->nf_5g.pwr[ichain] = nf_pwr[ichain];
5225 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
5231 struct ath_common *common = ath9k_hw_common(ah);
5232 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
5252 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
5253 scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
5378 if (ath9k_hw_mci_is_enabled(ah))
5381 ar9003_mci_get_max_txpower(ah,
5391 if (ath9k_hw_mci_is_enabled(ah))
5394 ar9003_mci_get_max_txpower(ah,
5414 static void ar9003_paprd_set_txpower(struct ath_hw *ah,
5420 if (!ar9003_is_paprd_enabled(ah))
5429 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) &&
5430 !AR_SREV_9462(ah) && !AR_SREV_9565(ah)) {
5438 ah->paprd_target_power = targetPowerValT2[i];
5441 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
5446 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
5447 struct ath_common *common = ath9k_hw_common(ah);
5459 ar9003_hw_get_target_power_eeprom(ah, chan, targetPowerValT2);
5461 if (ar9003_is_paprd_enabled(ah)) {
5462 ah->paprd_ratemask =
5463 ar9003_get_paprd_rate_mask_ht20(ah, IS_CHAN_2GHZ(chan)) &
5466 ah->paprd_ratemask_ht40 =
5467 ar9003_get_paprd_rate_mask_ht40(ah, IS_CHAN_2GHZ(chan)) &
5470 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
5474 if (!ah->paprd_table_write_done) {
5479 if (ah->paprd_ratemask & (1 << i)) {
5492 ar9003_hw_set_power_per_rate_table(ah, chan,
5500 if (ar9003_is_paprd_enabled(ah)) {
5502 if ((ah->paprd_ratemask & (1 << i)) &&
5506 ah->paprd_ratemask &= ~(1 << i);
5519 ath9k_hw_update_regulatory_maxpower(ah);
5530 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
5531 ar9003_hw_calibration_apply(ah, chan->channel);
5532 ar9003_paprd_set_txpower(ah, chan, targetPowerValT2);
5534 ar9003_hw_selfgen_tpc_txpower(ah, chan, targetPowerValT2);
5537 if (ah->tpc_enabled) {
5540 ar9003_hw_init_rate_txpower(ah, targetPowerValT2_tpc, chan);
5543 REG_WRITE(ah, AR_PHY_PWRTX_MAX,
5546 val = REG_READ(ah, AR_PHY_POWER_TX_SUB);
5547 if (AR_SREV_9340(ah))
5548 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
5551 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
5555 REG_WRITE(ah, AR_PHY_PWRTX_MAX, 0);
5559 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
5565 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
5567 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5572 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
5574 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5579 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is2ghz)
5581 return ar9003_modal_header(ah, is2ghz)->spurChans;
5584 u32 ar9003_get_paprd_rate_mask_ht20(struct ath_hw *ah, bool is2ghz)
5586 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->papdRateMaskHt20);
5589 u32 ar9003_get_paprd_rate_mask_ht40(struct ath_hw *ah, bool is2ghz)
5591 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->papdRateMaskHt40);
5594 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
5600 return MS(ar9003_get_paprd_rate_mask_ht20(ah, is2ghz),
5604 return MS(ar9003_get_paprd_rate_mask_ht20(ah, is2ghz),
5607 return MS(ar9003_get_paprd_rate_mask_ht40(ah, is2ghz),
5610 return MS(ar9003_get_paprd_rate_mask_ht40(ah, is2ghz),
5615 static u8 ar9003_get_eepmisc(struct ath_hw *ah)
5617 return ah->eeprom.ar9300_eep.baseEepHeader.opCapFlags.eepMisc;