ath/ath9k/ar9003_aic.c

40 static bool ar9003_hw_is_aic_enabled(struct ath_hw *ah)
42 	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
106 static void ar9003_aic_gain_table(struct ath_hw *ah)
111 	REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x2c200a00);
112 	REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x5c4e4438);
155 	REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000),
160 		REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000),
165 static u8 ar9003_aic_cal_start(struct ath_hw *ah, u8 min_valid_count)
167 	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;
171 	REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000),
176 		REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000), 0);
180 	REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B0,
190 	REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B1,
197 	REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B0,
206 	REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B1,
210 	REG_WRITE(ah, AR_PHY_AIC_CTRL_2_B0,
220 	REG_WRITE(ah, AR_PHY_AIC_CTRL_3_B0,
230 	REG_WRITE(ah, AR_PHY_AIC_CTRL_4_B0,
237 	REG_WRITE(ah, AR_PHY_AIC_CTRL_4_B1,
244 	ar9003_aic_gain_table(ah);
247 	REG_WRITE(ah, ATH_AIC_BT_JUPITER_CTRL,
248 		  (REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) |
251 	aic->aic_cal_start_time = REG_READ(ah, AR_TSF_L32);
254 	REG_CLR_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
255 	REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_CH_VALID_RESET);
256 	REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
264 static bool ar9003_aic_cal_post_process(struct ath_hw *ah)
266 	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;
437 static void ar9003_aic_cal_done(struct ath_hw *ah)
439 	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;
442 	REG_WRITE(ah, ATH_AIC_BT_JUPITER_CTRL,
443 		  (REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) &
446 	if (ar9003_aic_cal_post_process(ah))
452 static u8 ar9003_aic_cal_continue(struct ath_hw *ah, bool cal_once)
454 	struct ath_common *common = ath9k_hw_common(ah);
455 	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
456 	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;
468 			if ((REG_READ(ah, AR_PHY_AIC_CTRL_0_B1) &
480 	if ((REG_READ(ah, AR_PHY_AIC_CTRL_0_B1) &
486 	REG_WRITE(ah, AR_PHY_AIC_SRAM_ADDR_B1,
492 		value = REG_READ(ah, AR_PHY_AIC_SRAM_DATA_B1);
506 		ar9003_aic_cal_done(ah);
509 		REG_CLR_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
510 		REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1,
512 		REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
519 u8 ar9003_aic_calibration(struct ath_hw *ah)
521 	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;
526 		cal_ret = ar9003_aic_cal_start(ah, 1);
529 		cal_ret = ar9003_aic_cal_continue(ah, false);
541 u8 ar9003_aic_start_normal(struct ath_hw *ah)
543 	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;
549 	ar9003_aic_gain_table(ah);
551 	REG_WRITE(ah, AR_PHY_AIC_SRAM_ADDR_B1, ATH_AIC_SRAM_AUTO_INCREMENT);
554 		REG_WRITE(ah, AR_PHY_AIC_SRAM_DATA_B1, aic->aic_sram[i]);
558 	REG_WRITE(ah, 0xa6b0, 0x80);
559 	REG_WRITE(ah, 0xa6b4, 0x5b2df0);
560 	REG_WRITE(ah, 0xa6b8, 0x10762cc8);
561 	REG_WRITE(ah, 0xa6bc, 0x1219a4b);
562 	REG_WRITE(ah, 0xa6c0, 0x1e01);
563 	REG_WRITE(ah, 0xb6b4, 0xf0);
564 	REG_WRITE(ah, 0xb6c0, 0x1e01);
565 	REG_WRITE(ah, 0xb6b0, 0x81);
566 	REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX4, 0x40000000);
573 u8 ar9003_aic_cal_reset(struct ath_hw *ah)
575 	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;
581 u8 ar9003_aic_calibration_single(struct ath_hw *ah)
583 	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
589 	(void) ar9003_aic_cal_start(ah, num_chan);
590 	cal_ret = ar9003_aic_cal_continue(ah, true);
595 void ar9003_hw_attach_aic_ops(struct ath_hw *ah)
597 	struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);