ath/ath5k/dma.c

27  * handle queue setup for 5210 chipset (rest are handled on qcu.c).
116  * ath5k_hw_start_tx_dma() - Start DMA transmit for a specific queue
118  * @queue: The hw queue number
120  * Start DMA transmit for a specific queue and since 5210 doesn't have
121  * QCU/DCU, set up queue parameters for 5210 here based on queue type (one
122  * queue for normal data and one queue for beacons). For queue setup
123  * on newer chips check out qcu.c. Returns -EINVAL if queue number is out
124  * of range or if queue is already disabled.
127  * queue (see below).
130 ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
134 	AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
136 	/* Return if queue is declared inactive */
137 	if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
144 		 * Set the queue by type on 5210
146 		switch (ah->ah_txq[queue].tqi_type) {
163 		/* Start queue */
167 		/* Return if queue is disabled */
168 		if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue))
171 		/* Start queue */
172 		AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);
179  * ath5k_hw_stop_tx_dma() - Stop DMA transmit on a specific queue
181  * @queue: The hw queue number
183  * Stop DMA transmit on a specific hw queue and drain queue so we don't
185  * -EINVAL if queue number is out of range or inactive.
188 ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
193 	AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
195 	/* Return if queue is declared inactive */
196 	if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
203 		 * Set by queue type
205 		switch (ah->ah_txq[queue].tqi_type) {
219 		/* Stop queue */
228 		AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
232 		 * Schedule TX disable and wait until queue is empty
234 		AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);
236 		/* Wait for queue to stop */
238 		(AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue) != 0);
242 		if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
244 				"queue %i didn't stop !\n", queue);
250 				AR5K_QUEUE_STATUS(queue)) &
286 					AR5K_QUEUE_STATUS(queue)) &
297 					queue);
303 		AR5K_REG_DISABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
311 					queue, pending);
321  * ath5k_hw_stop_beacon_queue() - Stop beacon queue
323  * @queue: The queue number
325  * Returns -EIO if queue didn't stop
328 ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue)
331 	ret = ath5k_hw_stop_tx_dma(ah, queue);
334 				"beacon queue didn't stop !\n");
341  * ath5k_hw_get_txdp() - Get TX Descriptor's address for a specific queue
343  * @queue: The hw queue number
345  * Get TX descriptor's address for a specific queue. For 5210 we ignore
346  * the queue number and use tx queue type since we only have 2 queues.
347  * We use TXDP0 for normal data queue and TXDP1 for beacon queue.
353 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)
357 	AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
360 	 * Get the transmit queue descriptor pointer from the selected queue
364 		switch (ah->ah_txq[queue].tqi_type) {
376 		tx_reg = AR5K_QUEUE_TXDP(queue);
383  * ath5k_hw_set_txdp() - Set TX Descriptor's address for a specific queue
385  * @queue: The hw queue number
388  * Set TX descriptor's address for a specific queue. For 5210 we ignore
389  * the queue number and we use tx queue type since we only have 2 queues
390  * so as above we use TXDP0 for normal data queue and TXDP1 for beacon queue.
392  * Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still
396 ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
400 	AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
403 	 * Set the transmit queue descriptor pointer register by type
407 		switch (ah->ah_txq[queue].tqi_type) {
420 		 * Set the transmit queue descriptor pointer for
421 		 * the selected queue on QCU for 5211+
422 		 * (this won't work if the queue is still active)
424 		if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
427 		tx_reg = AR5K_QUEUE_TXDP(queue);
592 		 *			per-queue bits on SISR0
595 		 *			per-queue bits on SISR1
597 		 * TXURN -> Logical OR of TXURN per-queue bits on SISR2
606 		 *			QCBRURN per-queue bits on SISR3
607 		 * QTRIG -> Logical OR of QTRIG per-queue bits on SISR4
612 		 * interrupt got fired for another queue while we were reading
657 		 * so we track them all together per queue */
705 		/* A queue got CBR overrun */
709 		/* A queue got CBR underrun */
713 		/* A queue got triggered */
763 		/* Preserve per queue TXURN interrupt mask */
793 		/* Note: Per queue interrupt masks
907 		/* -EINVAL -> queue inactive */