ath/ath5k/debug.c

157 	struct ath5k_hw *ah = seq->private;
160 		ath5k_hw_reg_read(ah, r->addr));
178 	struct ath5k_hw *ah = file->private_data;
184 	v = ath5k_hw_reg_read(ah, AR5K_BEACON);
191 		"AR5K_LAST_TSTP", ath5k_hw_reg_read(ah, AR5K_LAST_TSTP));
194 		"AR5K_BEACON_CNT", ath5k_hw_reg_read(ah, AR5K_BEACON_CNT));
196 	v = ath5k_hw_reg_read(ah, AR5K_TIMER0);
200 	v = ath5k_hw_reg_read(ah, AR5K_TIMER1);
204 	v = ath5k_hw_reg_read(ah, AR5K_TIMER2);
208 	v = ath5k_hw_reg_read(ah, AR5K_TIMER3);
212 	tsf = ath5k_hw_get_tsf64(ah);
227 	struct ath5k_hw *ah = file->private_data;
236 		AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
239 		AR5K_REG_ENABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
260 	struct ath5k_hw *ah = file->private_data;
261 	ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "debug file triggered reset\n");
262 	ieee80211_queue_work(ah->hw, &ah->reset_work);
299 	struct ath5k_hw *ah = file->private_data;
305 		"DEBUG LEVEL: 0x%08x\n\n", ah->debug.level);
310 			ah->debug.level & dbg_info[i].level ? '+' : ' ',
315 		ah->debug.level == dbg_info[i].level ? '+' : ' ',
328 	struct ath5k_hw *ah = file->private_data;
340 			ah->debug.level ^= dbg_info[i].level; /* toggle bit */
361 	struct ath5k_hw *ah = file->private_data;
368 		ah->ah_ant_mode);
370 		ah->ah_def_ant);
372 		ah->ah_tx_ant);
375 	for (i = 1; i < ARRAY_SIZE(ah->stats.antenna_rx); i++) {
378 			i, ah->stats.antenna_rx[i], ah->stats.antenna_tx[i]);
381 			ah->stats.antenna_rx[0], ah->stats.antenna_tx[0]);
383 	v = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
387 	v = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
401 	v = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL);
406 	v = ath5k_hw_reg_read(ah, AR5K_PHY_RESTART);
411 	v = ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ANT_DIV);
416 	v = ath5k_hw_reg_read(ah, AR5K_PHY_ANT_SWITCH_TABLE_0);
419 	v = ath5k_hw_reg_read(ah, AR5K_PHY_ANT_SWITCH_TABLE_1);
433 	struct ath5k_hw *ah = file->private_data;
443 		ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
446 		ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_FIXED_A);
449 		ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_FIXED_B);
452 		for (i = 0; i < ARRAY_SIZE(ah->stats.antenna_rx); i++) {
453 			ah->stats.antenna_rx[i] = 0;
454 			ah->stats.antenna_tx[i] = 0;
474 	struct ath5k_hw *ah = file->private_data;
477 	u32 filt = ath5k_hw_get_rx_filter(ah);
480 			ah->bssidmask);
509 			ath_opmode_to_string(ah->opmode), ah->opmode);
529 	struct ath5k_hw *ah = file->private_data;
530 	struct ath5k_statistics *st = &ah->stats;
606 	struct ath5k_hw *ah = file->private_data;
607 	struct ath5k_statistics *st = &ah->stats;
647 	struct ath5k_hw *ah = file->private_data;
648 	struct ath5k_statistics *st = &ah->stats;
649 	struct ath5k_ani_state *as = &ah->ani_state;
656 			ah->ah_capabilities.cap_has_phyerr_counters ?
705 			(int)ewma_beacon_rssi_read(&ah->ah_beacon_rssi_avg));
737 			ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT1),
739 			ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT1)));
742 			ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT2),
744 			ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT2)));
756 	struct ath5k_hw *ah = file->private_data;
765 		ath5k_ani_init(ah, ATH5K_ANI_MODE_MANUAL_HIGH);
767 		ath5k_ani_init(ah, ATH5K_ANI_MODE_MANUAL_LOW);
769 		ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
771 		ath5k_ani_init(ah, ATH5K_ANI_MODE_AUTO);
773 		ath5k_ani_set_noise_immunity_level(ah, 0);
775 		ath5k_ani_set_noise_immunity_level(ah,
778 		ath5k_ani_set_spur_immunity_level(ah, 0);
780 		ath5k_ani_set_spur_immunity_level(ah,
781 						  ah->ani_state.max_spur_level);
783 		ath5k_ani_set_firstep_level(ah, 0);
785 		ath5k_ani_set_firstep_level(ah, ATH5K_ANI_MAX_FIRSTEP_LVL);
787 		ath5k_ani_set_ofdm_weak_signal_detection(ah, false);
789 		ath5k_ani_set_ofdm_weak_signal_detection(ah, true);
791 		ath5k_ani_set_cck_weak_signal_detection(ah, false);
793 		ath5k_ani_set_cck_weak_signal_detection(ah, true);
812 	struct ath5k_hw *ah = file->private_data;
821 			"available txbuffers: %d\n", ah->txbuf_len);
823 	for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
824 		txq = &ah->txqs[i];
854 	struct ath5k_hw *ah = file->private_data;
863 		ieee80211_wake_queues(ah->hw);
865 		ieee80211_stop_queues(ah->hw);
889 	struct ath5k_hw *ah = inode->i_private;
897 	res = ath5k_hw_nvram_read(ah, AR5K_EEPROM_SIZE_UPPER, &val);
906 		ath5k_hw_nvram_read(ah, AR5K_EEPROM_SIZE_LOWER, &val);
922 		if (!ath5k_hw_nvram_read(ah, i, &val)) {
978 ath5k_debug_init_device(struct ath5k_hw *ah)
982 	ah->debug.level = ath5k_debug;
984 	phydir = debugfs_create_dir("ath5k", ah->hw->wiphy->debugfsdir);
986 	debugfs_create_file("debug", 0600, phydir, ah, &fops_debug);
987 	debugfs_create_file("registers", 0400, phydir, ah, &registers_fops);
988 	debugfs_create_file("beacon", 0600, phydir, ah, &fops_beacon);
989 	debugfs_create_file("reset", 0200, phydir, ah, &fops_reset);
990 	debugfs_create_file("antenna", 0600, phydir, ah, &fops_antenna);
991 	debugfs_create_file("misc", 0400, phydir, ah, &fops_misc);
992 	debugfs_create_file("eeprom", 0400, phydir, ah, &fops_eeprom);
993 	debugfs_create_file("frameerrors", 0600, phydir, ah, &fops_frameerrors);
994 	debugfs_create_file("ani", 0600, phydir, ah, &fops_ani);
995 	debugfs_create_file("queue", 0600, phydir, ah, &fops_queue);
997 			    &ah->ah_use_32khz_clock);
1003 ath5k_debug_dump_bands(struct ath5k_hw *ah)
1007 	if (likely(!(ah->debug.level & ATH5K_DEBUG_DUMPBANDS)))
1011 		struct ieee80211_supported_band *band = &ah->sbands[b];
1061 ath5k_debug_printrxbuffs(struct ath5k_hw *ah)
1068 	if (likely(!(ah->debug.level & ATH5K_DEBUG_DESC)))
1072 		ath5k_hw_get_rxdp(ah), ah->rxlink);
1074 	spin_lock_bh(&ah->rxbuflock);
1075 	list_for_each_entry(bf, &ah->rxbuf, list) {
1077 		status = ah->ah_proc_rx_desc(ah, ds, &rs);
1081 	spin_unlock_bh(&ah->rxbuflock);
1085 ath5k_debug_printtxbuf(struct ath5k_hw *ah, struct ath5k_buf *bf)
1092 	if (likely(!(ah->debug.level & ATH5K_DEBUG_DESC)))
1095 	done = ah->ah_proc_tx_desc(ah, bf->desc, &ts);