ath/ath5k/attach.c

33  * @ah: The &struct ath5k_hw
35 static int ath5k_hw_post(struct ath5k_hw *ah)
54 		init_val = ath5k_hw_reg_read(ah, cur_reg);
58 			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
59 			cur_val = ath5k_hw_reg_read(ah, cur_reg);
62 				ATH5K_ERR(ah, "POST Failed !!!\n");
68 			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
73 			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
74 			cur_val = ath5k_hw_reg_read(ah, cur_reg);
77 				ATH5K_ERR(ah, "POST Failed !!!\n");
83 			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
87 		ath5k_hw_reg_write(ah, init_val, cur_reg);
97  * @ah: The &struct ath5k_hw associated with the device
104 int ath5k_hw_init(struct ath5k_hw *ah)
107 	struct ath_common *common = ath5k_hw_common(ah);
108 	struct pci_dev *pdev = ah->pdev;
116 	ah->ah_bwmode = AR5K_BWMODE_DEFAULT;
117 	ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
118 	ah->ah_imr = 0;
119 	ah->ah_retry_short = AR5K_INIT_RETRY_SHORT;
120 	ah->ah_retry_long = AR5K_INIT_RETRY_LONG;
121 	ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT;
122 	ah->ah_noise_floor = -95;	/* until first NF calibration is run */
123 	ah->ani_state.ani_mode = ATH5K_ANI_MODE_AUTO;
124 	ah->ah_current_channel = &ah->channels[0];
129 	ath5k_hw_read_srev(ah);
130 	srev = ah->ah_mac_srev;
132 		ah->ah_version = AR5K_AR5210;
134 		ah->ah_version = AR5K_AR5211;
136 		ah->ah_version = AR5K_AR5212;
139 	ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
142 	ret = ath5k_hw_init_desc_functions(ah);
147 	ret = ath5k_hw_nic_wakeup(ah, NULL);
152 	ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
154 	ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
158 	switch (ah->ah_radio_5ghz_revision & 0xf0) {
160 		ah->ah_radio = AR5K_RF5111;
161 		ah->ah_single_chip = false;
162 		ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
167 		ah->ah_radio = AR5K_RF5112;
168 		ah->ah_single_chip = false;
169 		ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
173 		ah->ah_radio = AR5K_RF2413;
174 		ah->ah_single_chip = true;
177 		ah->ah_radio = AR5K_RF5413;
178 		ah->ah_single_chip = true;
181 		ah->ah_radio = AR5K_RF2316;
182 		ah->ah_single_chip = true;
185 		ah->ah_radio = AR5K_RF2317;
186 		ah->ah_single_chip = true;
189 		if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
190 		    ah->ah_mac_version == AR5K_SREV_AR2417) {
191 			ah->ah_radio = AR5K_RF2425;
192 			ah->ah_single_chip = true;
194 			ah->ah_radio = AR5K_RF5413;
195 			ah->ah_single_chip = true;
200 		if (ah->ah_version == AR5K_AR5210) {
201 			ah->ah_radio = AR5K_RF5110;
202 			ah->ah_single_chip = false;
203 		} else if (ah->ah_version == AR5K_AR5211) {
204 			ah->ah_radio = AR5K_RF5111;
205 			ah->ah_single_chip = false;
206 			ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
208 		} else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
209 			   ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
210 			   ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
211 			ah->ah_radio = AR5K_RF2425;
212 			ah->ah_single_chip = true;
213 			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
215 			   ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
216 			ah->ah_radio = AR5K_RF5112;
217 			ah->ah_single_chip = false;
218 			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
219 		} else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4) ||
220 			   ah->ah_mac_version == (AR5K_SREV_AR2315_R6 >> 4)) {
221 			ah->ah_radio = AR5K_RF2316;
222 			ah->ah_single_chip = true;
223 			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
224 		} else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
225 			   ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
226 			ah->ah_radio = AR5K_RF5413;
227 			ah->ah_single_chip = true;
228 			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
229 		} else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
230 			   ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
231 			ah->ah_radio = AR5K_RF2413;
232 			ah->ah_single_chip = true;
233 			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
235 			ATH5K_ERR(ah, "Couldn't identify radio revision.\n");
244 		ATH5K_ERR(ah, "Device not yet supported.\n");
252 	ret = ath5k_hw_post(ah);
258 		AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX);
264 	ret = ath5k_eeprom_init(ah);
266 		ATH5K_ERR(ah, "unable to init EEPROM\n");
270 	ee = &ah->ah_capabilities.cap_eeprom;
275 	if ((ah->ah_version == AR5K_AR5212) && pdev && (pci_is_pcie(pdev))) {
276 		ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
277 		ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
280 		ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
281 		ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
287 			ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
289 			ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);
292 		ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
295 		ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
296 		ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
297 		ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
300 		ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
305 	ret = ath5k_hw_set_capabilities(ah);
307 		ATH5K_ERR(ah, "unable to get device capabilities\n");
312 	common->keymax = (ah->ah_version == AR5K_AR5210 ?
322 		AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
327 	ath5k_hw_set_lladdr(ah, zero_mac);
331 	ath5k_hw_set_bssid(ah);
332 	ath5k_hw_set_opmode(ah, ah->opmode);
334 	ath5k_hw_rfgain_opt_init(ah);
336 	ath5k_hw_init_nfcal_hist(ah);
339 	ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);
348  * @ah: The &struct ath5k_hw
350 void ath5k_hw_deinit(struct ath5k_hw *ah)
352 	__set_bit(ATH_STAT_INVALID, ah->status);
354 	kfree(ah->ah_rf_banks);
356 	ath5k_eeprom_detach(ah);