ath/ath12k/mhi.c

226 	ab_pci->mhi_ctrl->irq = irq;
227 	ab_pci->mhi_ctrl->nr_irqs = num_vectors;
307 	struct mhi_controller *mhi_ctrl;
312 	mhi_ctrl = mhi_alloc_controller();
313 	if (!mhi_ctrl)
316 	ab_pci->mhi_ctrl = mhi_ctrl;
317 	mhi_ctrl->cntrl_dev = ab->dev;
318 	mhi_ctrl->regs = ab->mem;
319 	mhi_ctrl->reg_len = ab->mem_len;
320 	mhi_ctrl->rddm_size = ab->hw_params->rddm_size;
340 			mhi_ctrl->fw_data = ab->fw.amss_dualmac_data;
341 			mhi_ctrl->fw_sz = ab->fw.amss_dualmac_len;
350 			mhi_ctrl->fw_data = ab->fw.amss_data;
351 			mhi_ctrl->fw_sz = ab->fw.amss_len;
357 			mhi_ctrl->fw_image = ab_pci->amss_path;
368 		mhi_ctrl->irq_flags = IRQF_SHARED | IRQF_NOBALANCING;
370 	mhi_ctrl->iova_start = 0;
371 	mhi_ctrl->iova_stop = 0xffffffff;
372 	mhi_ctrl->sbl_size = SZ_512K;
373 	mhi_ctrl->seg_len = SZ_512K;
374 	mhi_ctrl->fbc_download = true;
375 	mhi_ctrl->runtime_get = ath12k_mhi_op_runtime_get;
376 	mhi_ctrl->runtime_put = ath12k_mhi_op_runtime_put;
377 	mhi_ctrl->status_cb = ath12k_mhi_op_status_cb;
378 	mhi_ctrl->read_reg = ath12k_mhi_op_read_reg;
379 	mhi_ctrl->write_reg = ath12k_mhi_op_write_reg;
381 	ret = mhi_register_controller(mhi_ctrl, ab->hw_params->mhi_config);
390 	mhi_free_controller(mhi_ctrl);
391 	ab_pci->mhi_ctrl = NULL;
397 	struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl;
399 	mhi_unregister_controller(mhi_ctrl);
400 	kfree(mhi_ctrl->irq);
401 	mhi_free_controller(mhi_ctrl);
402 	ab_pci->mhi_ctrl = NULL;
537 		ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl);
540 		mhi_unprepare_after_power_down(ab_pci->mhi_ctrl);
555 		ret = mhi_sync_power_up(ab_pci->mhi_ctrl);
558 		mhi_power_down(ab_pci->mhi_ctrl, true);
562 		mhi_power_down_keep_dev(ab_pci->mhi_ctrl, true);
566 		mhi_power_down(ab_pci->mhi_ctrl, false);
570 		ret = mhi_pm_suspend(ab_pci->mhi_ctrl);
573 		ret = mhi_pm_resume(ab_pci->mhi_ctrl);
576 		ret = mhi_force_rddm_mode(ab_pci->mhi_ctrl);
602 	ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS;